mirror of
https://gitlab.winehq.org/wine/wine.git
synced 2025-08-29 10:43:55 +02:00
26589 lines
902 KiB
C++
26589 lines
902 KiB
C++
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Assembly Writer Source Fragment *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/// getMnemonic - This method is automatically generated by tablegen
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/// from the instruction set description.
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static uint64_t getMnemonic(MCInst *MI, SStream *O, unsigned int opcode) {
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#ifdef __GNUC__
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Woverlength-strings"
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#endif
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ "sha1su0\t\0"
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/* 9 */ "sha512su0\t\0"
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/* 20 */ "sha256su0\t\0"
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/* 31 */ "st64bv0\t\0"
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/* 40 */ "ld1\t\0"
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/* 45 */ "trn1\t\0"
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/* 51 */ "zip1\t\0"
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/* 57 */ "uzp1\t\0"
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/* 63 */ "dcps1\t\0"
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/* 70 */ "sm3ss1\t\0"
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/* 78 */ "st1\t\0"
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/* 83 */ "sha1su1\t\0"
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/* 92 */ "sha512su1\t\0"
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/* 103 */ "sha256su1\t\0"
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/* 114 */ "sm3partw1\t\0"
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/* 125 */ "rax1\t\0"
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/* 131 */ "rev32\t\0"
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/* 138 */ "ld2\t\0"
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/* 143 */ "sha512h2\t\0"
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/* 153 */ "sha256h2\t\0"
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/* 163 */ "sabal2\t\0"
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/* 171 */ "uabal2\t\0"
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/* 179 */ "sqdmlal2\t\0"
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/* 189 */ "fmlal2\t\0"
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/* 197 */ "smlal2\t\0"
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/* 205 */ "umlal2\t\0"
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/* 213 */ "ssubl2\t\0"
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/* 221 */ "usubl2\t\0"
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/* 229 */ "sabdl2\t\0"
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/* 237 */ "uabdl2\t\0"
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/* 245 */ "saddl2\t\0"
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/* 253 */ "uaddl2\t\0"
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/* 261 */ "sshll2\t\0"
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/* 269 */ "ushll2\t\0"
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/* 277 */ "sqdmull2\t\0"
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/* 287 */ "pmull2\t\0"
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/* 295 */ "smull2\t\0"
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/* 303 */ "umull2\t\0"
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/* 311 */ "sqdmlsl2\t\0"
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/* 321 */ "fmlsl2\t\0"
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/* 329 */ "smlsl2\t\0"
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/* 337 */ "umlsl2\t\0"
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/* 345 */ "fcvtl2\t\0"
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/* 353 */ "rsubhn2\t\0"
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/* 362 */ "raddhn2\t\0"
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/* 371 */ "sqshrn2\t\0"
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/* 380 */ "uqshrn2\t\0"
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/* 389 */ "sqrshrn2\t\0"
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/* 399 */ "uqrshrn2\t\0"
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/* 409 */ "trn2\t\0"
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/* 415 */ "bfcvtn2\t\0"
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/* 424 */ "sqxtn2\t\0"
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/* 432 */ "uqxtn2\t\0"
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/* 440 */ "sqshrun2\t\0"
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/* 450 */ "sqrshrun2\t\0"
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/* 461 */ "sqxtun2\t\0"
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/* 470 */ "fcvtxn2\t\0"
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/* 479 */ "zip2\t\0"
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/* 485 */ "uzp2\t\0"
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/* 491 */ "dcps2\t\0"
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/* 498 */ "st2\t\0"
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/* 503 */ "ssubw2\t\0"
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/* 511 */ "usubw2\t\0"
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/* 519 */ "saddw2\t\0"
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/* 527 */ "uaddw2\t\0"
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/* 535 */ "sm3partw2\t\0"
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/* 546 */ "ld3\t\0"
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/* 551 */ "eor3\t\0"
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/* 557 */ "dcps3\t\0"
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/* 564 */ "st3\t\0"
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/* 569 */ "rev64\t\0"
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/* 576 */ "ld4\t\0"
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/* 581 */ "st4\t\0"
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/* 586 */ "setf16\t\0"
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/* 594 */ "rev16\t\0"
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/* 601 */ "setf8\t\0"
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/* 608 */ "sm3tt1a\t\0"
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/* 617 */ "sm3tt2a\t\0"
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/* 626 */ "braa\t\0"
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/* 632 */ "ldraa\t\0"
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/* 639 */ "blraa\t\0"
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/* 646 */ "saba\t\0"
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/* 652 */ "uaba\t\0"
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/* 658 */ "pacda\t\0"
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/* 665 */ "ldadda\t\0"
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/* 673 */ "fadda\t\0"
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/* 680 */ "autda\t\0"
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/* 687 */ "pacga\t\0"
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/* 694 */ "addha\t\0"
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/* 701 */ "pacia\t\0"
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/* 708 */ "autia\t\0"
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/* 715 */ "brka\t\0"
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/* 721 */ "fcmla\t\0"
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/* 728 */ "fmla\t\0"
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/* 734 */ "bfmmla\t\0"
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/* 742 */ "usmmla\t\0"
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/* 750 */ "ummla\t\0"
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/* 757 */ "fnmla\t\0"
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/* 764 */ "ldsmina\t\0"
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/* 773 */ "ldumina\t\0"
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/* 782 */ "brkpa\t\0"
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/* 789 */ "bfmopa\t\0"
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/* 797 */ "usmopa\t\0"
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/* 805 */ "sumopa\t\0"
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/* 813 */ "caspa\t\0"
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/* 820 */ "swpa\t\0"
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/* 826 */ "fexpa\t\0"
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/* 833 */ "ldclra\t\0"
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/* 841 */ "ldeora\t\0"
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/* 849 */ "srsra\t\0"
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/* 856 */ "ursra\t\0"
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/* 863 */ "ssra\t\0"
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/* 869 */ "usra\t\0"
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/* 875 */ "casa\t\0"
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/* 881 */ "ldseta\t\0"
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/* 889 */ "frinta\t\0"
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/* 897 */ "clasta\t\0"
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/* 905 */ "addva\t\0"
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/* 912 */ "mova\t\0"
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/* 918 */ "ldsmaxa\t\0"
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/* 927 */ "ldumaxa\t\0"
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/* 936 */ "pacdza\t\0"
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/* 944 */ "autdza\t\0"
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/* 952 */ "paciza\t\0"
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/* 960 */ "autiza\t\0"
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/* 968 */ "ld1b\t\0"
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/* 974 */ "ldff1b\t\0"
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/* 982 */ "ldnf1b\t\0"
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/* 990 */ "ldnt1b\t\0"
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/* 998 */ "stnt1b\t\0"
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/* 1006 */ "st1b\t\0"
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/* 1012 */ "sm3tt1b\t\0"
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/* 1021 */ "crc32b\t\0"
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/* 1029 */ "ld2b\t\0"
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/* 1035 */ "st2b\t\0"
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/* 1041 */ "sm3tt2b\t\0"
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/* 1050 */ "ld3b\t\0"
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/* 1056 */ "st3b\t\0"
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/* 1062 */ "ld64b\t\0"
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/* 1069 */ "st64b\t\0"
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/* 1076 */ "ld4b\t\0"
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/* 1082 */ "st4b\t\0"
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/* 1088 */ "ldaddab\t\0"
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/* 1097 */ "ldsminab\t\0"
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/* 1107 */ "lduminab\t\0"
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/* 1117 */ "swpab\t\0"
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/* 1124 */ "brab\t\0"
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/* 1130 */ "ldrab\t\0"
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/* 1137 */ "blrab\t\0"
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/* 1144 */ "ldclrab\t\0"
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/* 1153 */ "ldeorab\t\0"
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/* 1162 */ "casab\t\0"
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/* 1169 */ "ldsetab\t\0"
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/* 1178 */ "ldsmaxab\t\0"
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/* 1188 */ "ldumaxab\t\0"
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/* 1198 */ "crc32cb\t\0"
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/* 1207 */ "sqdecb\t\0"
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/* 1215 */ "uqdecb\t\0"
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/* 1223 */ "sqincb\t\0"
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/* 1231 */ "uqincb\t\0"
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/* 1239 */ "pacdb\t\0"
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/* 1246 */ "ldaddb\t\0"
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/* 1254 */ "autdb\t\0"
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/* 1261 */ "prfb\t\0"
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/* 1267 */ "flogb\t\0"
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/* 1274 */ "pacib\t\0"
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/* 1281 */ "autib\t\0"
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/* 1288 */ "brkb\t\0"
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/* 1294 */ "sabalb\t\0"
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/* 1302 */ "uabalb\t\0"
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/* 1310 */ "ldaddalb\t\0"
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/* 1320 */ "sqdmlalb\t\0"
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/* 1330 */ "bfmlalb\t\0"
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/* 1339 */ "smlalb\t\0"
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/* 1347 */ "umlalb\t\0"
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/* 1355 */ "ldsminalb\t\0"
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/* 1366 */ "lduminalb\t\0"
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/* 1377 */ "swpalb\t\0"
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/* 1385 */ "ldclralb\t\0"
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/* 1395 */ "ldeoralb\t\0"
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/* 1405 */ "casalb\t\0"
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/* 1413 */ "ldsetalb\t\0"
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/* 1423 */ "ldsmaxalb\t\0"
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/* 1434 */ "ldumaxalb\t\0"
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/* 1445 */ "ssublb\t\0"
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/* 1453 */ "usublb\t\0"
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/* 1461 */ "sbclb\t\0"
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/* 1468 */ "adclb\t\0"
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/* 1475 */ "sabdlb\t\0"
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/* 1483 */ "uabdlb\t\0"
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/* 1491 */ "ldaddlb\t\0"
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/* 1500 */ "saddlb\t\0"
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/* 1508 */ "uaddlb\t\0"
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/* 1516 */ "sshllb\t\0"
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/* 1524 */ "ushllb\t\0"
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/* 1532 */ "sqdmullb\t\0"
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/* 1542 */ "pmullb\t\0"
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/* 1550 */ "smullb\t\0"
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/* 1558 */ "umullb\t\0"
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/* 1566 */ "ldsminlb\t\0"
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/* 1576 */ "lduminlb\t\0"
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/* 1586 */ "swplb\t\0"
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/* 1593 */ "ldclrlb\t\0"
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/* 1602 */ "ldeorlb\t\0"
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/* 1611 */ "caslb\t\0"
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/* 1618 */ "sqdmlslb\t\0"
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/* 1628 */ "fmlslb\t\0"
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/* 1636 */ "smlslb\t\0"
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/* 1644 */ "umlslb\t\0"
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/* 1652 */ "ldsetlb\t\0"
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/* 1661 */ "ldsmaxlb\t\0"
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/* 1671 */ "ldumaxlb\t\0"
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/* 1681 */ "dmb\t\0"
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/* 1686 */ "rsubhnb\t\0"
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/* 1695 */ "raddhnb\t\0"
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/* 1704 */ "ldsminb\t\0"
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/* 1713 */ "lduminb\t\0"
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/* 1722 */ "sqshrnb\t\0"
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/* 1731 */ "uqshrnb\t\0"
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/* 1740 */ "sqrshrnb\t\0"
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/* 1750 */ "uqrshrnb\t\0"
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/* 1760 */ "sqxtnb\t\0"
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/* 1768 */ "uqxtnb\t\0"
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/* 1776 */ "sqshrunb\t\0"
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/* 1786 */ "sqrshrunb\t\0"
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/* 1797 */ "sqxtunb\t\0"
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/* 1806 */ "ld1rob\t\0"
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/* 1814 */ "brkpb\t\0"
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/* 1821 */ "swpb\t\0"
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/* 1827 */ "ld1rqb\t\0"
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/* 1835 */ "ld1rb\t\0"
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/* 1842 */ "ldarb\t\0"
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/* 1849 */ "ldlarb\t\0"
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/* 1857 */ "ldrb\t\0"
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/* 1863 */ "ldclrb\t\0"
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/* 1871 */ "stllrb\t\0"
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/* 1879 */ "stlrb\t\0"
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/* 1886 */ "ldeorb\t\0"
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/* 1894 */ "ldaprb\t\0"
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/* 1902 */ "ldtrb\t\0"
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/* 1909 */ "strb\t\0"
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/* 1915 */ "sttrb\t\0"
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/* 1922 */ "ldurb\t\0"
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/* 1929 */ "stlurb\t\0"
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/* 1937 */ "ldapurb\t\0"
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/* 1946 */ "sturb\t\0"
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/* 1953 */ "ldaxrb\t\0"
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/* 1961 */ "ldxrb\t\0"
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/* 1968 */ "stlxrb\t\0"
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/* 1976 */ "stxrb\t\0"
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/* 1983 */ "ld1sb\t\0"
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/* 1990 */ "ldff1sb\t\0"
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/* 1999 */ "ldnf1sb\t\0"
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/* 2008 */ "ldnt1sb\t\0"
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/* 2017 */ "casb\t\0"
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/* 2023 */ "dsb\t\0"
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/* 2028 */ "isb\t\0"
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/* 2033 */ "fmsb\t\0"
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/* 2039 */ "fnmsb\t\0"
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/* 2046 */ "ld1rsb\t\0"
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/* 2054 */ "ldrsb\t\0"
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/* 2061 */ "ldtrsb\t\0"
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/* 2069 */ "ldursb\t\0"
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/* 2077 */ "ldapursb\t\0"
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/* 2087 */ "tsb\t\0"
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/* 2092 */ "ldsetb\t\0"
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/* 2100 */ "ssubltb\t\0"
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/* 2109 */ "cntb\t\0"
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/* 2115 */ "eortb\t\0"
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/* 2122 */ "clastb\t\0"
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/* 2130 */ "sxtb\t\0"
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/* 2136 */ "uxtb\t\0"
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/* 2142 */ "fsub\t\0"
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/* 2148 */ "shsub\t\0"
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/* 2155 */ "uhsub\t\0"
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/* 2162 */ "fmsub\t\0"
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/* 2169 */ "fnmsub\t\0"
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/* 2177 */ "sqsub\t\0"
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/* 2184 */ "uqsub\t\0"
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/* 2191 */ "revb\t\0"
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/* 2197 */ "ssubwb\t\0"
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/* 2205 */ "usubwb\t\0"
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/* 2213 */ "saddwb\t\0"
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/* 2221 */ "uaddwb\t\0"
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/* 2229 */ "ldsmaxb\t\0"
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/* 2238 */ "ldumaxb\t\0"
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/* 2247 */ "pacdzb\t\0"
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/* 2255 */ "autdzb\t\0"
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/* 2263 */ "pacizb\t\0"
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/* 2271 */ "autizb\t\0"
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/* 2279 */ "sha1c\t\0"
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/* 2286 */ "sbc\t\0"
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/* 2291 */ "adc\t\0"
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/* 2296 */ "bic\t\0"
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/* 2301 */ "aesimc\t\0"
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/* 2309 */ "aesmc\t\0"
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/* 2316 */ "csinc\t\0"
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/* 2323 */ "hvc\t\0"
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/* 2328 */ "svc\t\0"
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/* 2333 */ "ld1d\t\0"
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/* 2339 */ "ldff1d\t\0"
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/* 2347 */ "ldnf1d\t\0"
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|
/* 2355 */ "ldnt1d\t\0"
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|
/* 2363 */ "stnt1d\t\0"
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|
/* 2371 */ "st1d\t\0"
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|
/* 2377 */ "ld2d\t\0"
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|
/* 2383 */ "st2d\t\0"
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|
/* 2389 */ "ld3d\t\0"
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|
/* 2395 */ "st3d\t\0"
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|
/* 2401 */ "ld4d\t\0"
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|
/* 2407 */ "st4d\t\0"
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|
/* 2413 */ "fmad\t\0"
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|
/* 2419 */ "fnmad\t\0"
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/* 2426 */ "ftmad\t\0"
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/* 2433 */ "fabd\t\0"
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/* 2439 */ "sabd\t\0"
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/* 2445 */ "uabd\t\0"
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|
/* 2451 */ "xpacd\t\0"
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|
/* 2458 */ "sqdecd\t\0"
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|
/* 2466 */ "uqdecd\t\0"
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|
/* 2474 */ "sqincd\t\0"
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|
/* 2482 */ "uqincd\t\0"
|
|
/* 2490 */ "fcadd\t\0"
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|
/* 2497 */ "sqcadd\t\0"
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|
/* 2505 */ "ldadd\t\0"
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|
/* 2512 */ "fadd\t\0"
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/* 2518 */ "srhadd\t\0"
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|
/* 2526 */ "urhadd\t\0"
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|
/* 2534 */ "shadd\t\0"
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|
/* 2541 */ "uhadd\t\0"
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|
/* 2548 */ "fmadd\t\0"
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|
/* 2555 */ "fnmadd\t\0"
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/* 2563 */ "usqadd\t\0"
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|
/* 2571 */ "suqadd\t\0"
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|
/* 2579 */ "prfd\t\0"
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|
/* 2585 */ "nand\t\0"
|
|
/* 2591 */ "ld1rod\t\0"
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|
/* 2599 */ "ld1rqd\t\0"
|
|
/* 2607 */ "ld1rd\t\0"
|
|
/* 2614 */ "asrd\t\0"
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|
/* 2620 */ "aesd\t\0"
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|
/* 2626 */ "cntd\t\0"
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|
/* 2632 */ "revd\t\0"
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|
/* 2638 */ "sm4e\t\0"
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|
/* 2644 */ "splice\t\0"
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|
/* 2652 */ "facge\t\0"
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|
/* 2659 */ "whilege\t\0"
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/* 2668 */ "fcmge\t\0"
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|
/* 2675 */ "cmpge\t\0"
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/* 2682 */ "fscale\t\0"
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|
/* 2690 */ "whilele\t\0"
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/* 2699 */ "fcmle\t\0"
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/* 2706 */ "cmple\t\0"
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/* 2713 */ "fcmne\t\0"
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/* 2720 */ "ctermne\t\0"
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|
/* 2729 */ "cmpne\t\0"
|
|
/* 2736 */ "frecpe\t\0"
|
|
/* 2744 */ "urecpe\t\0"
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|
/* 2752 */ "fccmpe\t\0"
|
|
/* 2760 */ "fcmpe\t\0"
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|
/* 2767 */ "aese\t\0"
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|
/* 2773 */ "pfalse\t\0"
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|
/* 2781 */ "frsqrte\t\0"
|
|
/* 2790 */ "ursqrte\t\0"
|
|
/* 2799 */ "ptrue\t\0"
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|
/* 2806 */ "udf\t\0"
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|
/* 2811 */ "bif\t\0"
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/* 2816 */ "rmif\t\0"
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|
/* 2822 */ "scvtf\t\0"
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/* 2829 */ "ucvtf\t\0"
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/* 2836 */ "st2g\t\0"
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/* 2842 */ "stz2g\t\0"
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/* 2849 */ "subg\t\0"
|
|
/* 2855 */ "addg\t\0"
|
|
/* 2861 */ "ldg\t\0"
|
|
/* 2866 */ "fneg\t\0"
|
|
/* 2872 */ "sqneg\t\0"
|
|
/* 2879 */ "csneg\t\0"
|
|
/* 2886 */ "histseg\t\0"
|
|
/* 2895 */ "irg\t\0"
|
|
/* 2900 */ "stg\t\0"
|
|
/* 2905 */ "stzg\t\0"
|
|
/* 2911 */ "sha1h\t\0"
|
|
/* 2918 */ "ld1h\t\0"
|
|
/* 2924 */ "ldff1h\t\0"
|
|
/* 2932 */ "ldnf1h\t\0"
|
|
/* 2940 */ "ldnt1h\t\0"
|
|
/* 2948 */ "stnt1h\t\0"
|
|
/* 2956 */ "st1h\t\0"
|
|
/* 2962 */ "sha512h\t\0"
|
|
/* 2971 */ "crc32h\t\0"
|
|
/* 2979 */ "ld2h\t\0"
|
|
/* 2985 */ "st2h\t\0"
|
|
/* 2991 */ "ld3h\t\0"
|
|
/* 2997 */ "st3h\t\0"
|
|
/* 3003 */ "ld4h\t\0"
|
|
/* 3009 */ "st4h\t\0"
|
|
/* 3015 */ "sha256h\t\0"
|
|
/* 3024 */ "ldaddah\t\0"
|
|
/* 3033 */ "sqrdcmlah\t\0"
|
|
/* 3044 */ "sqrdmlah\t\0"
|
|
/* 3054 */ "ldsminah\t\0"
|
|
/* 3064 */ "lduminah\t\0"
|
|
/* 3074 */ "swpah\t\0"
|
|
/* 3081 */ "ldclrah\t\0"
|
|
/* 3090 */ "ldeorah\t\0"
|
|
/* 3099 */ "casah\t\0"
|
|
/* 3106 */ "ldsetah\t\0"
|
|
/* 3115 */ "ldsmaxah\t\0"
|
|
/* 3125 */ "ldumaxah\t\0"
|
|
/* 3135 */ "crc32ch\t\0"
|
|
/* 3144 */ "sqdech\t\0"
|
|
/* 3152 */ "uqdech\t\0"
|
|
/* 3160 */ "sqinch\t\0"
|
|
/* 3168 */ "uqinch\t\0"
|
|
/* 3176 */ "nmatch\t\0"
|
|
/* 3184 */ "ldaddh\t\0"
|
|
/* 3192 */ "prfh\t\0"
|
|
/* 3198 */ "ldaddalh\t\0"
|
|
/* 3208 */ "ldsminalh\t\0"
|
|
/* 3219 */ "lduminalh\t\0"
|
|
/* 3230 */ "swpalh\t\0"
|
|
/* 3238 */ "ldclralh\t\0"
|
|
/* 3248 */ "ldeoralh\t\0"
|
|
/* 3258 */ "casalh\t\0"
|
|
/* 3266 */ "ldsetalh\t\0"
|
|
/* 3276 */ "ldsmaxalh\t\0"
|
|
/* 3287 */ "ldumaxalh\t\0"
|
|
/* 3298 */ "ldaddlh\t\0"
|
|
/* 3307 */ "ldsminlh\t\0"
|
|
/* 3317 */ "lduminlh\t\0"
|
|
/* 3327 */ "swplh\t\0"
|
|
/* 3334 */ "ldclrlh\t\0"
|
|
/* 3343 */ "ldeorlh\t\0"
|
|
/* 3352 */ "caslh\t\0"
|
|
/* 3359 */ "ldsetlh\t\0"
|
|
/* 3368 */ "sqdmulh\t\0"
|
|
/* 3377 */ "sqrdmulh\t\0"
|
|
/* 3387 */ "smulh\t\0"
|
|
/* 3394 */ "umulh\t\0"
|
|
/* 3401 */ "ldsmaxlh\t\0"
|
|
/* 3411 */ "ldumaxlh\t\0"
|
|
/* 3421 */ "ldsminh\t\0"
|
|
/* 3430 */ "lduminh\t\0"
|
|
/* 3439 */ "ld1roh\t\0"
|
|
/* 3447 */ "swph\t\0"
|
|
/* 3453 */ "ld1rqh\t\0"
|
|
/* 3461 */ "ld1rh\t\0"
|
|
/* 3468 */ "ldarh\t\0"
|
|
/* 3475 */ "ldlarh\t\0"
|
|
/* 3483 */ "ldrh\t\0"
|
|
/* 3489 */ "ldclrh\t\0"
|
|
/* 3497 */ "stllrh\t\0"
|
|
/* 3505 */ "stlrh\t\0"
|
|
/* 3512 */ "ldeorh\t\0"
|
|
/* 3520 */ "ldaprh\t\0"
|
|
/* 3528 */ "ldtrh\t\0"
|
|
/* 3535 */ "strh\t\0"
|
|
/* 3541 */ "sttrh\t\0"
|
|
/* 3548 */ "ldurh\t\0"
|
|
/* 3555 */ "stlurh\t\0"
|
|
/* 3563 */ "ldapurh\t\0"
|
|
/* 3572 */ "sturh\t\0"
|
|
/* 3579 */ "ldaxrh\t\0"
|
|
/* 3587 */ "ldxrh\t\0"
|
|
/* 3594 */ "stlxrh\t\0"
|
|
/* 3602 */ "stxrh\t\0"
|
|
/* 3609 */ "ld1sh\t\0"
|
|
/* 3616 */ "ldff1sh\t\0"
|
|
/* 3625 */ "ldnf1sh\t\0"
|
|
/* 3634 */ "ldnt1sh\t\0"
|
|
/* 3643 */ "cash\t\0"
|
|
/* 3649 */ "sqrdmlsh\t\0"
|
|
/* 3659 */ "ld1rsh\t\0"
|
|
/* 3667 */ "ldrsh\t\0"
|
|
/* 3674 */ "ldtrsh\t\0"
|
|
/* 3682 */ "ldursh\t\0"
|
|
/* 3690 */ "ldapursh\t\0"
|
|
/* 3700 */ "ldseth\t\0"
|
|
/* 3708 */ "cnth\t\0"
|
|
/* 3714 */ "sxth\t\0"
|
|
/* 3720 */ "uxth\t\0"
|
|
/* 3726 */ "revh\t\0"
|
|
/* 3732 */ "ldsmaxh\t\0"
|
|
/* 3741 */ "ldumaxh\t\0"
|
|
/* 3750 */ "xpaci\t\0"
|
|
/* 3757 */ "whilehi\t\0"
|
|
/* 3766 */ "punpkhi\t\0"
|
|
/* 3775 */ "sunpkhi\t\0"
|
|
/* 3784 */ "uunpkhi\t\0"
|
|
/* 3793 */ "cmhi\t\0"
|
|
/* 3799 */ "cmphi\t\0"
|
|
/* 3806 */ "sli\t\0"
|
|
/* 3811 */ "gmi\t\0"
|
|
/* 3816 */ "mvni\t\0"
|
|
/* 3822 */ "sri\t\0"
|
|
/* 3827 */ "frinti\t\0"
|
|
/* 3835 */ "movi\t\0"
|
|
/* 3841 */ "brk\t\0"
|
|
/* 3846 */ "movk\t\0"
|
|
/* 3852 */ "sabal\t\0"
|
|
/* 3859 */ "uabal\t\0"
|
|
/* 3866 */ "ldaddal\t\0"
|
|
/* 3875 */ "sqdmlal\t\0"
|
|
/* 3884 */ "fmlal\t\0"
|
|
/* 3891 */ "smlal\t\0"
|
|
/* 3898 */ "umlal\t\0"
|
|
/* 3905 */ "ldsminal\t\0"
|
|
/* 3915 */ "lduminal\t\0"
|
|
/* 3925 */ "caspal\t\0"
|
|
/* 3933 */ "swpal\t\0"
|
|
/* 3940 */ "ldclral\t\0"
|
|
/* 3949 */ "ldeoral\t\0"
|
|
/* 3958 */ "casal\t\0"
|
|
/* 3965 */ "ldsetal\t\0"
|
|
/* 3974 */ "ldsmaxal\t\0"
|
|
/* 3984 */ "ldumaxal\t\0"
|
|
/* 3994 */ "tbl\t\0"
|
|
/* 3999 */ "smsubl\t\0"
|
|
/* 4007 */ "umsubl\t\0"
|
|
/* 4015 */ "ssubl\t\0"
|
|
/* 4022 */ "usubl\t\0"
|
|
/* 4029 */ "sabdl\t\0"
|
|
/* 4036 */ "uabdl\t\0"
|
|
/* 4043 */ "ldaddl\t\0"
|
|
/* 4051 */ "smaddl\t\0"
|
|
/* 4059 */ "umaddl\t\0"
|
|
/* 4067 */ "saddl\t\0"
|
|
/* 4074 */ "uaddl\t\0"
|
|
/* 4081 */ "tcancel\t\0"
|
|
/* 4090 */ "fcsel\t\0"
|
|
/* 4097 */ "psel\t\0"
|
|
/* 4103 */ "ftssel\t\0"
|
|
/* 4111 */ "sqshl\t\0"
|
|
/* 4118 */ "uqshl\t\0"
|
|
/* 4125 */ "sqrshl\t\0"
|
|
/* 4133 */ "uqrshl\t\0"
|
|
/* 4141 */ "srshl\t\0"
|
|
/* 4148 */ "urshl\t\0"
|
|
/* 4155 */ "sshl\t\0"
|
|
/* 4161 */ "ushl\t\0"
|
|
/* 4167 */ "sshll\t\0"
|
|
/* 4174 */ "ushll\t\0"
|
|
/* 4181 */ "sqdmull\t\0"
|
|
/* 4190 */ "pmull\t\0"
|
|
/* 4197 */ "smull\t\0"
|
|
/* 4204 */ "umull\t\0"
|
|
/* 4211 */ "ldsminl\t\0"
|
|
/* 4220 */ "lduminl\t\0"
|
|
/* 4229 */ "addpl\t\0"
|
|
/* 4236 */ "caspl\t\0"
|
|
/* 4243 */ "swpl\t\0"
|
|
/* 4249 */ "ldclrl\t\0"
|
|
/* 4257 */ "ldeorl\t\0"
|
|
/* 4265 */ "casl\t\0"
|
|
/* 4271 */ "nbsl\t\0"
|
|
/* 4277 */ "sqdmlsl\t\0"
|
|
/* 4286 */ "fmlsl\t\0"
|
|
/* 4293 */ "smlsl\t\0"
|
|
/* 4300 */ "umlsl\t\0"
|
|
/* 4307 */ "sysl\t\0"
|
|
/* 4313 */ "ldsetl\t\0"
|
|
/* 4321 */ "fcvtl\t\0"
|
|
/* 4328 */ "fmul\t\0"
|
|
/* 4334 */ "fnmul\t\0"
|
|
/* 4341 */ "pmul\t\0"
|
|
/* 4347 */ "ftsmul\t\0"
|
|
/* 4355 */ "addvl\t\0"
|
|
/* 4362 */ "rdvl\t\0"
|
|
/* 4368 */ "ldsmaxl\t\0"
|
|
/* 4377 */ "ldumaxl\t\0"
|
|
/* 4386 */ "sha1m\t\0"
|
|
/* 4393 */ "sbfm\t\0"
|
|
/* 4399 */ "ubfm\t\0"
|
|
/* 4405 */ "prfm\t\0"
|
|
/* 4411 */ "ldgm\t\0"
|
|
/* 4417 */ "stgm\t\0"
|
|
/* 4423 */ "stzgm\t\0"
|
|
/* 4430 */ "fminnm\t\0"
|
|
/* 4438 */ "fmaxnm\t\0"
|
|
/* 4446 */ "dupm\t\0"
|
|
/* 4452 */ "frintm\t\0"
|
|
/* 4460 */ "prfum\t\0"
|
|
/* 4467 */ "bsl1n\t\0"
|
|
/* 4474 */ "bsl2n\t\0"
|
|
/* 4481 */ "rsubhn\t\0"
|
|
/* 4489 */ "raddhn\t\0"
|
|
/* 4497 */ "fmin\t\0"
|
|
/* 4503 */ "ldsmin\t\0"
|
|
/* 4511 */ "ldumin\t\0"
|
|
/* 4519 */ "brkn\t\0"
|
|
/* 4525 */ "ccmn\t\0"
|
|
/* 4531 */ "eon\t\0"
|
|
/* 4536 */ "sqshrn\t\0"
|
|
/* 4544 */ "uqshrn\t\0"
|
|
/* 4552 */ "sqrshrn\t\0"
|
|
/* 4561 */ "uqrshrn\t\0"
|
|
/* 4570 */ "orn\t\0"
|
|
/* 4575 */ "frintn\t\0"
|
|
/* 4583 */ "bfcvtn\t\0"
|
|
/* 4591 */ "sqxtn\t\0"
|
|
/* 4598 */ "uqxtn\t\0"
|
|
/* 4605 */ "sqshrun\t\0"
|
|
/* 4614 */ "sqrshrun\t\0"
|
|
/* 4624 */ "sqxtun\t\0"
|
|
/* 4632 */ "movn\t\0"
|
|
/* 4638 */ "fcvtxn\t\0"
|
|
/* 4646 */ "whilelo\t\0"
|
|
/* 4655 */ "punpklo\t\0"
|
|
/* 4664 */ "sunpklo\t\0"
|
|
/* 4673 */ "uunpklo\t\0"
|
|
/* 4682 */ "cmplo\t\0"
|
|
/* 4689 */ "zero\t\0"
|
|
/* 4695 */ "fcmuo\t\0"
|
|
/* 4702 */ "sha1p\t\0"
|
|
/* 4709 */ "subp\t\0"
|
|
/* 4715 */ "sqdecp\t\0"
|
|
/* 4723 */ "uqdecp\t\0"
|
|
/* 4731 */ "sqincp\t\0"
|
|
/* 4739 */ "uqincp\t\0"
|
|
/* 4747 */ "faddp\t\0"
|
|
/* 4754 */ "ldp\t\0"
|
|
/* 4759 */ "bdep\t\0"
|
|
/* 4765 */ "stgp\t\0"
|
|
/* 4771 */ "sadalp\t\0"
|
|
/* 4779 */ "uadalp\t\0"
|
|
/* 4787 */ "saddlp\t\0"
|
|
/* 4795 */ "uaddlp\t\0"
|
|
/* 4803 */ "sclamp\t\0"
|
|
/* 4811 */ "uclamp\t\0"
|
|
/* 4819 */ "fccmp\t\0"
|
|
/* 4826 */ "fcmp\t\0"
|
|
/* 4832 */ "fminnmp\t\0"
|
|
/* 4841 */ "fmaxnmp\t\0"
|
|
/* 4850 */ "ldnp\t\0"
|
|
/* 4856 */ "fminp\t\0"
|
|
/* 4863 */ "sminp\t\0"
|
|
/* 4870 */ "uminp\t\0"
|
|
/* 4877 */ "stnp\t\0"
|
|
/* 4883 */ "adrp\t\0"
|
|
/* 4889 */ "bgrp\t\0"
|
|
/* 4895 */ "casp\t\0"
|
|
/* 4901 */ "cntp\t\0"
|
|
/* 4907 */ "frintp\t\0"
|
|
/* 4915 */ "stp\t\0"
|
|
/* 4920 */ "fdup\t\0"
|
|
/* 4926 */ "swp\t\0"
|
|
/* 4931 */ "ldaxp\t\0"
|
|
/* 4938 */ "fmaxp\t\0"
|
|
/* 4945 */ "smaxp\t\0"
|
|
/* 4952 */ "umaxp\t\0"
|
|
/* 4959 */ "ldxp\t\0"
|
|
/* 4965 */ "stlxp\t\0"
|
|
/* 4972 */ "stxp\t\0"
|
|
/* 4978 */ "fcmeq\t\0"
|
|
/* 4985 */ "ctermeq\t\0"
|
|
/* 4994 */ "cmpeq\t\0"
|
|
/* 5001 */ "ld1r\t\0"
|
|
/* 5007 */ "ld2r\t\0"
|
|
/* 5013 */ "ld3r\t\0"
|
|
/* 5019 */ "ld4r\t\0"
|
|
/* 5025 */ "ldar\t\0"
|
|
/* 5031 */ "ldlar\t\0"
|
|
/* 5038 */ "xar\t\0"
|
|
/* 5043 */ "fsubr\t\0"
|
|
/* 5050 */ "shsubr\t\0"
|
|
/* 5058 */ "uhsubr\t\0"
|
|
/* 5066 */ "sqsubr\t\0"
|
|
/* 5074 */ "uqsubr\t\0"
|
|
/* 5082 */ "adr\t\0"
|
|
/* 5087 */ "ldr\t\0"
|
|
/* 5092 */ "rdffr\t\0"
|
|
/* 5099 */ "wrffr\t\0"
|
|
/* 5106 */ "srshr\t\0"
|
|
/* 5113 */ "urshr\t\0"
|
|
/* 5120 */ "sshr\t\0"
|
|
/* 5126 */ "ushr\t\0"
|
|
/* 5132 */ "blr\t\0"
|
|
/* 5137 */ "ldclr\t\0"
|
|
/* 5144 */ "sqshlr\t\0"
|
|
/* 5152 */ "uqshlr\t\0"
|
|
/* 5160 */ "sqrshlr\t\0"
|
|
/* 5169 */ "uqrshlr\t\0"
|
|
/* 5178 */ "srshlr\t\0"
|
|
/* 5186 */ "urshlr\t\0"
|
|
/* 5194 */ "stllr\t\0"
|
|
/* 5201 */ "lslr\t\0"
|
|
/* 5207 */ "stlr\t\0"
|
|
/* 5213 */ "ldeor\t\0"
|
|
/* 5220 */ "nor\t\0"
|
|
/* 5225 */ "ror\t\0"
|
|
/* 5230 */ "ldapr\t\0"
|
|
/* 5237 */ "orr\t\0"
|
|
/* 5242 */ "asrr\t\0"
|
|
/* 5248 */ "lsrr\t\0"
|
|
/* 5254 */ "asr\t\0"
|
|
/* 5259 */ "lsr\t\0"
|
|
/* 5264 */ "msr\t\0"
|
|
/* 5269 */ "insr\t\0"
|
|
/* 5275 */ "ldtr\t\0"
|
|
/* 5281 */ "str\t\0"
|
|
/* 5286 */ "sttr\t\0"
|
|
/* 5292 */ "extr\t\0"
|
|
/* 5298 */ "ldur\t\0"
|
|
/* 5304 */ "stlur\t\0"
|
|
/* 5311 */ "ldapur\t\0"
|
|
/* 5319 */ "stur\t\0"
|
|
/* 5325 */ "fdivr\t\0"
|
|
/* 5332 */ "sdivr\t\0"
|
|
/* 5339 */ "udivr\t\0"
|
|
/* 5346 */ "whilewr\t\0"
|
|
/* 5355 */ "ldaxr\t\0"
|
|
/* 5362 */ "ldxr\t\0"
|
|
/* 5368 */ "stlxr\t\0"
|
|
/* 5375 */ "stxr\t\0"
|
|
/* 5381 */ "cas\t\0"
|
|
/* 5386 */ "brkas\t\0"
|
|
/* 5393 */ "brkpas\t\0"
|
|
/* 5401 */ "fcvtas\t\0"
|
|
/* 5409 */ "fabs\t\0"
|
|
/* 5415 */ "sqabs\t\0"
|
|
/* 5422 */ "brkbs\t\0"
|
|
/* 5429 */ "brkpbs\t\0"
|
|
/* 5437 */ "subs\t\0"
|
|
/* 5443 */ "sbcs\t\0"
|
|
/* 5449 */ "adcs\t\0"
|
|
/* 5455 */ "bics\t\0"
|
|
/* 5461 */ "adds\t\0"
|
|
/* 5467 */ "nands\t\0"
|
|
/* 5474 */ "ptrues\t\0"
|
|
/* 5482 */ "whilehs\t\0"
|
|
/* 5491 */ "cmhs\t\0"
|
|
/* 5497 */ "cmphs\t\0"
|
|
/* 5504 */ "cls\t\0"
|
|
/* 5509 */ "whilels\t\0"
|
|
/* 5518 */ "fmls\t\0"
|
|
/* 5524 */ "fnmls\t\0"
|
|
/* 5531 */ "cmpls\t\0"
|
|
/* 5538 */ "fcvtms\t\0"
|
|
/* 5546 */ "ins\t\0"
|
|
/* 5551 */ "brkns\t\0"
|
|
/* 5558 */ "orns\t\0"
|
|
/* 5564 */ "fcvtns\t\0"
|
|
/* 5572 */ "subps\t\0"
|
|
/* 5579 */ "frecps\t\0"
|
|
/* 5587 */ "bfmops\t\0"
|
|
/* 5595 */ "usmops\t\0"
|
|
/* 5603 */ "sumops\t\0"
|
|
/* 5611 */ "fcvtps\t\0"
|
|
/* 5619 */ "rdffrs\t\0"
|
|
/* 5627 */ "mrs\t\0"
|
|
/* 5632 */ "eors\t\0"
|
|
/* 5638 */ "nors\t\0"
|
|
/* 5644 */ "orrs\t\0"
|
|
/* 5650 */ "frsqrts\t\0"
|
|
/* 5659 */ "sys\t\0"
|
|
/* 5664 */ "fcvtzs\t\0"
|
|
/* 5672 */ "fjcvtzs\t\0"
|
|
/* 5681 */ "sqdmlalbt\t\0"
|
|
/* 5692 */ "ssublbt\t\0"
|
|
/* 5701 */ "saddlbt\t\0"
|
|
/* 5710 */ "sqdmlslbt\t\0"
|
|
/* 5721 */ "eorbt\t\0"
|
|
/* 5728 */ "compact\t\0"
|
|
/* 5737 */ "wfet\t\0"
|
|
/* 5743 */ "ret\t\0"
|
|
/* 5748 */ "ldset\t\0"
|
|
/* 5755 */ "facgt\t\0"
|
|
/* 5762 */ "whilegt\t\0"
|
|
/* 5771 */ "fcmgt\t\0"
|
|
/* 5778 */ "cmpgt\t\0"
|
|
/* 5785 */ "rbit\t\0"
|
|
/* 5791 */ "wfit\t\0"
|
|
/* 5797 */ "sabalt\t\0"
|
|
/* 5805 */ "uabalt\t\0"
|
|
/* 5813 */ "sqdmlalt\t\0"
|
|
/* 5823 */ "bfmlalt\t\0"
|
|
/* 5832 */ "smlalt\t\0"
|
|
/* 5840 */ "umlalt\t\0"
|
|
/* 5848 */ "ssublt\t\0"
|
|
/* 5856 */ "usublt\t\0"
|
|
/* 5864 */ "sbclt\t\0"
|
|
/* 5871 */ "adclt\t\0"
|
|
/* 5878 */ "sabdlt\t\0"
|
|
/* 5886 */ "uabdlt\t\0"
|
|
/* 5894 */ "saddlt\t\0"
|
|
/* 5902 */ "uaddlt\t\0"
|
|
/* 5910 */ "whilelt\t\0"
|
|
/* 5919 */ "hlt\t\0"
|
|
/* 5924 */ "sshllt\t\0"
|
|
/* 5932 */ "ushllt\t\0"
|
|
/* 5940 */ "sqdmullt\t\0"
|
|
/* 5950 */ "pmullt\t\0"
|
|
/* 5958 */ "smullt\t\0"
|
|
/* 5966 */ "umullt\t\0"
|
|
/* 5974 */ "fcmlt\t\0"
|
|
/* 5981 */ "cmplt\t\0"
|
|
/* 5988 */ "sqdmlslt\t\0"
|
|
/* 5998 */ "fmlslt\t\0"
|
|
/* 6006 */ "smlslt\t\0"
|
|
/* 6014 */ "umlslt\t\0"
|
|
/* 6022 */ "fcvtlt\t\0"
|
|
/* 6030 */ "histcnt\t\0"
|
|
/* 6039 */ "rsubhnt\t\0"
|
|
/* 6048 */ "raddhnt\t\0"
|
|
/* 6057 */ "hint\t\0"
|
|
/* 6063 */ "sqshrnt\t\0"
|
|
/* 6072 */ "uqshrnt\t\0"
|
|
/* 6081 */ "sqrshrnt\t\0"
|
|
/* 6091 */ "uqrshrnt\t\0"
|
|
/* 6101 */ "bfcvtnt\t\0"
|
|
/* 6110 */ "sqxtnt\t\0"
|
|
/* 6118 */ "uqxtnt\t\0"
|
|
/* 6126 */ "sqshrunt\t\0"
|
|
/* 6136 */ "sqrshrunt\t\0"
|
|
/* 6147 */ "sqxtunt\t\0"
|
|
/* 6156 */ "fcvtxnt\t\0"
|
|
/* 6165 */ "cdot\t\0"
|
|
/* 6171 */ "bfdot\t\0"
|
|
/* 6178 */ "usdot\t\0"
|
|
/* 6185 */ "sudot\t\0"
|
|
/* 6192 */ "cnot\t\0"
|
|
/* 6198 */ "tstart\t\0"
|
|
/* 6206 */ "fsqrt\t\0"
|
|
/* 6213 */ "ptest\t\0"
|
|
/* 6220 */ "ttest\t\0"
|
|
/* 6227 */ "pfirst\t\0"
|
|
/* 6235 */ "cmtst\t\0"
|
|
/* 6242 */ "bfcvt\t\0"
|
|
/* 6249 */ "ssubwt\t\0"
|
|
/* 6257 */ "usubwt\t\0"
|
|
/* 6265 */ "saddwt\t\0"
|
|
/* 6273 */ "uaddwt\t\0"
|
|
/* 6281 */ "bext\t\0"
|
|
/* 6287 */ "pnext\t\0"
|
|
/* 6294 */ "fcvtau\t\0"
|
|
/* 6302 */ "sqshlu\t\0"
|
|
/* 6310 */ "fcvtmu\t\0"
|
|
/* 6318 */ "fcvtnu\t\0"
|
|
/* 6326 */ "fcvtpu\t\0"
|
|
/* 6334 */ "fcvtzu\t\0"
|
|
/* 6342 */ "st64bv\t\0"
|
|
/* 6350 */ "faddv\t\0"
|
|
/* 6357 */ "saddv\t\0"
|
|
/* 6364 */ "uaddv\t\0"
|
|
/* 6371 */ "andv\t\0"
|
|
/* 6377 */ "rev\t\0"
|
|
/* 6382 */ "fdiv\t\0"
|
|
/* 6388 */ "sdiv\t\0"
|
|
/* 6394 */ "udiv\t\0"
|
|
/* 6400 */ "saddlv\t\0"
|
|
/* 6408 */ "uaddlv\t\0"
|
|
/* 6416 */ "fminnmv\t\0"
|
|
/* 6425 */ "fmaxnmv\t\0"
|
|
/* 6434 */ "fminv\t\0"
|
|
/* 6441 */ "sminv\t\0"
|
|
/* 6448 */ "uminv\t\0"
|
|
/* 6455 */ "csinv\t\0"
|
|
/* 6462 */ "fmov\t\0"
|
|
/* 6468 */ "smov\t\0"
|
|
/* 6474 */ "umov\t\0"
|
|
/* 6480 */ "eorv\t\0"
|
|
/* 6486 */ "fmaxv\t\0"
|
|
/* 6493 */ "smaxv\t\0"
|
|
/* 6500 */ "umaxv\t\0"
|
|
/* 6507 */ "ld1w\t\0"
|
|
/* 6513 */ "ldff1w\t\0"
|
|
/* 6521 */ "ldnf1w\t\0"
|
|
/* 6529 */ "ldnt1w\t\0"
|
|
/* 6537 */ "stnt1w\t\0"
|
|
/* 6545 */ "st1w\t\0"
|
|
/* 6551 */ "crc32w\t\0"
|
|
/* 6559 */ "ld2w\t\0"
|
|
/* 6565 */ "st2w\t\0"
|
|
/* 6571 */ "ld3w\t\0"
|
|
/* 6577 */ "st3w\t\0"
|
|
/* 6583 */ "ld4w\t\0"
|
|
/* 6589 */ "st4w\t\0"
|
|
/* 6595 */ "ssubw\t\0"
|
|
/* 6602 */ "usubw\t\0"
|
|
/* 6609 */ "crc32cw\t\0"
|
|
/* 6618 */ "sqdecw\t\0"
|
|
/* 6626 */ "uqdecw\t\0"
|
|
/* 6634 */ "sqincw\t\0"
|
|
/* 6642 */ "uqincw\t\0"
|
|
/* 6650 */ "saddw\t\0"
|
|
/* 6657 */ "uaddw\t\0"
|
|
/* 6664 */ "prfw\t\0"
|
|
/* 6670 */ "ld1row\t\0"
|
|
/* 6678 */ "ld1rqw\t\0"
|
|
/* 6686 */ "ld1rw\t\0"
|
|
/* 6693 */ "whilerw\t\0"
|
|
/* 6702 */ "ld1sw\t\0"
|
|
/* 6709 */ "ldff1sw\t\0"
|
|
/* 6718 */ "ldnf1sw\t\0"
|
|
/* 6727 */ "ldnt1sw\t\0"
|
|
/* 6736 */ "ldpsw\t\0"
|
|
/* 6743 */ "ld1rsw\t\0"
|
|
/* 6751 */ "ldrsw\t\0"
|
|
/* 6758 */ "ldtrsw\t\0"
|
|
/* 6766 */ "ldursw\t\0"
|
|
/* 6774 */ "ldapursw\t\0"
|
|
/* 6784 */ "cntw\t\0"
|
|
/* 6790 */ "sxtw\t\0"
|
|
/* 6796 */ "uxtw\t\0"
|
|
/* 6802 */ "revw\t\0"
|
|
/* 6808 */ "crc32x\t\0"
|
|
/* 6816 */ "frint32x\t\0"
|
|
/* 6826 */ "frint64x\t\0"
|
|
/* 6836 */ "bcax\t\0"
|
|
/* 6842 */ "fmax\t\0"
|
|
/* 6848 */ "ldsmax\t\0"
|
|
/* 6856 */ "ldumax\t\0"
|
|
/* 6864 */ "tbx\t\0"
|
|
/* 6869 */ "crc32cx\t\0"
|
|
/* 6878 */ "index\t\0"
|
|
/* 6885 */ "clrex\t\0"
|
|
/* 6892 */ "movprfx\t\0"
|
|
/* 6901 */ "fmulx\t\0"
|
|
/* 6908 */ "frecpx\t\0"
|
|
/* 6916 */ "frintx\t\0"
|
|
/* 6924 */ "fcvtx\t\0"
|
|
/* 6931 */ "sm4ekey\t\0"
|
|
/* 6940 */ "fcpy\t\0"
|
|
/* 6946 */ "frint32z\t\0"
|
|
/* 6956 */ "frint64z\t\0"
|
|
/* 6966 */ "braaz\t\0"
|
|
/* 6973 */ "blraaz\t\0"
|
|
/* 6981 */ "brabz\t\0"
|
|
/* 6988 */ "blrabz\t\0"
|
|
/* 6996 */ "cbz\t\0"
|
|
/* 7001 */ "tbz\t\0"
|
|
/* 7006 */ "clz\t\0"
|
|
/* 7011 */ "cbnz\t\0"
|
|
/* 7017 */ "tbnz\t\0"
|
|
/* 7023 */ "frintz\t\0"
|
|
/* 7031 */ "movz\t\0"
|
|
/* 7037 */ ".tlsdesccall \0"
|
|
/* 7051 */ "# XRay Function Patchable RET.\0"
|
|
/* 7082 */ "b.\0"
|
|
/* 7085 */ "bc.\0"
|
|
/* 7089 */ "# XRay Typed Event Log.\0"
|
|
/* 7113 */ "# XRay Custom Event Log.\0"
|
|
/* 7138 */ "# XRay Function Enter.\0"
|
|
/* 7161 */ "# XRay Tail Call Exit.\0"
|
|
/* 7184 */ "# XRay Function Exit.\0"
|
|
/* 7206 */ "hint\t#10\0"
|
|
/* 7215 */ "hint\t#30\0"
|
|
/* 7224 */ "hint\t#31\0"
|
|
/* 7233 */ "hint\t#12\0"
|
|
/* 7242 */ "hint\t#14\0"
|
|
/* 7251 */ "hint\t#24\0"
|
|
/* 7260 */ "hint\t#25\0"
|
|
/* 7269 */ "hint\t#26\0"
|
|
/* 7278 */ "hint\t#7\0"
|
|
/* 7286 */ "hint\t#27\0"
|
|
/* 7295 */ "hint\t#8\0"
|
|
/* 7303 */ "hint\t#28\0"
|
|
/* 7312 */ "hint\t#29\0"
|
|
/* 7321 */ "LIFETIME_END\0"
|
|
/* 7334 */ "PSEUDO_PROBE\0"
|
|
/* 7347 */ "BUNDLE\0"
|
|
/* 7354 */ "DBG_VALUE\0"
|
|
/* 7364 */ "DBG_INSTR_REF\0"
|
|
/* 7378 */ "DBG_PHI\0"
|
|
/* 7386 */ "DBG_LABEL\0"
|
|
/* 7396 */ "LIFETIME_START\0"
|
|
/* 7411 */ "DBG_VALUE_LIST\0"
|
|
/* 7426 */ "cpyfe\t[\0"
|
|
/* 7434 */ "setge\t[\0"
|
|
/* 7442 */ "sete\t[\0"
|
|
/* 7449 */ "cpye\t[\0"
|
|
/* 7456 */ "cpyfm\t[\0"
|
|
/* 7464 */ "setgm\t[\0"
|
|
/* 7472 */ "setm\t[\0"
|
|
/* 7479 */ "cpym\t[\0"
|
|
/* 7486 */ "cpyfen\t[\0"
|
|
/* 7495 */ "setgen\t[\0"
|
|
/* 7504 */ "seten\t[\0"
|
|
/* 7512 */ "cpyen\t[\0"
|
|
/* 7520 */ "cpyfmn\t[\0"
|
|
/* 7529 */ "setgmn\t[\0"
|
|
/* 7538 */ "setmn\t[\0"
|
|
/* 7546 */ "cpymn\t[\0"
|
|
/* 7554 */ "cpyfpn\t[\0"
|
|
/* 7563 */ "setgpn\t[\0"
|
|
/* 7572 */ "setpn\t[\0"
|
|
/* 7580 */ "cpypn\t[\0"
|
|
/* 7588 */ "cpyfern\t[\0"
|
|
/* 7598 */ "cpyern\t[\0"
|
|
/* 7607 */ "cpyfmrn\t[\0"
|
|
/* 7617 */ "cpymrn\t[\0"
|
|
/* 7626 */ "cpyfprn\t[\0"
|
|
/* 7636 */ "cpyprn\t[\0"
|
|
/* 7645 */ "cpyfetrn\t[\0"
|
|
/* 7656 */ "cpyetrn\t[\0"
|
|
/* 7666 */ "cpyfmtrn\t[\0"
|
|
/* 7677 */ "cpymtrn\t[\0"
|
|
/* 7687 */ "cpyfptrn\t[\0"
|
|
/* 7698 */ "cpyptrn\t[\0"
|
|
/* 7708 */ "cpyfertrn\t[\0"
|
|
/* 7720 */ "cpyertrn\t[\0"
|
|
/* 7731 */ "cpyfmrtrn\t[\0"
|
|
/* 7743 */ "cpymrtrn\t[\0"
|
|
/* 7754 */ "cpyfprtrn\t[\0"
|
|
/* 7766 */ "cpyprtrn\t[\0"
|
|
/* 7777 */ "cpyfewtrn\t[\0"
|
|
/* 7789 */ "cpyewtrn\t[\0"
|
|
/* 7800 */ "cpyfmwtrn\t[\0"
|
|
/* 7812 */ "cpymwtrn\t[\0"
|
|
/* 7823 */ "cpyfpwtrn\t[\0"
|
|
/* 7835 */ "cpypwtrn\t[\0"
|
|
/* 7846 */ "cpyfetn\t[\0"
|
|
/* 7856 */ "setgetn\t[\0"
|
|
/* 7866 */ "setetn\t[\0"
|
|
/* 7875 */ "cpyetn\t[\0"
|
|
/* 7884 */ "cpyfmtn\t[\0"
|
|
/* 7894 */ "setgmtn\t[\0"
|
|
/* 7904 */ "setmtn\t[\0"
|
|
/* 7913 */ "cpymtn\t[\0"
|
|
/* 7922 */ "cpyfptn\t[\0"
|
|
/* 7932 */ "setgptn\t[\0"
|
|
/* 7942 */ "setptn\t[\0"
|
|
/* 7951 */ "cpyptn\t[\0"
|
|
/* 7960 */ "cpyfertn\t[\0"
|
|
/* 7971 */ "cpyertn\t[\0"
|
|
/* 7981 */ "cpyfmrtn\t[\0"
|
|
/* 7992 */ "cpymrtn\t[\0"
|
|
/* 8002 */ "cpyfprtn\t[\0"
|
|
/* 8013 */ "cpyprtn\t[\0"
|
|
/* 8023 */ "cpyfewtn\t[\0"
|
|
/* 8034 */ "cpyewtn\t[\0"
|
|
/* 8044 */ "cpyfmwtn\t[\0"
|
|
/* 8055 */ "cpymwtn\t[\0"
|
|
/* 8065 */ "cpyfpwtn\t[\0"
|
|
/* 8076 */ "cpypwtn\t[\0"
|
|
/* 8086 */ "cpyfewn\t[\0"
|
|
/* 8096 */ "cpyewn\t[\0"
|
|
/* 8105 */ "cpyfmwn\t[\0"
|
|
/* 8115 */ "cpymwn\t[\0"
|
|
/* 8124 */ "cpyfpwn\t[\0"
|
|
/* 8134 */ "cpypwn\t[\0"
|
|
/* 8143 */ "cpyfetwn\t[\0"
|
|
/* 8154 */ "cpyetwn\t[\0"
|
|
/* 8164 */ "cpyfmtwn\t[\0"
|
|
/* 8175 */ "cpymtwn\t[\0"
|
|
/* 8185 */ "cpyfptwn\t[\0"
|
|
/* 8196 */ "cpyptwn\t[\0"
|
|
/* 8206 */ "cpyfertwn\t[\0"
|
|
/* 8218 */ "cpyertwn\t[\0"
|
|
/* 8229 */ "cpyfmrtwn\t[\0"
|
|
/* 8241 */ "cpymrtwn\t[\0"
|
|
/* 8252 */ "cpyfprtwn\t[\0"
|
|
/* 8264 */ "cpyprtwn\t[\0"
|
|
/* 8275 */ "cpyfewtwn\t[\0"
|
|
/* 8287 */ "cpyewtwn\t[\0"
|
|
/* 8298 */ "cpyfmwtwn\t[\0"
|
|
/* 8310 */ "cpymwtwn\t[\0"
|
|
/* 8321 */ "cpyfpwtwn\t[\0"
|
|
/* 8333 */ "cpypwtwn\t[\0"
|
|
/* 8344 */ "cpyfp\t[\0"
|
|
/* 8352 */ "setgp\t[\0"
|
|
/* 8360 */ "setp\t[\0"
|
|
/* 8367 */ "cpyp\t[\0"
|
|
/* 8374 */ "cpyfet\t[\0"
|
|
/* 8383 */ "setget\t[\0"
|
|
/* 8392 */ "setet\t[\0"
|
|
/* 8400 */ "cpyet\t[\0"
|
|
/* 8408 */ "cpyfmt\t[\0"
|
|
/* 8417 */ "setgmt\t[\0"
|
|
/* 8426 */ "setmt\t[\0"
|
|
/* 8434 */ "cpymt\t[\0"
|
|
/* 8442 */ "cpyfpt\t[\0"
|
|
/* 8451 */ "setgpt\t[\0"
|
|
/* 8460 */ "setpt\t[\0"
|
|
/* 8468 */ "cpypt\t[\0"
|
|
/* 8476 */ "cpyfert\t[\0"
|
|
/* 8486 */ "cpyert\t[\0"
|
|
/* 8495 */ "cpyfmrt\t[\0"
|
|
/* 8505 */ "cpymrt\t[\0"
|
|
/* 8514 */ "cpyfprt\t[\0"
|
|
/* 8524 */ "cpyprt\t[\0"
|
|
/* 8533 */ "cpyfewt\t[\0"
|
|
/* 8543 */ "cpyewt\t[\0"
|
|
/* 8552 */ "cpyfmwt\t[\0"
|
|
/* 8562 */ "cpymwt\t[\0"
|
|
/* 8571 */ "cpyfpwt\t[\0"
|
|
/* 8581 */ "cpypwt\t[\0"
|
|
/* 8590 */ "eretaa\0"
|
|
/* 8597 */ "eretab\0"
|
|
/* 8604 */ "sb\0"
|
|
/* 8607 */ "xaflag\0"
|
|
/* 8614 */ "axflag\0"
|
|
/* 8621 */ "brb\tinj\0"
|
|
/* 8629 */ "# FEntry call\0"
|
|
/* 8643 */ "brb\tiall\0"
|
|
/* 8652 */ "setffr\0"
|
|
/* 8659 */ "drps\0"
|
|
/* 8664 */ "eret\0"
|
|
/* 8669 */ "tcommit\0"
|
|
/* 8677 */ "cfinv\0"
|
|
/* 8683 */ "ld1b\t{\0"
|
|
/* 8690 */ "st1b\t{\0"
|
|
/* 8697 */ "ld1d\t{\0"
|
|
/* 8704 */ "st1d\t{\0"
|
|
/* 8711 */ "ld1h\t{\0"
|
|
/* 8718 */ "st1h\t{\0"
|
|
/* 8725 */ "ld1q\t{\0"
|
|
/* 8732 */ "st1q\t{\0"
|
|
/* 8739 */ "ld1w\t{\0"
|
|
/* 8746 */ "st1w\t{\0"
|
|
};
|
|
#endif
|
|
|
|
#ifdef __GNUC__
|
|
#pragma GCC diagnostic pop
|
|
#endif
|
|
|
|
static const uint32_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
7355U, // DBG_VALUE
|
|
7412U, // DBG_VALUE_LIST
|
|
7365U, // DBG_INSTR_REF
|
|
7379U, // DBG_PHI
|
|
7387U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
7348U, // BUNDLE
|
|
7397U, // LIFETIME_START
|
|
7322U, // LIFETIME_END
|
|
7335U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
8630U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
7139U, // PATCHABLE_FUNCTION_ENTER
|
|
7052U, // PATCHABLE_RET
|
|
7185U, // PATCHABLE_FUNCTION_EXIT
|
|
7162U, // PATCHABLE_TAIL_CALL
|
|
7114U, // PATCHABLE_EVENT_CALL
|
|
7090U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_FENCE
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ABS_ZPmZ_UNDEF_B
|
|
0U, // ABS_ZPmZ_UNDEF_D
|
|
0U, // ABS_ZPmZ_UNDEF_H
|
|
0U, // ABS_ZPmZ_UNDEF_S
|
|
0U, // ADDSWrr
|
|
0U, // ADDSXrr
|
|
0U, // ADDWrr
|
|
0U, // ADDXrr
|
|
0U, // ADD_ZPZZ_UNDEF_B
|
|
0U, // ADD_ZPZZ_UNDEF_D
|
|
0U, // ADD_ZPZZ_UNDEF_H
|
|
0U, // ADD_ZPZZ_UNDEF_S
|
|
0U, // ADD_ZPZZ_ZERO_B
|
|
0U, // ADD_ZPZZ_ZERO_D
|
|
0U, // ADD_ZPZZ_ZERO_H
|
|
0U, // ADD_ZPZZ_ZERO_S
|
|
0U, // ADDlowTLS
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // AESIMCrrTied
|
|
0U, // AESMCrrTied
|
|
0U, // ANDSWrr
|
|
0U, // ANDSXrr
|
|
0U, // ANDWrr
|
|
0U, // ANDXrr
|
|
0U, // ASRD_ZPZI_ZERO_B
|
|
0U, // ASRD_ZPZI_ZERO_D
|
|
0U, // ASRD_ZPZI_ZERO_H
|
|
0U, // ASRD_ZPZI_ZERO_S
|
|
0U, // ASR_ZPZI_UNDEF_B
|
|
0U, // ASR_ZPZI_UNDEF_D
|
|
0U, // ASR_ZPZI_UNDEF_H
|
|
0U, // ASR_ZPZI_UNDEF_S
|
|
0U, // ASR_ZPZZ_UNDEF_B
|
|
0U, // ASR_ZPZZ_UNDEF_D
|
|
0U, // ASR_ZPZZ_UNDEF_H
|
|
0U, // ASR_ZPZZ_UNDEF_S
|
|
0U, // ASR_ZPZZ_ZERO_B
|
|
0U, // ASR_ZPZZ_ZERO_D
|
|
0U, // ASR_ZPZZ_ZERO_H
|
|
0U, // ASR_ZPZZ_ZERO_S
|
|
0U, // BICSWrr
|
|
0U, // BICSXrr
|
|
0U, // BICWrr
|
|
0U, // BICXrr
|
|
0U, // BLRNoIP
|
|
0U, // BLR_BTI
|
|
0U, // BLR_RVMARKER
|
|
0U, // BSPv16i8
|
|
0U, // BSPv8i8
|
|
0U, // CATCHRET
|
|
0U, // CLEANUPRET
|
|
0U, // CLS_ZPmZ_UNDEF_B
|
|
0U, // CLS_ZPmZ_UNDEF_D
|
|
0U, // CLS_ZPmZ_UNDEF_H
|
|
0U, // CLS_ZPmZ_UNDEF_S
|
|
0U, // CLZ_ZPmZ_UNDEF_B
|
|
0U, // CLZ_ZPmZ_UNDEF_D
|
|
0U, // CLZ_ZPmZ_UNDEF_H
|
|
0U, // CLZ_ZPmZ_UNDEF_S
|
|
0U, // CMP_SWAP_128
|
|
0U, // CMP_SWAP_128_ACQUIRE
|
|
0U, // CMP_SWAP_128_MONOTONIC
|
|
0U, // CMP_SWAP_128_RELEASE
|
|
0U, // CMP_SWAP_16
|
|
0U, // CMP_SWAP_32
|
|
0U, // CMP_SWAP_64
|
|
0U, // CMP_SWAP_8
|
|
0U, // CNOT_ZPmZ_UNDEF_B
|
|
0U, // CNOT_ZPmZ_UNDEF_D
|
|
0U, // CNOT_ZPmZ_UNDEF_H
|
|
0U, // CNOT_ZPmZ_UNDEF_S
|
|
0U, // CNT_ZPmZ_UNDEF_B
|
|
0U, // CNT_ZPmZ_UNDEF_D
|
|
0U, // CNT_ZPmZ_UNDEF_H
|
|
0U, // CNT_ZPmZ_UNDEF_S
|
|
0U, // CompilerBarrier
|
|
0U, // EMITBKEY
|
|
0U, // EONWrr
|
|
0U, // EONXrr
|
|
0U, // EORWrr
|
|
0U, // EORXrr
|
|
0U, // F128CSEL
|
|
0U, // FABD_ZPZZ_UNDEF_D
|
|
0U, // FABD_ZPZZ_UNDEF_H
|
|
0U, // FABD_ZPZZ_UNDEF_S
|
|
0U, // FABD_ZPZZ_ZERO_D
|
|
0U, // FABD_ZPZZ_ZERO_H
|
|
0U, // FABD_ZPZZ_ZERO_S
|
|
0U, // FABS_ZPmZ_UNDEF_D
|
|
0U, // FABS_ZPmZ_UNDEF_H
|
|
0U, // FABS_ZPmZ_UNDEF_S
|
|
0U, // FADD_ZPZI_UNDEF_D
|
|
0U, // FADD_ZPZI_UNDEF_H
|
|
0U, // FADD_ZPZI_UNDEF_S
|
|
0U, // FADD_ZPZI_ZERO_D
|
|
0U, // FADD_ZPZI_ZERO_H
|
|
0U, // FADD_ZPZI_ZERO_S
|
|
0U, // FADD_ZPZZ_UNDEF_D
|
|
0U, // FADD_ZPZZ_UNDEF_H
|
|
0U, // FADD_ZPZZ_UNDEF_S
|
|
0U, // FADD_ZPZZ_ZERO_D
|
|
0U, // FADD_ZPZZ_ZERO_H
|
|
0U, // FADD_ZPZZ_ZERO_S
|
|
0U, // FCVTZS_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoS_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoH_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_StoD_UNDEF
|
|
0U, // FCVT_ZPmZ_StoH_UNDEF
|
|
0U, // FDIVR_ZPZZ_ZERO_D
|
|
0U, // FDIVR_ZPZZ_ZERO_H
|
|
0U, // FDIVR_ZPZZ_ZERO_S
|
|
0U, // FDIV_ZPZZ_UNDEF_D
|
|
0U, // FDIV_ZPZZ_UNDEF_H
|
|
0U, // FDIV_ZPZZ_UNDEF_S
|
|
0U, // FDIV_ZPZZ_ZERO_D
|
|
0U, // FDIV_ZPZZ_ZERO_H
|
|
0U, // FDIV_ZPZZ_ZERO_S
|
|
0U, // FMAXNM_ZPZI_UNDEF_D
|
|
0U, // FMAXNM_ZPZI_UNDEF_H
|
|
0U, // FMAXNM_ZPZI_UNDEF_S
|
|
0U, // FMAXNM_ZPZI_ZERO_D
|
|
0U, // FMAXNM_ZPZI_ZERO_H
|
|
0U, // FMAXNM_ZPZI_ZERO_S
|
|
0U, // FMAXNM_ZPZZ_UNDEF_D
|
|
0U, // FMAXNM_ZPZZ_UNDEF_H
|
|
0U, // FMAXNM_ZPZZ_UNDEF_S
|
|
0U, // FMAXNM_ZPZZ_ZERO_D
|
|
0U, // FMAXNM_ZPZZ_ZERO_H
|
|
0U, // FMAXNM_ZPZZ_ZERO_S
|
|
0U, // FMAX_ZPZI_UNDEF_D
|
|
0U, // FMAX_ZPZI_UNDEF_H
|
|
0U, // FMAX_ZPZI_UNDEF_S
|
|
0U, // FMAX_ZPZI_ZERO_D
|
|
0U, // FMAX_ZPZI_ZERO_H
|
|
0U, // FMAX_ZPZI_ZERO_S
|
|
0U, // FMAX_ZPZZ_UNDEF_D
|
|
0U, // FMAX_ZPZZ_UNDEF_H
|
|
0U, // FMAX_ZPZZ_UNDEF_S
|
|
0U, // FMAX_ZPZZ_ZERO_D
|
|
0U, // FMAX_ZPZZ_ZERO_H
|
|
0U, // FMAX_ZPZZ_ZERO_S
|
|
0U, // FMINNM_ZPZI_UNDEF_D
|
|
0U, // FMINNM_ZPZI_UNDEF_H
|
|
0U, // FMINNM_ZPZI_UNDEF_S
|
|
0U, // FMINNM_ZPZI_ZERO_D
|
|
0U, // FMINNM_ZPZI_ZERO_H
|
|
0U, // FMINNM_ZPZI_ZERO_S
|
|
0U, // FMINNM_ZPZZ_UNDEF_D
|
|
0U, // FMINNM_ZPZZ_UNDEF_H
|
|
0U, // FMINNM_ZPZZ_UNDEF_S
|
|
0U, // FMINNM_ZPZZ_ZERO_D
|
|
0U, // FMINNM_ZPZZ_ZERO_H
|
|
0U, // FMINNM_ZPZZ_ZERO_S
|
|
0U, // FMIN_ZPZI_UNDEF_D
|
|
0U, // FMIN_ZPZI_UNDEF_H
|
|
0U, // FMIN_ZPZI_UNDEF_S
|
|
0U, // FMIN_ZPZI_ZERO_D
|
|
0U, // FMIN_ZPZI_ZERO_H
|
|
0U, // FMIN_ZPZI_ZERO_S
|
|
0U, // FMIN_ZPZZ_UNDEF_D
|
|
0U, // FMIN_ZPZZ_UNDEF_H
|
|
0U, // FMIN_ZPZZ_UNDEF_S
|
|
0U, // FMIN_ZPZZ_ZERO_D
|
|
0U, // FMIN_ZPZZ_ZERO_H
|
|
0U, // FMIN_ZPZZ_ZERO_S
|
|
0U, // FMLA_ZPZZZ_UNDEF_D
|
|
0U, // FMLA_ZPZZZ_UNDEF_H
|
|
0U, // FMLA_ZPZZZ_UNDEF_S
|
|
0U, // FMLS_ZPZZZ_UNDEF_D
|
|
0U, // FMLS_ZPZZZ_UNDEF_H
|
|
0U, // FMLS_ZPZZZ_UNDEF_S
|
|
0U, // FMOVD0
|
|
0U, // FMOVH0
|
|
0U, // FMOVS0
|
|
0U, // FMULX_ZPZZ_ZERO_D
|
|
0U, // FMULX_ZPZZ_ZERO_H
|
|
0U, // FMULX_ZPZZ_ZERO_S
|
|
0U, // FMUL_ZPZI_UNDEF_D
|
|
0U, // FMUL_ZPZI_UNDEF_H
|
|
0U, // FMUL_ZPZI_UNDEF_S
|
|
0U, // FMUL_ZPZI_ZERO_D
|
|
0U, // FMUL_ZPZI_ZERO_H
|
|
0U, // FMUL_ZPZI_ZERO_S
|
|
0U, // FMUL_ZPZZ_UNDEF_D
|
|
0U, // FMUL_ZPZZ_UNDEF_H
|
|
0U, // FMUL_ZPZZ_UNDEF_S
|
|
0U, // FMUL_ZPZZ_ZERO_D
|
|
0U, // FMUL_ZPZZ_ZERO_H
|
|
0U, // FMUL_ZPZZ_ZERO_S
|
|
0U, // FNEG_ZPmZ_UNDEF_D
|
|
0U, // FNEG_ZPmZ_UNDEF_H
|
|
0U, // FNEG_ZPmZ_UNDEF_S
|
|
0U, // FNMLA_ZPZZZ_UNDEF_D
|
|
0U, // FNMLA_ZPZZZ_UNDEF_H
|
|
0U, // FNMLA_ZPZZZ_UNDEF_S
|
|
0U, // FNMLS_ZPZZZ_UNDEF_D
|
|
0U, // FNMLS_ZPZZZ_UNDEF_H
|
|
0U, // FNMLS_ZPZZZ_UNDEF_S
|
|
0U, // FRECPX_ZPmZ_UNDEF_D
|
|
0U, // FRECPX_ZPmZ_UNDEF_H
|
|
0U, // FRECPX_ZPmZ_UNDEF_S
|
|
0U, // FRINTA_ZPmZ_UNDEF_D
|
|
0U, // FRINTA_ZPmZ_UNDEF_H
|
|
0U, // FRINTA_ZPmZ_UNDEF_S
|
|
0U, // FRINTI_ZPmZ_UNDEF_D
|
|
0U, // FRINTI_ZPmZ_UNDEF_H
|
|
0U, // FRINTI_ZPmZ_UNDEF_S
|
|
0U, // FRINTM_ZPmZ_UNDEF_D
|
|
0U, // FRINTM_ZPmZ_UNDEF_H
|
|
0U, // FRINTM_ZPmZ_UNDEF_S
|
|
0U, // FRINTN_ZPmZ_UNDEF_D
|
|
0U, // FRINTN_ZPmZ_UNDEF_H
|
|
0U, // FRINTN_ZPmZ_UNDEF_S
|
|
0U, // FRINTP_ZPmZ_UNDEF_D
|
|
0U, // FRINTP_ZPmZ_UNDEF_H
|
|
0U, // FRINTP_ZPmZ_UNDEF_S
|
|
0U, // FRINTX_ZPmZ_UNDEF_D
|
|
0U, // FRINTX_ZPmZ_UNDEF_H
|
|
0U, // FRINTX_ZPmZ_UNDEF_S
|
|
0U, // FRINTZ_ZPmZ_UNDEF_D
|
|
0U, // FRINTZ_ZPmZ_UNDEF_H
|
|
0U, // FRINTZ_ZPmZ_UNDEF_S
|
|
0U, // FSQRT_ZPmZ_UNDEF_D
|
|
0U, // FSQRT_ZPmZ_UNDEF_H
|
|
0U, // FSQRT_ZPmZ_UNDEF_S
|
|
0U, // FSUBR_ZPZI_UNDEF_D
|
|
0U, // FSUBR_ZPZI_UNDEF_H
|
|
0U, // FSUBR_ZPZI_UNDEF_S
|
|
0U, // FSUBR_ZPZI_ZERO_D
|
|
0U, // FSUBR_ZPZI_ZERO_H
|
|
0U, // FSUBR_ZPZI_ZERO_S
|
|
0U, // FSUBR_ZPZZ_ZERO_D
|
|
0U, // FSUBR_ZPZZ_ZERO_H
|
|
0U, // FSUBR_ZPZZ_ZERO_S
|
|
0U, // FSUB_ZPZI_UNDEF_D
|
|
0U, // FSUB_ZPZI_UNDEF_H
|
|
0U, // FSUB_ZPZI_UNDEF_S
|
|
0U, // FSUB_ZPZI_ZERO_D
|
|
0U, // FSUB_ZPZI_ZERO_H
|
|
0U, // FSUB_ZPZI_ZERO_S
|
|
0U, // FSUB_ZPZZ_UNDEF_D
|
|
0U, // FSUB_ZPZZ_UNDEF_H
|
|
0U, // FSUB_ZPZZ_UNDEF_S
|
|
0U, // FSUB_ZPZZ_ZERO_D
|
|
0U, // FSUB_ZPZZ_ZERO_H
|
|
0U, // FSUB_ZPZZ_ZERO_S
|
|
0U, // GLD1B_D
|
|
0U, // GLD1B_D_IMM
|
|
0U, // GLD1B_D_SXTW
|
|
0U, // GLD1B_D_UXTW
|
|
0U, // GLD1B_S_IMM
|
|
0U, // GLD1B_S_SXTW
|
|
0U, // GLD1B_S_UXTW
|
|
0U, // GLD1D
|
|
0U, // GLD1D_IMM
|
|
0U, // GLD1D_SCALED
|
|
0U, // GLD1D_SXTW
|
|
0U, // GLD1D_SXTW_SCALED
|
|
0U, // GLD1D_UXTW
|
|
0U, // GLD1D_UXTW_SCALED
|
|
0U, // GLD1H_D
|
|
0U, // GLD1H_D_IMM
|
|
0U, // GLD1H_D_SCALED
|
|
0U, // GLD1H_D_SXTW
|
|
0U, // GLD1H_D_SXTW_SCALED
|
|
0U, // GLD1H_D_UXTW
|
|
0U, // GLD1H_D_UXTW_SCALED
|
|
0U, // GLD1H_S_IMM
|
|
0U, // GLD1H_S_SXTW
|
|
0U, // GLD1H_S_SXTW_SCALED
|
|
0U, // GLD1H_S_UXTW
|
|
0U, // GLD1H_S_UXTW_SCALED
|
|
0U, // GLD1SB_D
|
|
0U, // GLD1SB_D_IMM
|
|
0U, // GLD1SB_D_SXTW
|
|
0U, // GLD1SB_D_UXTW
|
|
0U, // GLD1SB_S_IMM
|
|
0U, // GLD1SB_S_SXTW
|
|
0U, // GLD1SB_S_UXTW
|
|
0U, // GLD1SH_D
|
|
0U, // GLD1SH_D_IMM
|
|
0U, // GLD1SH_D_SCALED
|
|
0U, // GLD1SH_D_SXTW
|
|
0U, // GLD1SH_D_SXTW_SCALED
|
|
0U, // GLD1SH_D_UXTW
|
|
0U, // GLD1SH_D_UXTW_SCALED
|
|
0U, // GLD1SH_S_IMM
|
|
0U, // GLD1SH_S_SXTW
|
|
0U, // GLD1SH_S_SXTW_SCALED
|
|
0U, // GLD1SH_S_UXTW
|
|
0U, // GLD1SH_S_UXTW_SCALED
|
|
0U, // GLD1SW_D
|
|
0U, // GLD1SW_D_IMM
|
|
0U, // GLD1SW_D_SCALED
|
|
0U, // GLD1SW_D_SXTW
|
|
0U, // GLD1SW_D_SXTW_SCALED
|
|
0U, // GLD1SW_D_UXTW
|
|
0U, // GLD1SW_D_UXTW_SCALED
|
|
0U, // GLD1W_D
|
|
0U, // GLD1W_D_IMM
|
|
0U, // GLD1W_D_SCALED
|
|
0U, // GLD1W_D_SXTW
|
|
0U, // GLD1W_D_SXTW_SCALED
|
|
0U, // GLD1W_D_UXTW
|
|
0U, // GLD1W_D_UXTW_SCALED
|
|
0U, // GLD1W_IMM
|
|
0U, // GLD1W_SXTW
|
|
0U, // GLD1W_SXTW_SCALED
|
|
0U, // GLD1W_UXTW
|
|
0U, // GLD1W_UXTW_SCALED
|
|
0U, // GLDFF1B_D
|
|
0U, // GLDFF1B_D_IMM
|
|
0U, // GLDFF1B_D_SXTW
|
|
0U, // GLDFF1B_D_UXTW
|
|
0U, // GLDFF1B_S_IMM
|
|
0U, // GLDFF1B_S_SXTW
|
|
0U, // GLDFF1B_S_UXTW
|
|
0U, // GLDFF1D
|
|
0U, // GLDFF1D_IMM
|
|
0U, // GLDFF1D_SCALED
|
|
0U, // GLDFF1D_SXTW
|
|
0U, // GLDFF1D_SXTW_SCALED
|
|
0U, // GLDFF1D_UXTW
|
|
0U, // GLDFF1D_UXTW_SCALED
|
|
0U, // GLDFF1H_D
|
|
0U, // GLDFF1H_D_IMM
|
|
0U, // GLDFF1H_D_SCALED
|
|
0U, // GLDFF1H_D_SXTW
|
|
0U, // GLDFF1H_D_SXTW_SCALED
|
|
0U, // GLDFF1H_D_UXTW
|
|
0U, // GLDFF1H_D_UXTW_SCALED
|
|
0U, // GLDFF1H_S_IMM
|
|
0U, // GLDFF1H_S_SXTW
|
|
0U, // GLDFF1H_S_SXTW_SCALED
|
|
0U, // GLDFF1H_S_UXTW
|
|
0U, // GLDFF1H_S_UXTW_SCALED
|
|
0U, // GLDFF1SB_D
|
|
0U, // GLDFF1SB_D_IMM
|
|
0U, // GLDFF1SB_D_SXTW
|
|
0U, // GLDFF1SB_D_UXTW
|
|
0U, // GLDFF1SB_S_IMM
|
|
0U, // GLDFF1SB_S_SXTW
|
|
0U, // GLDFF1SB_S_UXTW
|
|
0U, // GLDFF1SH_D
|
|
0U, // GLDFF1SH_D_IMM
|
|
0U, // GLDFF1SH_D_SCALED
|
|
0U, // GLDFF1SH_D_SXTW
|
|
0U, // GLDFF1SH_D_SXTW_SCALED
|
|
0U, // GLDFF1SH_D_UXTW
|
|
0U, // GLDFF1SH_D_UXTW_SCALED
|
|
0U, // GLDFF1SH_S_IMM
|
|
0U, // GLDFF1SH_S_SXTW
|
|
0U, // GLDFF1SH_S_SXTW_SCALED
|
|
0U, // GLDFF1SH_S_UXTW
|
|
0U, // GLDFF1SH_S_UXTW_SCALED
|
|
0U, // GLDFF1SW_D
|
|
0U, // GLDFF1SW_D_IMM
|
|
0U, // GLDFF1SW_D_SCALED
|
|
0U, // GLDFF1SW_D_SXTW
|
|
0U, // GLDFF1SW_D_SXTW_SCALED
|
|
0U, // GLDFF1SW_D_UXTW
|
|
0U, // GLDFF1SW_D_UXTW_SCALED
|
|
0U, // GLDFF1W_D
|
|
0U, // GLDFF1W_D_IMM
|
|
0U, // GLDFF1W_D_SCALED
|
|
0U, // GLDFF1W_D_SXTW
|
|
0U, // GLDFF1W_D_SXTW_SCALED
|
|
0U, // GLDFF1W_D_UXTW
|
|
0U, // GLDFF1W_D_UXTW_SCALED
|
|
0U, // GLDFF1W_IMM
|
|
0U, // GLDFF1W_SXTW
|
|
0U, // GLDFF1W_SXTW_SCALED
|
|
0U, // GLDFF1W_UXTW
|
|
0U, // GLDFF1W_UXTW_SCALED
|
|
0U, // G_ADD_LOW
|
|
0U, // G_DUP
|
|
0U, // G_DUPLANE16
|
|
0U, // G_DUPLANE32
|
|
0U, // G_DUPLANE64
|
|
0U, // G_DUPLANE8
|
|
0U, // G_EXT
|
|
0U, // G_FCMEQ
|
|
0U, // G_FCMEQZ
|
|
0U, // G_FCMGE
|
|
0U, // G_FCMGEZ
|
|
0U, // G_FCMGT
|
|
0U, // G_FCMGTZ
|
|
0U, // G_FCMLEZ
|
|
0U, // G_FCMLTZ
|
|
0U, // G_REV16
|
|
0U, // G_REV32
|
|
0U, // G_REV64
|
|
0U, // G_SITOF
|
|
0U, // G_TRN1
|
|
0U, // G_TRN2
|
|
0U, // G_UITOF
|
|
0U, // G_UZP1
|
|
0U, // G_UZP2
|
|
0U, // G_VASHR
|
|
0U, // G_VLSHR
|
|
0U, // G_ZIP1
|
|
0U, // G_ZIP2
|
|
0U, // HOM_Epilog
|
|
0U, // HOM_Prolog
|
|
0U, // HWASAN_CHECK_MEMACCESS
|
|
0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
|
|
0U, // IRGstack
|
|
0U, // JumpTableDest16
|
|
0U, // JumpTableDest32
|
|
0U, // JumpTableDest8
|
|
0U, // LD1B_D_IMM
|
|
0U, // LD1B_H_IMM
|
|
0U, // LD1B_IMM
|
|
0U, // LD1B_S_IMM
|
|
0U, // LD1D_IMM
|
|
0U, // LD1H_D_IMM
|
|
0U, // LD1H_IMM
|
|
0U, // LD1H_S_IMM
|
|
0U, // LD1SB_D_IMM
|
|
0U, // LD1SB_H_IMM
|
|
0U, // LD1SB_S_IMM
|
|
0U, // LD1SH_D_IMM
|
|
0U, // LD1SH_S_IMM
|
|
0U, // LD1SW_D_IMM
|
|
0U, // LD1W_D_IMM
|
|
0U, // LD1W_IMM
|
|
0U, // LDFF1B
|
|
0U, // LDFF1B_D
|
|
0U, // LDFF1B_H
|
|
0U, // LDFF1B_S
|
|
0U, // LDFF1D
|
|
0U, // LDFF1H
|
|
0U, // LDFF1H_D
|
|
0U, // LDFF1H_S
|
|
0U, // LDFF1SB_D
|
|
0U, // LDFF1SB_H
|
|
0U, // LDFF1SB_S
|
|
0U, // LDFF1SH_D
|
|
0U, // LDFF1SH_S
|
|
0U, // LDFF1SW_D
|
|
0U, // LDFF1W
|
|
0U, // LDFF1W_D
|
|
0U, // LDNF1B_D_IMM
|
|
0U, // LDNF1B_H_IMM
|
|
0U, // LDNF1B_IMM
|
|
0U, // LDNF1B_S_IMM
|
|
0U, // LDNF1D_IMM
|
|
0U, // LDNF1H_D_IMM
|
|
0U, // LDNF1H_IMM
|
|
0U, // LDNF1H_S_IMM
|
|
0U, // LDNF1SB_D_IMM
|
|
0U, // LDNF1SB_H_IMM
|
|
0U, // LDNF1SB_S_IMM
|
|
0U, // LDNF1SH_D_IMM
|
|
0U, // LDNF1SH_S_IMM
|
|
0U, // LDNF1SW_D_IMM
|
|
0U, // LDNF1W_D_IMM
|
|
0U, // LDNF1W_IMM
|
|
0U, // LDR_ZZXI
|
|
0U, // LDR_ZZZXI
|
|
0U, // LDR_ZZZZXI
|
|
0U, // LOADgot
|
|
0U, // LSL_ZPZI_UNDEF_B
|
|
0U, // LSL_ZPZI_UNDEF_D
|
|
0U, // LSL_ZPZI_UNDEF_H
|
|
0U, // LSL_ZPZI_UNDEF_S
|
|
0U, // LSL_ZPZZ_UNDEF_B
|
|
0U, // LSL_ZPZZ_UNDEF_D
|
|
0U, // LSL_ZPZZ_UNDEF_H
|
|
0U, // LSL_ZPZZ_UNDEF_S
|
|
0U, // LSL_ZPZZ_ZERO_B
|
|
0U, // LSL_ZPZZ_ZERO_D
|
|
0U, // LSL_ZPZZ_ZERO_H
|
|
0U, // LSL_ZPZZ_ZERO_S
|
|
0U, // LSR_ZPZI_UNDEF_B
|
|
0U, // LSR_ZPZI_UNDEF_D
|
|
0U, // LSR_ZPZI_UNDEF_H
|
|
0U, // LSR_ZPZI_UNDEF_S
|
|
0U, // LSR_ZPZZ_UNDEF_B
|
|
0U, // LSR_ZPZZ_UNDEF_D
|
|
0U, // LSR_ZPZZ_UNDEF_H
|
|
0U, // LSR_ZPZZ_UNDEF_S
|
|
0U, // LSR_ZPZZ_ZERO_B
|
|
0U, // LSR_ZPZZ_ZERO_D
|
|
0U, // LSR_ZPZZ_ZERO_H
|
|
0U, // LSR_ZPZZ_ZERO_S
|
|
0U, // MOPSMemoryCopyPseudo
|
|
0U, // MOPSMemoryMovePseudo
|
|
0U, // MOPSMemorySetPseudo
|
|
0U, // MOPSMemorySetTaggingPseudo
|
|
0U, // MOVMCSym
|
|
0U, // MOVaddr
|
|
0U, // MOVaddrBA
|
|
0U, // MOVaddrCP
|
|
0U, // MOVaddrEXT
|
|
0U, // MOVaddrJT
|
|
0U, // MOVaddrTLS
|
|
0U, // MOVbaseTLS
|
|
0U, // MOVi32imm
|
|
0U, // MOVi64imm
|
|
0U, // MUL_ZPZZ_UNDEF_B
|
|
0U, // MUL_ZPZZ_UNDEF_D
|
|
0U, // MUL_ZPZZ_UNDEF_H
|
|
0U, // MUL_ZPZZ_UNDEF_S
|
|
0U, // NEG_ZPmZ_UNDEF_B
|
|
0U, // NEG_ZPmZ_UNDEF_D
|
|
0U, // NEG_ZPmZ_UNDEF_H
|
|
0U, // NEG_ZPmZ_UNDEF_S
|
|
0U, // NOT_ZPmZ_UNDEF_B
|
|
0U, // NOT_ZPmZ_UNDEF_D
|
|
0U, // NOT_ZPmZ_UNDEF_H
|
|
0U, // NOT_ZPmZ_UNDEF_S
|
|
0U, // ORNWrr
|
|
0U, // ORNXrr
|
|
0U, // ORRWrr
|
|
0U, // ORRXrr
|
|
0U, // RDFFR_P
|
|
0U, // RDFFR_PPz
|
|
0U, // RET_ReallyLR
|
|
0U, // SABD_ZPZZ_UNDEF_B
|
|
0U, // SABD_ZPZZ_UNDEF_D
|
|
0U, // SABD_ZPZZ_UNDEF_H
|
|
0U, // SABD_ZPZZ_UNDEF_S
|
|
0U, // SCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // SCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // SDIV_ZPZZ_UNDEF_D
|
|
0U, // SDIV_ZPZZ_UNDEF_S
|
|
0U, // SEH_AddFP
|
|
0U, // SEH_EpilogEnd
|
|
0U, // SEH_EpilogStart
|
|
0U, // SEH_Nop
|
|
0U, // SEH_PrologEnd
|
|
0U, // SEH_SaveFPLR
|
|
0U, // SEH_SaveFPLR_X
|
|
0U, // SEH_SaveFReg
|
|
0U, // SEH_SaveFRegP
|
|
0U, // SEH_SaveFRegP_X
|
|
0U, // SEH_SaveFReg_X
|
|
0U, // SEH_SaveReg
|
|
0U, // SEH_SaveRegP
|
|
0U, // SEH_SaveRegP_X
|
|
0U, // SEH_SaveReg_X
|
|
0U, // SEH_SetFP
|
|
0U, // SEH_StackAlloc
|
|
0U, // SMAX_ZPZZ_UNDEF_B
|
|
0U, // SMAX_ZPZZ_UNDEF_D
|
|
0U, // SMAX_ZPZZ_UNDEF_H
|
|
0U, // SMAX_ZPZZ_UNDEF_S
|
|
0U, // SMIN_ZPZZ_UNDEF_B
|
|
0U, // SMIN_ZPZZ_UNDEF_D
|
|
0U, // SMIN_ZPZZ_UNDEF_H
|
|
0U, // SMIN_ZPZZ_UNDEF_S
|
|
0U, // SMULH_ZPZZ_UNDEF_B
|
|
0U, // SMULH_ZPZZ_UNDEF_D
|
|
0U, // SMULH_ZPZZ_UNDEF_H
|
|
0U, // SMULH_ZPZZ_UNDEF_S
|
|
0U, // SPACE
|
|
0U, // SQABS_ZPmZ_UNDEF_B
|
|
0U, // SQABS_ZPmZ_UNDEF_D
|
|
0U, // SQABS_ZPmZ_UNDEF_H
|
|
0U, // SQABS_ZPmZ_UNDEF_S
|
|
0U, // SQNEG_ZPmZ_UNDEF_B
|
|
0U, // SQNEG_ZPmZ_UNDEF_D
|
|
0U, // SQNEG_ZPmZ_UNDEF_H
|
|
0U, // SQNEG_ZPmZ_UNDEF_S
|
|
0U, // SQRSHL_ZPZZ_UNDEF_B
|
|
0U, // SQRSHL_ZPZZ_UNDEF_D
|
|
0U, // SQRSHL_ZPZZ_UNDEF_H
|
|
0U, // SQRSHL_ZPZZ_UNDEF_S
|
|
0U, // SQSHLU_ZPZI_ZERO_B
|
|
0U, // SQSHLU_ZPZI_ZERO_D
|
|
0U, // SQSHLU_ZPZI_ZERO_H
|
|
0U, // SQSHLU_ZPZI_ZERO_S
|
|
0U, // SQSHL_ZPZI_ZERO_B
|
|
0U, // SQSHL_ZPZI_ZERO_D
|
|
0U, // SQSHL_ZPZI_ZERO_H
|
|
0U, // SQSHL_ZPZI_ZERO_S
|
|
0U, // SQSHL_ZPZZ_UNDEF_B
|
|
0U, // SQSHL_ZPZZ_UNDEF_D
|
|
0U, // SQSHL_ZPZZ_UNDEF_H
|
|
0U, // SQSHL_ZPZZ_UNDEF_S
|
|
0U, // SRSHL_ZPZZ_UNDEF_B
|
|
0U, // SRSHL_ZPZZ_UNDEF_D
|
|
0U, // SRSHL_ZPZZ_UNDEF_H
|
|
0U, // SRSHL_ZPZZ_UNDEF_S
|
|
0U, // SRSHR_ZPZI_ZERO_B
|
|
0U, // SRSHR_ZPZI_ZERO_D
|
|
0U, // SRSHR_ZPZI_ZERO_H
|
|
0U, // SRSHR_ZPZI_ZERO_S
|
|
0U, // STGloop
|
|
0U, // STGloop_wback
|
|
0U, // STR_ZZXI
|
|
0U, // STR_ZZZXI
|
|
0U, // STR_ZZZZXI
|
|
0U, // STZGloop
|
|
0U, // STZGloop_wback
|
|
0U, // SUBR_ZPZZ_ZERO_B
|
|
0U, // SUBR_ZPZZ_ZERO_D
|
|
0U, // SUBR_ZPZZ_ZERO_H
|
|
0U, // SUBR_ZPZZ_ZERO_S
|
|
0U, // SUBSWrr
|
|
0U, // SUBSXrr
|
|
0U, // SUBWrr
|
|
0U, // SUBXrr
|
|
0U, // SUB_ZPZZ_UNDEF_B
|
|
0U, // SUB_ZPZZ_UNDEF_D
|
|
0U, // SUB_ZPZZ_UNDEF_H
|
|
0U, // SUB_ZPZZ_UNDEF_S
|
|
0U, // SUB_ZPZZ_ZERO_B
|
|
0U, // SUB_ZPZZ_ZERO_D
|
|
0U, // SUB_ZPZZ_ZERO_H
|
|
0U, // SUB_ZPZZ_ZERO_S
|
|
0U, // SXTB_ZPmZ_UNDEF_D
|
|
0U, // SXTB_ZPmZ_UNDEF_H
|
|
0U, // SXTB_ZPmZ_UNDEF_S
|
|
0U, // SXTH_ZPmZ_UNDEF_D
|
|
0U, // SXTH_ZPmZ_UNDEF_S
|
|
0U, // SXTW_ZPmZ_UNDEF_D
|
|
0U, // SpeculationBarrierISBDSBEndBB
|
|
0U, // SpeculationBarrierSBEndBB
|
|
0U, // SpeculationSafeValueW
|
|
0U, // SpeculationSafeValueX
|
|
0U, // StoreSwiftAsyncContext
|
|
0U, // TAGPstack
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNriALL
|
|
0U, // TCRETURNriBTI
|
|
23422U, // TLSDESCCALL
|
|
0U, // TLSDESC_CALLSEQ
|
|
0U, // UABD_ZPZZ_UNDEF_B
|
|
0U, // UABD_ZPZZ_UNDEF_D
|
|
0U, // UABD_ZPZZ_UNDEF_H
|
|
0U, // UABD_ZPZZ_UNDEF_S
|
|
0U, // UCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // UCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // UDIV_ZPZZ_UNDEF_D
|
|
0U, // UDIV_ZPZZ_UNDEF_S
|
|
0U, // UMAX_ZPZZ_UNDEF_B
|
|
0U, // UMAX_ZPZZ_UNDEF_D
|
|
0U, // UMAX_ZPZZ_UNDEF_H
|
|
0U, // UMAX_ZPZZ_UNDEF_S
|
|
0U, // UMIN_ZPZZ_UNDEF_B
|
|
0U, // UMIN_ZPZZ_UNDEF_D
|
|
0U, // UMIN_ZPZZ_UNDEF_H
|
|
0U, // UMIN_ZPZZ_UNDEF_S
|
|
0U, // UMULH_ZPZZ_UNDEF_B
|
|
0U, // UMULH_ZPZZ_UNDEF_D
|
|
0U, // UMULH_ZPZZ_UNDEF_H
|
|
0U, // UMULH_ZPZZ_UNDEF_S
|
|
0U, // UQRSHL_ZPZZ_UNDEF_B
|
|
0U, // UQRSHL_ZPZZ_UNDEF_D
|
|
0U, // UQRSHL_ZPZZ_UNDEF_H
|
|
0U, // UQRSHL_ZPZZ_UNDEF_S
|
|
0U, // UQSHL_ZPZI_ZERO_B
|
|
0U, // UQSHL_ZPZI_ZERO_D
|
|
0U, // UQSHL_ZPZI_ZERO_H
|
|
0U, // UQSHL_ZPZI_ZERO_S
|
|
0U, // UQSHL_ZPZZ_UNDEF_B
|
|
0U, // UQSHL_ZPZZ_UNDEF_D
|
|
0U, // UQSHL_ZPZZ_UNDEF_H
|
|
0U, // UQSHL_ZPZZ_UNDEF_S
|
|
0U, // URECPE_ZPmZ_UNDEF_S
|
|
0U, // URSHL_ZPZZ_UNDEF_B
|
|
0U, // URSHL_ZPZZ_UNDEF_D
|
|
0U, // URSHL_ZPZZ_UNDEF_H
|
|
0U, // URSHL_ZPZZ_UNDEF_S
|
|
0U, // URSHR_ZPZI_ZERO_B
|
|
0U, // URSHR_ZPZI_ZERO_D
|
|
0U, // URSHR_ZPZI_ZERO_H
|
|
0U, // URSHR_ZPZI_ZERO_S
|
|
0U, // URSQRTE_ZPmZ_UNDEF_S
|
|
0U, // UXTB_ZPmZ_UNDEF_D
|
|
0U, // UXTB_ZPmZ_UNDEF_H
|
|
0U, // UXTB_ZPmZ_UNDEF_S
|
|
0U, // UXTH_ZPmZ_UNDEF_D
|
|
0U, // UXTH_ZPmZ_UNDEF_S
|
|
0U, // UXTW_ZPmZ_UNDEF_D
|
|
2135331U, // ABS_ZPmZ_B
|
|
2151715U, // ABS_ZPmZ_D
|
|
272700707U, // ABS_ZPmZ_H
|
|
2184483U, // ABS_ZPmZ_S
|
|
543266083U, // ABSv16i8
|
|
807425315U, // ABSv1i64
|
|
545363235U, // ABSv2i32
|
|
547460387U, // ABSv2i64
|
|
549557539U, // ABSv4i16
|
|
551654691U, // ABSv4i32
|
|
553751843U, // ABSv8i16
|
|
555848995U, // ABSv8i8
|
|
1075889597U, // ADCLB_ZZZ_D
|
|
1344357821U, // ADCLB_ZZZ_S
|
|
1075894000U, // ADCLT_ZZZ_D
|
|
1344362224U, // ADCLT_ZZZ_S
|
|
807425354U, // ADCSWr
|
|
807425354U, // ADCSXr
|
|
807422196U, // ADCWr
|
|
807422196U, // ADCXr
|
|
807422760U, // ADDG
|
|
1631699639U, // ADDHA_MPPZ_D
|
|
1633796791U, // ADDHA_MPPZ_S
|
|
1881179809U, // ADDHNB_ZZZ_B
|
|
2172716705U, // ADDHNB_ZZZ_H
|
|
2418099873U, // ADDHNB_ZZZ_S
|
|
2686490530U, // ADDHNT_ZZZ_B
|
|
2174818210U, // ADDHNT_ZZZ_H
|
|
1075926946U, // ADDHNT_ZZZ_S
|
|
545362315U, // ADDHNv2i64_v2i32
|
|
2967601516U, // ADDHNv2i64_v4i32
|
|
549556619U, // ADDHNv4i32_v4i16
|
|
2969698668U, // ADDHNv4i32_v8i16
|
|
2959212908U, // ADDHNv8i16_v16i8
|
|
555848075U, // ADDHNv8i16_v8i8
|
|
807424134U, // ADDPL_XXI
|
|
3223360141U, // ADDP_ZPmZ_B
|
|
3223376525U, // ADDP_ZPmZ_D
|
|
3519091341U, // ADDP_ZPmZ_H
|
|
3223409293U, // ADDP_ZPmZ_S
|
|
543265421U, // ADDPv16i8
|
|
545362573U, // ADDPv2i32
|
|
547459725U, // ADDPv2i64
|
|
538989197U, // ADDPv2i64p
|
|
549556877U, // ADDPv4i16
|
|
551654029U, // ADDPv4i32
|
|
553751181U, // ADDPv8i16
|
|
555848333U, // ADDPv8i8
|
|
807425366U, // ADDSWri
|
|
807425366U, // ADDSWrs
|
|
807425366U, // ADDSWrx
|
|
807425366U, // ADDSXri
|
|
807425366U, // ADDSXrs
|
|
807425366U, // ADDSXrx
|
|
807425366U, // ADDSXrx64
|
|
1631699850U, // ADDVA_MPPZ_D
|
|
1633797002U, // ADDVA_MPPZ_S
|
|
807424260U, // ADDVL_XXI
|
|
538990800U, // ADDVv16i8v
|
|
538990800U, // ADDVv4i16v
|
|
538990800U, // ADDVv4i32v
|
|
538990800U, // ADDVv8i16v
|
|
538990800U, // ADDVv8i8v
|
|
807422397U, // ADDWri
|
|
807422397U, // ADDWrs
|
|
807422397U, // ADDWrx
|
|
807422397U, // ADDXri
|
|
807422397U, // ADDXrs
|
|
807422397U, // ADDXrx
|
|
807422397U, // ADDXrx64
|
|
3760228797U, // ADD_ZI_B
|
|
2418067901U, // ADD_ZI_D
|
|
2179008957U, // ADD_ZI_H
|
|
4028713405U, // ADD_ZI_S
|
|
3223357885U, // ADD_ZPmZ_B
|
|
3223374269U, // ADD_ZPmZ_D
|
|
3519089085U, // ADD_ZPmZ_H
|
|
3223407037U, // ADD_ZPmZ_S
|
|
3760228797U, // ADD_ZZZ_B
|
|
2418067901U, // ADD_ZZZ_D
|
|
2179008957U, // ADD_ZZZ_H
|
|
4028713405U, // ADD_ZZZ_S
|
|
543263165U, // ADDv16i8
|
|
807422397U, // ADDv1i64
|
|
545360317U, // ADDv2i32
|
|
547457469U, // ADDv2i64
|
|
549554621U, // ADDv4i16
|
|
551651773U, // ADDv4i32
|
|
553748925U, // ADDv8i16
|
|
555846077U, // ADDv8i8
|
|
807424987U, // ADR
|
|
2118420U, // ADRP
|
|
2449527771U, // ADR_LSL_ZZZ_D_0
|
|
2449527771U, // ADR_LSL_ZZZ_D_1
|
|
2449527771U, // ADR_LSL_ZZZ_D_2
|
|
2449527771U, // ADR_LSL_ZZZ_D_3
|
|
4060173275U, // ADR_LSL_ZZZ_S_0
|
|
4060173275U, // ADR_LSL_ZZZ_S_1
|
|
4060173275U, // ADR_LSL_ZZZ_S_2
|
|
4060173275U, // ADR_LSL_ZZZ_S_3
|
|
2449527771U, // ADR_SXTW_ZZZ_D_0
|
|
2449527771U, // ADR_SXTW_ZZZ_D_1
|
|
2449527771U, // ADR_SXTW_ZZZ_D_2
|
|
2449527771U, // ADR_SXTW_ZZZ_D_3
|
|
2449527771U, // ADR_UXTW_ZZZ_D_0
|
|
2449527771U, // ADR_UXTW_ZZZ_D_1
|
|
2449527771U, // ADR_UXTW_ZZZ_D_2
|
|
2449527771U, // ADR_UXTW_ZZZ_D_3
|
|
3760228925U, // AESD_ZZZ_B
|
|
2959215165U, // AESDrr
|
|
3760229072U, // AESE_ZZZ_B
|
|
2959215312U, // AESErr
|
|
3760228606U, // AESIMC_ZZ_B
|
|
543262974U, // AESIMCrr
|
|
3760228614U, // AESMC_ZZ_B
|
|
543262982U, // AESMCrr
|
|
807425373U, // ANDSWri
|
|
807425373U, // ANDSWrs
|
|
807425373U, // ANDSXri
|
|
807425373U, // ANDSXrs
|
|
3223360861U, // ANDS_PPzPP
|
|
153828U, // ANDV_VPZ_B
|
|
1646434532U, // ANDV_VPZ_D
|
|
1648548068U, // ANDV_VPZ_H
|
|
1638078692U, // ANDV_VPZ_S
|
|
807422491U, // ANDWri
|
|
807422491U, // ANDWrs
|
|
807422491U, // ANDXri
|
|
807422491U, // ANDXrs
|
|
3223357979U, // AND_PPzPP
|
|
2418067995U, // AND_ZI
|
|
3223357979U, // AND_ZPmZ_B
|
|
3223374363U, // AND_ZPmZ_D
|
|
3519089179U, // AND_ZPmZ_H
|
|
3223407131U, // AND_ZPmZ_S
|
|
2418067995U, // AND_ZZZ
|
|
543263259U, // ANDv16i8
|
|
555846171U, // ANDv8i8
|
|
3223358007U, // ASRD_ZPmI_B
|
|
3223374391U, // ASRD_ZPmI_D
|
|
3519089207U, // ASRD_ZPmI_H
|
|
3223407159U, // ASRD_ZPmI_S
|
|
3223360635U, // ASRR_ZPmZ_B
|
|
3223377019U, // ASRR_ZPmZ_D
|
|
3519091835U, // ASRR_ZPmZ_H
|
|
3223409787U, // ASRR_ZPmZ_S
|
|
807425159U, // ASRVWr
|
|
807425159U, // ASRVXr
|
|
3223360647U, // ASR_WIDE_ZPmZ_B
|
|
3519091847U, // ASR_WIDE_ZPmZ_H
|
|
3223409799U, // ASR_WIDE_ZPmZ_S
|
|
3760231559U, // ASR_WIDE_ZZZ_B
|
|
2179011719U, // ASR_WIDE_ZZZ_H
|
|
4028716167U, // ASR_WIDE_ZZZ_S
|
|
3223360647U, // ASR_ZPmI_B
|
|
3223377031U, // ASR_ZPmI_D
|
|
3519091847U, // ASR_ZPmI_H
|
|
3223409799U, // ASR_ZPmI_S
|
|
3223360647U, // ASR_ZPmZ_B
|
|
3223377031U, // ASR_ZPmZ_D
|
|
3519091847U, // ASR_ZPmZ_H
|
|
3223409799U, // ASR_ZPmZ_S
|
|
3760231559U, // ASR_ZZI_B
|
|
2418070663U, // ASR_ZZI_D
|
|
2179011719U, // ASR_ZZI_H
|
|
4028716167U, // ASR_ZZI_S
|
|
270746281U, // AUTDA
|
|
270746855U, // AUTDB
|
|
213937U, // AUTDZA
|
|
215248U, // AUTDZB
|
|
270746309U, // AUTIA
|
|
7234U, // AUTIA1716
|
|
7313U, // AUTIASP
|
|
7304U, // AUTIAZ
|
|
270746882U, // AUTIB
|
|
7243U, // AUTIB1716
|
|
7225U, // AUTIBSP
|
|
7216U, // AUTIBZ
|
|
213953U, // AUTIZA
|
|
215264U, // AUTIZB
|
|
8615U, // AXFLAG
|
|
230348U, // B
|
|
543267509U, // BCAX
|
|
2418072245U, // BCAX_ZZZZ
|
|
252846U, // BCcc
|
|
3760231064U, // BDEP_ZZZ_B
|
|
2418070168U, // BDEP_ZZZ_D
|
|
2179011224U, // BDEP_ZZZ_H
|
|
4028715672U, // BDEP_ZZZ_S
|
|
3760232586U, // BEXT_ZZZ_B
|
|
2418071690U, // BEXT_ZZZ_D
|
|
2179012746U, // BEXT_ZZZ_H
|
|
4028717194U, // BEXT_ZZZ_S
|
|
2961315868U, // BF16DOTlanev4bf16
|
|
2967607324U, // BF16DOTlanev8bf16
|
|
807426147U, // BFCVT
|
|
549556712U, // BFCVTN
|
|
2969698720U, // BFCVTN2
|
|
541136854U, // BFCVTNT_ZPmZ
|
|
541136995U, // BFCVT_ZPmZ
|
|
2686539804U, // BFDOT_ZZI
|
|
2686539804U, // BFDOT_ZZZ
|
|
2961315868U, // BFDOTv4bf16
|
|
2967607324U, // BFDOTv8bf16
|
|
2967602483U, // BFMLALB
|
|
2967602483U, // BFMLALBIdx
|
|
2967606976U, // BFMLALT
|
|
2967606976U, // BFMLALTIdx
|
|
2967601887U, // BFMMLA
|
|
2686534963U, // BFMMLA_B_ZZI
|
|
2686534963U, // BFMMLA_B_ZZZ
|
|
2686539456U, // BFMMLA_T_ZZI
|
|
2686539456U, // BFMMLA_T_ZZZ
|
|
2686534367U, // BFMMLA_ZZZ
|
|
270553387U, // BFMWri
|
|
270553387U, // BFMXri
|
|
3760231194U, // BGRP_ZZZ_B
|
|
2418070298U, // BGRP_ZZZ_D
|
|
2179011354U, // BGRP_ZZZ_H
|
|
4028715802U, // BGRP_ZZZ_S
|
|
807425360U, // BICSWrs
|
|
807425360U, // BICSXrs
|
|
3223360848U, // BICS_PPzPP
|
|
807422201U, // BICWrs
|
|
807422201U, // BICXrs
|
|
3223357689U, // BIC_PPzPP
|
|
3223357689U, // BIC_ZPmZ_B
|
|
3223374073U, // BIC_ZPmZ_D
|
|
3519088889U, // BIC_ZPmZ_H
|
|
3223406841U, // BIC_ZPmZ_S
|
|
2418067705U, // BIC_ZZZ
|
|
543262969U, // BICv16i8
|
|
813828345U, // BICv2i32
|
|
818022649U, // BICv4i16
|
|
820119801U, // BICv4i32
|
|
822216953U, // BICv8i16
|
|
555845881U, // BICv8i8
|
|
2959215356U, // BIFv16i8
|
|
2971798268U, // BIFv8i8
|
|
2959218331U, // BITv16i8
|
|
2971801243U, // BITv8i8
|
|
233372U, // BL
|
|
21517U, // BLR
|
|
807420544U, // BLRAA
|
|
23358U, // BLRAAZ
|
|
807421042U, // BLRAB
|
|
23373U, // BLRABZ
|
|
21431U, // BR
|
|
807420531U, // BRAA
|
|
23351U, // BRAAZ
|
|
807421029U, // BRAB
|
|
23366U, // BRABZ
|
|
8644U, // BRB_IALL
|
|
8622U, // BRB_INJ
|
|
265986U, // BRK
|
|
3223360779U, // BRKAS_PPzP
|
|
2130636U, // BRKA_PPmP
|
|
3223356108U, // BRKA_PPzP
|
|
3223360815U, // BRKBS_PPzP
|
|
2131209U, // BRKB_PPmP
|
|
3223356681U, // BRKB_PPzP
|
|
3223360944U, // BRKNS_PPzP
|
|
3223359912U, // BRKN_PPzP
|
|
3223360786U, // BRKPAS_PPzPP
|
|
3223356175U, // BRKPA_PPzPP
|
|
3223360822U, // BRKPBS_PPzPP
|
|
3223357207U, // BRKPB_PPzPP
|
|
2418069876U, // BSL1N_ZZZZ
|
|
2418069883U, // BSL2N_ZZZZ
|
|
2418069681U, // BSL_ZZZZ
|
|
2959216817U, // BSLv16i8
|
|
2971799729U, // BSLv8i8
|
|
252843U, // Bcc
|
|
3760228796U, // CADD_ZZI_B
|
|
2418067900U, // CADD_ZZI_D
|
|
2179008956U, // CADD_ZZI_H
|
|
4028713404U, // CADD_ZZI_S
|
|
270746763U, // CASAB
|
|
270748700U, // CASAH
|
|
270747006U, // CASALB
|
|
270748859U, // CASALH
|
|
270749559U, // CASALW
|
|
270749559U, // CASALX
|
|
270746476U, // CASAW
|
|
270746476U, // CASAX
|
|
270747618U, // CASB
|
|
270749244U, // CASH
|
|
270747212U, // CASLB
|
|
270748953U, // CASLH
|
|
270749866U, // CASLW
|
|
270749866U, // CASLX
|
|
282454U, // CASPALW
|
|
298838U, // CASPALX
|
|
279342U, // CASPAW
|
|
295726U, // CASPAX
|
|
282765U, // CASPLW
|
|
299149U, // CASPLX
|
|
283424U, // CASPW
|
|
299808U, // CASPX
|
|
270750982U, // CASW
|
|
270750982U, // CASX
|
|
1075862372U, // CBNZW
|
|
1075862372U, // CBNZX
|
|
1075862357U, // CBZW
|
|
1075862357U, // CBZX
|
|
807424430U, // CCMNWi
|
|
807424430U, // CCMNWr
|
|
807424430U, // CCMNXi
|
|
807424430U, // CCMNXr
|
|
807424725U, // CCMPWi
|
|
807424725U, // CCMPWr
|
|
807424725U, // CCMPXi
|
|
807424725U, // CCMPXr
|
|
2686507030U, // CDOT_ZZZI_D
|
|
1344362518U, // CDOT_ZZZI_S
|
|
2686507030U, // CDOT_ZZZ_D
|
|
1344362518U, // CDOT_ZZZ_S
|
|
8678U, // CFINV
|
|
3223339906U, // CLASTA_RPZ_B
|
|
3223339906U, // CLASTA_RPZ_D
|
|
3223339906U, // CLASTA_RPZ_H
|
|
3223339906U, // CLASTA_RPZ_S
|
|
3223339906U, // CLASTA_VPZ_B
|
|
3223339906U, // CLASTA_VPZ_D
|
|
3223339906U, // CLASTA_VPZ_H
|
|
3223339906U, // CLASTA_VPZ_S
|
|
3223356290U, // CLASTA_ZPZ_B
|
|
3223372674U, // CLASTA_ZPZ_D
|
|
2176910210U, // CLASTA_ZPZ_H
|
|
3223405442U, // CLASTA_ZPZ_S
|
|
3223341131U, // CLASTB_RPZ_B
|
|
3223341131U, // CLASTB_RPZ_D
|
|
3223341131U, // CLASTB_RPZ_H
|
|
3223341131U, // CLASTB_RPZ_S
|
|
3223341131U, // CLASTB_VPZ_B
|
|
3223341131U, // CLASTB_VPZ_D
|
|
3223341131U, // CLASTB_VPZ_H
|
|
3223341131U, // CLASTB_VPZ_S
|
|
3223357515U, // CLASTB_ZPZ_B
|
|
3223373899U, // CLASTB_ZPZ_D
|
|
2176911435U, // CLASTB_ZPZ_H
|
|
3223406667U, // CLASTB_ZPZ_S
|
|
23270U, // CLREX
|
|
807425409U, // CLSWr
|
|
807425409U, // CLSXr
|
|
2135425U, // CLS_ZPmZ_B
|
|
2151809U, // CLS_ZPmZ_D
|
|
272700801U, // CLS_ZPmZ_H
|
|
2184577U, // CLS_ZPmZ_S
|
|
543266177U, // CLSv16i8
|
|
545363329U, // CLSv2i32
|
|
549557633U, // CLSv4i16
|
|
551654785U, // CLSv4i32
|
|
553751937U, // CLSv8i16
|
|
555849089U, // CLSv8i8
|
|
807426911U, // CLZWr
|
|
807426911U, // CLZXr
|
|
2136927U, // CLZ_ZPmZ_B
|
|
2153311U, // CLZ_ZPmZ_D
|
|
272702303U, // CLZ_ZPmZ_H
|
|
2186079U, // CLZ_ZPmZ_S
|
|
543267679U, // CLZv16i8
|
|
545364831U, // CLZv2i32
|
|
549559135U, // CLZv4i16
|
|
551656287U, // CLZv4i32
|
|
553753439U, // CLZv8i16
|
|
555850591U, // CLZv8i8
|
|
543265652U, // CMEQv16i8
|
|
543265652U, // CMEQv16i8rz
|
|
807424884U, // CMEQv1i64
|
|
807424884U, // CMEQv1i64rz
|
|
545362804U, // CMEQv2i32
|
|
545362804U, // CMEQv2i32rz
|
|
547459956U, // CMEQv2i64
|
|
547459956U, // CMEQv2i64rz
|
|
549557108U, // CMEQv4i16
|
|
549557108U, // CMEQv4i16rz
|
|
551654260U, // CMEQv4i32
|
|
551654260U, // CMEQv4i32rz
|
|
553751412U, // CMEQv8i16
|
|
553751412U, // CMEQv8i16rz
|
|
555848564U, // CMEQv8i8
|
|
555848564U, // CMEQv8i8rz
|
|
543263342U, // CMGEv16i8
|
|
543263342U, // CMGEv16i8rz
|
|
807422574U, // CMGEv1i64
|
|
807422574U, // CMGEv1i64rz
|
|
545360494U, // CMGEv2i32
|
|
545360494U, // CMGEv2i32rz
|
|
547457646U, // CMGEv2i64
|
|
547457646U, // CMGEv2i64rz
|
|
549554798U, // CMGEv4i16
|
|
549554798U, // CMGEv4i16rz
|
|
551651950U, // CMGEv4i32
|
|
551651950U, // CMGEv4i32rz
|
|
553749102U, // CMGEv8i16
|
|
553749102U, // CMGEv8i16rz
|
|
555846254U, // CMGEv8i8
|
|
555846254U, // CMGEv8i8rz
|
|
543266445U, // CMGTv16i8
|
|
543266445U, // CMGTv16i8rz
|
|
807425677U, // CMGTv1i64
|
|
807425677U, // CMGTv1i64rz
|
|
545363597U, // CMGTv2i32
|
|
545363597U, // CMGTv2i32rz
|
|
547460749U, // CMGTv2i64
|
|
547460749U, // CMGTv2i64rz
|
|
549557901U, // CMGTv4i16
|
|
549557901U, // CMGTv4i16rz
|
|
551655053U, // CMGTv4i32
|
|
551655053U, // CMGTv4i32rz
|
|
553752205U, // CMGTv8i16
|
|
553752205U, // CMGTv8i16rz
|
|
555849357U, // CMGTv8i8
|
|
555849357U, // CMGTv8i8rz
|
|
543264466U, // CMHIv16i8
|
|
807423698U, // CMHIv1i64
|
|
545361618U, // CMHIv2i32
|
|
547458770U, // CMHIv2i64
|
|
549555922U, // CMHIv4i16
|
|
551653074U, // CMHIv4i32
|
|
553750226U, // CMHIv8i16
|
|
555847378U, // CMHIv8i8
|
|
543266164U, // CMHSv16i8
|
|
807425396U, // CMHSv1i64
|
|
545363316U, // CMHSv2i32
|
|
547460468U, // CMHSv2i64
|
|
549557620U, // CMHSv4i16
|
|
551654772U, // CMHSv4i32
|
|
553751924U, // CMHSv8i16
|
|
555849076U, // CMHSv8i8
|
|
2185298643U, // CMLA_ZZZI_H
|
|
1344357075U, // CMLA_ZZZI_S
|
|
1344307923U, // CMLA_ZZZ_B
|
|
1075888851U, // CMLA_ZZZ_D
|
|
2185298643U, // CMLA_ZZZ_H
|
|
1344357075U, // CMLA_ZZZ_S
|
|
543263373U, // CMLEv16i8rz
|
|
807422605U, // CMLEv1i64rz
|
|
545360525U, // CMLEv2i32rz
|
|
547457677U, // CMLEv2i64rz
|
|
549554829U, // CMLEv4i16rz
|
|
551651981U, // CMLEv4i32rz
|
|
553749133U, // CMLEv8i16rz
|
|
555846285U, // CMLEv8i8rz
|
|
543266648U, // CMLTv16i8rz
|
|
807425880U, // CMLTv1i64rz
|
|
545363800U, // CMLTv2i32rz
|
|
547460952U, // CMLTv2i64rz
|
|
549558104U, // CMLTv4i16rz
|
|
551655256U, // CMLTv4i32rz
|
|
553752408U, // CMLTv8i16rz
|
|
555849560U, // CMLTv8i8rz
|
|
3223360387U, // CMPEQ_PPzZI_B
|
|
3223376771U, // CMPEQ_PPzZI_D
|
|
1640043395U, // CMPEQ_PPzZI_H
|
|
3223409539U, // CMPEQ_PPzZI_S
|
|
3223360387U, // CMPEQ_PPzZZ_B
|
|
3223376771U, // CMPEQ_PPzZZ_D
|
|
1640043395U, // CMPEQ_PPzZZ_H
|
|
3223409539U, // CMPEQ_PPzZZ_S
|
|
3223360387U, // CMPEQ_WIDE_PPzZZ_B
|
|
1640043395U, // CMPEQ_WIDE_PPzZZ_H
|
|
3223409539U, // CMPEQ_WIDE_PPzZZ_S
|
|
3223358068U, // CMPGE_PPzZI_B
|
|
3223374452U, // CMPGE_PPzZI_D
|
|
1640041076U, // CMPGE_PPzZI_H
|
|
3223407220U, // CMPGE_PPzZI_S
|
|
3223358068U, // CMPGE_PPzZZ_B
|
|
3223374452U, // CMPGE_PPzZZ_D
|
|
1640041076U, // CMPGE_PPzZZ_H
|
|
3223407220U, // CMPGE_PPzZZ_S
|
|
3223358068U, // CMPGE_WIDE_PPzZZ_B
|
|
1640041076U, // CMPGE_WIDE_PPzZZ_H
|
|
3223407220U, // CMPGE_WIDE_PPzZZ_S
|
|
3223361171U, // CMPGT_PPzZI_B
|
|
3223377555U, // CMPGT_PPzZI_D
|
|
1640044179U, // CMPGT_PPzZI_H
|
|
3223410323U, // CMPGT_PPzZI_S
|
|
3223361171U, // CMPGT_PPzZZ_B
|
|
3223377555U, // CMPGT_PPzZZ_D
|
|
1640044179U, // CMPGT_PPzZZ_H
|
|
3223410323U, // CMPGT_PPzZZ_S
|
|
3223361171U, // CMPGT_WIDE_PPzZZ_B
|
|
1640044179U, // CMPGT_WIDE_PPzZZ_H
|
|
3223410323U, // CMPGT_WIDE_PPzZZ_S
|
|
3223359192U, // CMPHI_PPzZI_B
|
|
3223375576U, // CMPHI_PPzZI_D
|
|
1640042200U, // CMPHI_PPzZI_H
|
|
3223408344U, // CMPHI_PPzZI_S
|
|
3223359192U, // CMPHI_PPzZZ_B
|
|
3223375576U, // CMPHI_PPzZZ_D
|
|
1640042200U, // CMPHI_PPzZZ_H
|
|
3223408344U, // CMPHI_PPzZZ_S
|
|
3223359192U, // CMPHI_WIDE_PPzZZ_B
|
|
1640042200U, // CMPHI_WIDE_PPzZZ_H
|
|
3223408344U, // CMPHI_WIDE_PPzZZ_S
|
|
3223360890U, // CMPHS_PPzZI_B
|
|
3223377274U, // CMPHS_PPzZI_D
|
|
1640043898U, // CMPHS_PPzZI_H
|
|
3223410042U, // CMPHS_PPzZI_S
|
|
3223360890U, // CMPHS_PPzZZ_B
|
|
3223377274U, // CMPHS_PPzZZ_D
|
|
1640043898U, // CMPHS_PPzZZ_H
|
|
3223410042U, // CMPHS_PPzZZ_S
|
|
3223360890U, // CMPHS_WIDE_PPzZZ_B
|
|
1640043898U, // CMPHS_WIDE_PPzZZ_H
|
|
3223410042U, // CMPHS_WIDE_PPzZZ_S
|
|
3223358099U, // CMPLE_PPzZI_B
|
|
3223374483U, // CMPLE_PPzZI_D
|
|
1640041107U, // CMPLE_PPzZI_H
|
|
3223407251U, // CMPLE_PPzZI_S
|
|
3223358099U, // CMPLE_WIDE_PPzZZ_B
|
|
1640041107U, // CMPLE_WIDE_PPzZZ_H
|
|
3223407251U, // CMPLE_WIDE_PPzZZ_S
|
|
3223360075U, // CMPLO_PPzZI_B
|
|
3223376459U, // CMPLO_PPzZI_D
|
|
1640043083U, // CMPLO_PPzZI_H
|
|
3223409227U, // CMPLO_PPzZI_S
|
|
3223360075U, // CMPLO_WIDE_PPzZZ_B
|
|
1640043083U, // CMPLO_WIDE_PPzZZ_H
|
|
3223409227U, // CMPLO_WIDE_PPzZZ_S
|
|
3223360924U, // CMPLS_PPzZI_B
|
|
3223377308U, // CMPLS_PPzZI_D
|
|
1640043932U, // CMPLS_PPzZI_H
|
|
3223410076U, // CMPLS_PPzZI_S
|
|
3223360924U, // CMPLS_WIDE_PPzZZ_B
|
|
1640043932U, // CMPLS_WIDE_PPzZZ_H
|
|
3223410076U, // CMPLS_WIDE_PPzZZ_S
|
|
3223361374U, // CMPLT_PPzZI_B
|
|
3223377758U, // CMPLT_PPzZI_D
|
|
1640044382U, // CMPLT_PPzZI_H
|
|
3223410526U, // CMPLT_PPzZI_S
|
|
3223361374U, // CMPLT_WIDE_PPzZZ_B
|
|
1640044382U, // CMPLT_WIDE_PPzZZ_H
|
|
3223410526U, // CMPLT_WIDE_PPzZZ_S
|
|
3223358122U, // CMPNE_PPzZI_B
|
|
3223374506U, // CMPNE_PPzZI_D
|
|
1640041130U, // CMPNE_PPzZI_H
|
|
3223407274U, // CMPNE_PPzZI_S
|
|
3223358122U, // CMPNE_PPzZZ_B
|
|
3223374506U, // CMPNE_PPzZZ_D
|
|
1640041130U, // CMPNE_PPzZZ_H
|
|
3223407274U, // CMPNE_PPzZZ_S
|
|
3223358122U, // CMPNE_WIDE_PPzZZ_B
|
|
1640041130U, // CMPNE_WIDE_PPzZZ_H
|
|
3223407274U, // CMPNE_WIDE_PPzZZ_S
|
|
543266908U, // CMTSTv16i8
|
|
807426140U, // CMTSTv1i64
|
|
545364060U, // CMTSTv2i32
|
|
547461212U, // CMTSTv2i64
|
|
549558364U, // CMTSTv4i16
|
|
551655516U, // CMTSTv4i32
|
|
553752668U, // CMTSTv8i16
|
|
555849820U, // CMTSTv8i8
|
|
2136113U, // CNOT_ZPmZ_B
|
|
2152497U, // CNOT_ZPmZ_D
|
|
272701489U, // CNOT_ZPmZ_H
|
|
2185265U, // CNOT_ZPmZ_S
|
|
1881163838U, // CNTB_XPiI
|
|
1881164355U, // CNTD_XPiI
|
|
1881165437U, // CNTH_XPiI
|
|
3223343910U, // CNTP_XPP_B
|
|
3223343910U, // CNTP_XPP_D
|
|
3223343910U, // CNTP_XPP_H
|
|
3223343910U, // CNTP_XPP_S
|
|
1881168513U, // CNTW_XPiI
|
|
2135955U, // CNT_ZPmZ_B
|
|
2152339U, // CNT_ZPmZ_D
|
|
272701331U, // CNT_ZPmZ_H
|
|
2185107U, // CNT_ZPmZ_S
|
|
543266707U, // CNTv16i8
|
|
555849619U, // CNTv8i8
|
|
3223377505U, // COMPACT_ZPZ_D
|
|
3223410273U, // COMPACT_ZPZ_S
|
|
318746U, // CPYE
|
|
318809U, // CPYEN
|
|
318895U, // CPYERN
|
|
319783U, // CPYERT
|
|
319268U, // CPYERTN
|
|
319017U, // CPYERTRN
|
|
319515U, // CPYERTWN
|
|
319697U, // CPYET
|
|
319172U, // CPYETN
|
|
318953U, // CPYETRN
|
|
319451U, // CPYETWN
|
|
319393U, // CPYEWN
|
|
319840U, // CPYEWT
|
|
319331U, // CPYEWTN
|
|
319086U, // CPYEWTRN
|
|
319584U, // CPYEWTWN
|
|
318723U, // CPYFE
|
|
318783U, // CPYFEN
|
|
318885U, // CPYFERN
|
|
319773U, // CPYFERT
|
|
319257U, // CPYFERTN
|
|
319005U, // CPYFERTRN
|
|
319503U, // CPYFERTWN
|
|
319671U, // CPYFET
|
|
319143U, // CPYFETN
|
|
318942U, // CPYFETRN
|
|
319440U, // CPYFETWN
|
|
319383U, // CPYFEWN
|
|
319830U, // CPYFEWT
|
|
319320U, // CPYFEWTN
|
|
319074U, // CPYFEWTRN
|
|
319572U, // CPYFEWTWN
|
|
318753U, // CPYFM
|
|
318817U, // CPYFMN
|
|
318904U, // CPYFMRN
|
|
319792U, // CPYFMRT
|
|
319278U, // CPYFMRTN
|
|
319028U, // CPYFMRTRN
|
|
319526U, // CPYFMRTWN
|
|
319705U, // CPYFMT
|
|
319181U, // CPYFMTN
|
|
318963U, // CPYFMTRN
|
|
319461U, // CPYFMTWN
|
|
319402U, // CPYFMWN
|
|
319849U, // CPYFMWT
|
|
319341U, // CPYFMWTN
|
|
319097U, // CPYFMWTRN
|
|
319595U, // CPYFMWTWN
|
|
319641U, // CPYFP
|
|
318851U, // CPYFPN
|
|
318923U, // CPYFPRN
|
|
319811U, // CPYFPRT
|
|
319299U, // CPYFPRTN
|
|
319051U, // CPYFPRTRN
|
|
319549U, // CPYFPRTWN
|
|
319739U, // CPYFPT
|
|
319219U, // CPYFPTN
|
|
318984U, // CPYFPTRN
|
|
319482U, // CPYFPTWN
|
|
319421U, // CPYFPWN
|
|
319868U, // CPYFPWT
|
|
319362U, // CPYFPWTN
|
|
319120U, // CPYFPWTRN
|
|
319618U, // CPYFPWTWN
|
|
318776U, // CPYM
|
|
318843U, // CPYMN
|
|
318914U, // CPYMRN
|
|
319802U, // CPYMRT
|
|
319289U, // CPYMRTN
|
|
319040U, // CPYMRTRN
|
|
319538U, // CPYMRTWN
|
|
319731U, // CPYMT
|
|
319210U, // CPYMTN
|
|
318974U, // CPYMTRN
|
|
319472U, // CPYMTWN
|
|
319412U, // CPYMWN
|
|
319859U, // CPYMWT
|
|
319352U, // CPYMWTN
|
|
319109U, // CPYMWTRN
|
|
319607U, // CPYMWTWN
|
|
319664U, // CPYP
|
|
318877U, // CPYPN
|
|
318933U, // CPYPRN
|
|
319821U, // CPYPRT
|
|
319310U, // CPYPRTN
|
|
319063U, // CPYPRTRN
|
|
319561U, // CPYPRTWN
|
|
319765U, // CPYPT
|
|
319248U, // CPYPTN
|
|
318995U, // CPYPTRN
|
|
319493U, // CPYPTWN
|
|
319431U, // CPYPWN
|
|
319878U, // CPYPWT
|
|
319373U, // CPYPWTN
|
|
319132U, // CPYPWTRN
|
|
319630U, // CPYPWTWN
|
|
2136862U, // CPY_ZPmI_B
|
|
2153246U, // CPY_ZPmI_D
|
|
2151750430U, // CPY_ZPmI_H
|
|
2186014U, // CPY_ZPmI_S
|
|
2136862U, // CPY_ZPmR_B
|
|
2153246U, // CPY_ZPmR_D
|
|
2420185886U, // CPY_ZPmR_H
|
|
2186014U, // CPY_ZPmR_S
|
|
2136862U, // CPY_ZPmV_B
|
|
2153246U, // CPY_ZPmV_D
|
|
2420185886U, // CPY_ZPmV_H
|
|
2186014U, // CPY_ZPmV_S
|
|
3223362334U, // CPY_ZPzI_B
|
|
3223378718U, // CPY_ZPzI_D
|
|
1640045342U, // CPY_ZPzI_H
|
|
3223411486U, // CPY_ZPzI_S
|
|
807420926U, // CRC32Brr
|
|
807421103U, // CRC32CBrr
|
|
807423040U, // CRC32CHrr
|
|
807426514U, // CRC32CWrr
|
|
807426774U, // CRC32CXrr
|
|
807422876U, // CRC32Hrr
|
|
807426456U, // CRC32Wrr
|
|
807426713U, // CRC32Xrr
|
|
807423996U, // CSELWr
|
|
807423996U, // CSELXr
|
|
807422221U, // CSINCWr
|
|
807422221U, // CSINCXr
|
|
807426360U, // CSINVWr
|
|
807426360U, // CSINVXr
|
|
807422784U, // CSNEGWr
|
|
807422784U, // CSNEGXr
|
|
807424890U, // CTERMEQ_WW
|
|
807424890U, // CTERMEQ_XX
|
|
807422625U, // CTERMNE_WW
|
|
807422625U, // CTERMNE_XX
|
|
262208U, // DCPS1
|
|
262636U, // DCPS2
|
|
262702U, // DCPS3
|
|
2686469306U, // DECB_XPiI
|
|
2686470557U, // DECD_XPiI
|
|
2686503325U, // DECD_ZPiI
|
|
2686471243U, // DECH_XPiI
|
|
39914571U, // DECH_ZPiI
|
|
3760214638U, // DECP_XP_B
|
|
2418037358U, // DECP_XP_D
|
|
1881166446U, // DECP_XP_H
|
|
4028650094U, // DECP_XP_S
|
|
1075892846U, // DECP_ZP_D
|
|
1648431726U, // DECP_ZP_H
|
|
1344361070U, // DECP_ZP_S
|
|
2686474717U, // DECW_XPiI
|
|
2686540253U, // DECW_ZPiI
|
|
329362U, // DMB
|
|
8660U, // DRPS
|
|
329704U, // DSB
|
|
346088U, // DSBnXS
|
|
2954940767U, // DUPM_ZI
|
|
3223360314U, // DUP_ZI_B
|
|
3491812154U, // DUP_ZI_D
|
|
42013498U, // DUP_ZI_H
|
|
3760280378U, // DUP_ZI_S
|
|
807441210U, // DUP_ZR_B
|
|
807457594U, // DUP_ZR_D
|
|
1654723386U, // DUP_ZR_H
|
|
807490362U, // DUP_ZR_S
|
|
3760231226U, // DUP_ZZI_B
|
|
2418070330U, // DUP_ZZI_D
|
|
4058059578U, // DUP_ZZI_H
|
|
4073034554U, // DUP_ZZI_Q
|
|
4028715834U, // DUP_ZZI_S
|
|
538990912U, // DUPi16
|
|
538990912U, // DUPi32
|
|
538990912U, // DUPi64
|
|
538990912U, // DUPi8
|
|
811701050U, // DUPv16i8gpr
|
|
543265594U, // DUPv16i8lane
|
|
813798202U, // DUPv2i32gpr
|
|
545362746U, // DUPv2i32lane
|
|
815895354U, // DUPv2i64gpr
|
|
547459898U, // DUPv2i64lane
|
|
817992506U, // DUPv4i16gpr
|
|
549557050U, // DUPv4i16lane
|
|
820089658U, // DUPv4i32gpr
|
|
551654202U, // DUPv4i32lane
|
|
822186810U, // DUPv8i16gpr
|
|
553751354U, // DUPv8i16lane
|
|
824283962U, // DUPv8i8gpr
|
|
555848506U, // DUPv8i8lane
|
|
807424436U, // EONWrs
|
|
807424436U, // EONXrs
|
|
543261224U, // EOR3
|
|
2418065960U, // EOR3_ZZZZ
|
|
1344312922U, // EORBT_ZZZ_B
|
|
1075893850U, // EORBT_ZZZ_D
|
|
2185303642U, // EORBT_ZZZ_H
|
|
1344362074U, // EORBT_ZZZ_S
|
|
3223361025U, // EORS_PPzPP
|
|
1344309316U, // EORTB_ZZZ_B
|
|
1075890244U, // EORTB_ZZZ_D
|
|
2185300036U, // EORTB_ZZZ_H
|
|
1344358468U, // EORTB_ZZZ_S
|
|
153937U, // EORV_VPZ_B
|
|
1646434641U, // EORV_VPZ_D
|
|
1648548177U, // EORV_VPZ_H
|
|
1638078801U, // EORV_VPZ_S
|
|
807425120U, // EORWri
|
|
807425120U, // EORWrs
|
|
807425120U, // EORXri
|
|
807425120U, // EORXrs
|
|
3223360608U, // EOR_PPzPP
|
|
2418070624U, // EOR_ZI
|
|
3223360608U, // EOR_ZPmZ_B
|
|
3223376992U, // EOR_ZPmZ_D
|
|
3519091808U, // EOR_ZPmZ_H
|
|
3223409760U, // EOR_ZPmZ_S
|
|
2418070624U, // EOR_ZZZ
|
|
543265888U, // EORv16i8
|
|
555848800U, // EORv8i8
|
|
8665U, // ERET
|
|
8591U, // ERETAA
|
|
8598U, // ERETAB
|
|
3223356305U, // EXTRACT_ZPMXI_H_B
|
|
3223372689U, // EXTRACT_ZPMXI_H_D
|
|
3519087505U, // EXTRACT_ZPMXI_H_H
|
|
3519382417U, // EXTRACT_ZPMXI_H_Q
|
|
3223405457U, // EXTRACT_ZPMXI_H_S
|
|
3223356305U, // EXTRACT_ZPMXI_V_B
|
|
3223372689U, // EXTRACT_ZPMXI_V_D
|
|
3519087505U, // EXTRACT_ZPMXI_V_H
|
|
3519382417U, // EXTRACT_ZPMXI_V_Q
|
|
3223405457U, // EXTRACT_ZPMXI_V_S
|
|
807425197U, // EXTRWrri
|
|
807425197U, // EXTRXrri
|
|
3760232587U, // EXT_ZZI
|
|
2136203U, // EXT_ZZI_B
|
|
543266955U, // EXTv16i8
|
|
555849867U, // EXTv8i8
|
|
807422338U, // FABD16
|
|
807422338U, // FABD32
|
|
807422338U, // FABD64
|
|
3223374210U, // FABD_ZPmZ_D
|
|
3519089026U, // FABD_ZPmZ_H
|
|
3223406978U, // FABD_ZPmZ_S
|
|
545360258U, // FABDv2f32
|
|
547457410U, // FABDv2f64
|
|
549554562U, // FABDv4f16
|
|
551651714U, // FABDv4f32
|
|
553748866U, // FABDv8f16
|
|
807425314U, // FABSDr
|
|
807425314U, // FABSHr
|
|
807425314U, // FABSSr
|
|
2151714U, // FABS_ZPmZ_D
|
|
272700706U, // FABS_ZPmZ_H
|
|
2184482U, // FABS_ZPmZ_S
|
|
545363234U, // FABSv2f32
|
|
547460386U, // FABSv2f64
|
|
549557538U, // FABSv4f16
|
|
551654690U, // FABSv4f32
|
|
553751842U, // FABSv8f16
|
|
807422557U, // FACGE16
|
|
807422557U, // FACGE32
|
|
807422557U, // FACGE64
|
|
3223374429U, // FACGE_PPzZZ_D
|
|
1640041053U, // FACGE_PPzZZ_H
|
|
3223407197U, // FACGE_PPzZZ_S
|
|
545360477U, // FACGEv2f32
|
|
547457629U, // FACGEv2f64
|
|
549554781U, // FACGEv4f16
|
|
551651933U, // FACGEv4f32
|
|
553749085U, // FACGEv8f16
|
|
807425660U, // FACGT16
|
|
807425660U, // FACGT32
|
|
807425660U, // FACGT64
|
|
3223377532U, // FACGT_PPzZZ_D
|
|
1640044156U, // FACGT_PPzZZ_H
|
|
3223410300U, // FACGT_PPzZZ_S
|
|
545363580U, // FACGTv2f32
|
|
547460732U, // FACGTv2f64
|
|
549557884U, // FACGTv4f16
|
|
551655036U, // FACGTv4f32
|
|
553752188U, // FACGTv8f16
|
|
48399010U, // FADDA_VPZ_D
|
|
2197996194U, // FADDA_VPZ_H
|
|
52626082U, // FADDA_VPZ_S
|
|
807422417U, // FADDDrr
|
|
807422417U, // FADDHrr
|
|
3223376524U, // FADDP_ZPmZZ_D
|
|
3519091340U, // FADDP_ZPmZZ_H
|
|
3223409292U, // FADDP_ZPmZZ_S
|
|
545362572U, // FADDPv2f32
|
|
547459724U, // FADDPv2f64
|
|
538989196U, // FADDPv2i16p
|
|
538989196U, // FADDPv2i32p
|
|
538989196U, // FADDPv2i64p
|
|
549556876U, // FADDPv4f16
|
|
551654028U, // FADDPv4f32
|
|
553751180U, // FADDPv8f16
|
|
807422417U, // FADDSrr
|
|
1646434511U, // FADDV_VPZ_D
|
|
1648548047U, // FADDV_VPZ_H
|
|
1638078671U, // FADDV_VPZ_S
|
|
3223374289U, // FADD_ZPmI_D
|
|
3519089105U, // FADD_ZPmI_H
|
|
3223407057U, // FADD_ZPmI_S
|
|
3223374289U, // FADD_ZPmZ_D
|
|
3519089105U, // FADD_ZPmZ_H
|
|
3223407057U, // FADD_ZPmZ_S
|
|
2418067921U, // FADD_ZZZ_D
|
|
2179008977U, // FADD_ZZZ_H
|
|
4028713425U, // FADD_ZZZ_S
|
|
545360337U, // FADDv2f32
|
|
547457489U, // FADDv2f64
|
|
549554641U, // FADDv4f16
|
|
551651793U, // FADDv4f32
|
|
553748945U, // FADDv8f16
|
|
3223374267U, // FCADD_ZPmZ_D
|
|
3519089083U, // FCADD_ZPmZ_H
|
|
3223407035U, // FCADD_ZPmZ_S
|
|
545360315U, // FCADDv2f32
|
|
547457467U, // FCADDv2f64
|
|
549554619U, // FCADDv4f16
|
|
551651771U, // FCADDv4f32
|
|
553748923U, // FCADDv8f16
|
|
807424724U, // FCCMPDrr
|
|
807422657U, // FCCMPEDrr
|
|
807422657U, // FCCMPEHrr
|
|
807422657U, // FCCMPESrr
|
|
807424724U, // FCCMPHrr
|
|
807424724U, // FCCMPSrr
|
|
807424883U, // FCMEQ16
|
|
807424883U, // FCMEQ32
|
|
807424883U, // FCMEQ64
|
|
3223376755U, // FCMEQ_PPzZ0_D
|
|
1640043379U, // FCMEQ_PPzZ0_H
|
|
3223409523U, // FCMEQ_PPzZ0_S
|
|
3223376755U, // FCMEQ_PPzZZ_D
|
|
1640043379U, // FCMEQ_PPzZZ_H
|
|
3223409523U, // FCMEQ_PPzZZ_S
|
|
807424883U, // FCMEQv1i16rz
|
|
807424883U, // FCMEQv1i32rz
|
|
807424883U, // FCMEQv1i64rz
|
|
545362803U, // FCMEQv2f32
|
|
547459955U, // FCMEQv2f64
|
|
545362803U, // FCMEQv2i32rz
|
|
547459955U, // FCMEQv2i64rz
|
|
549557107U, // FCMEQv4f16
|
|
551654259U, // FCMEQv4f32
|
|
549557107U, // FCMEQv4i16rz
|
|
551654259U, // FCMEQv4i32rz
|
|
553751411U, // FCMEQv8f16
|
|
553751411U, // FCMEQv8i16rz
|
|
807422573U, // FCMGE16
|
|
807422573U, // FCMGE32
|
|
807422573U, // FCMGE64
|
|
3223374445U, // FCMGE_PPzZ0_D
|
|
1640041069U, // FCMGE_PPzZ0_H
|
|
3223407213U, // FCMGE_PPzZ0_S
|
|
3223374445U, // FCMGE_PPzZZ_D
|
|
1640041069U, // FCMGE_PPzZZ_H
|
|
3223407213U, // FCMGE_PPzZZ_S
|
|
807422573U, // FCMGEv1i16rz
|
|
807422573U, // FCMGEv1i32rz
|
|
807422573U, // FCMGEv1i64rz
|
|
545360493U, // FCMGEv2f32
|
|
547457645U, // FCMGEv2f64
|
|
545360493U, // FCMGEv2i32rz
|
|
547457645U, // FCMGEv2i64rz
|
|
549554797U, // FCMGEv4f16
|
|
551651949U, // FCMGEv4f32
|
|
549554797U, // FCMGEv4i16rz
|
|
551651949U, // FCMGEv4i32rz
|
|
553749101U, // FCMGEv8f16
|
|
553749101U, // FCMGEv8i16rz
|
|
807425676U, // FCMGT16
|
|
807425676U, // FCMGT32
|
|
807425676U, // FCMGT64
|
|
3223377548U, // FCMGT_PPzZ0_D
|
|
1640044172U, // FCMGT_PPzZ0_H
|
|
3223410316U, // FCMGT_PPzZ0_S
|
|
3223377548U, // FCMGT_PPzZZ_D
|
|
1640044172U, // FCMGT_PPzZZ_H
|
|
3223410316U, // FCMGT_PPzZZ_S
|
|
807425676U, // FCMGTv1i16rz
|
|
807425676U, // FCMGTv1i32rz
|
|
807425676U, // FCMGTv1i64rz
|
|
545363596U, // FCMGTv2f32
|
|
547460748U, // FCMGTv2f64
|
|
545363596U, // FCMGTv2i32rz
|
|
547460748U, // FCMGTv2i64rz
|
|
549557900U, // FCMGTv4f16
|
|
551655052U, // FCMGTv4f32
|
|
549557900U, // FCMGTv4i16rz
|
|
551655052U, // FCMGTv4i32rz
|
|
553752204U, // FCMGTv8f16
|
|
553752204U, // FCMGTv8i16rz
|
|
3223372498U, // FCMLA_ZPmZZ_D
|
|
3519087314U, // FCMLA_ZPmZZ_H
|
|
3223405266U, // FCMLA_ZPmZZ_S
|
|
2185298642U, // FCMLA_ZZZI_H
|
|
1344357074U, // FCMLA_ZZZI_S
|
|
2961310418U, // FCMLAv2f32
|
|
2963407570U, // FCMLAv2f64
|
|
2965504722U, // FCMLAv4f16
|
|
2965504722U, // FCMLAv4f16_indexed
|
|
2967601874U, // FCMLAv4f32
|
|
2967601874U, // FCMLAv4f32_indexed
|
|
2969699026U, // FCMLAv8f16
|
|
2969699026U, // FCMLAv8f16_indexed
|
|
3223374476U, // FCMLE_PPzZ0_D
|
|
1640041100U, // FCMLE_PPzZ0_H
|
|
3223407244U, // FCMLE_PPzZ0_S
|
|
807422604U, // FCMLEv1i16rz
|
|
807422604U, // FCMLEv1i32rz
|
|
807422604U, // FCMLEv1i64rz
|
|
545360524U, // FCMLEv2i32rz
|
|
547457676U, // FCMLEv2i64rz
|
|
549554828U, // FCMLEv4i16rz
|
|
551651980U, // FCMLEv4i32rz
|
|
553749132U, // FCMLEv8i16rz
|
|
3223377751U, // FCMLT_PPzZ0_D
|
|
1640044375U, // FCMLT_PPzZ0_H
|
|
3223410519U, // FCMLT_PPzZ0_S
|
|
807425879U, // FCMLTv1i16rz
|
|
807425879U, // FCMLTv1i32rz
|
|
807425879U, // FCMLTv1i64rz
|
|
545363799U, // FCMLTv2i32rz
|
|
547460951U, // FCMLTv2i64rz
|
|
549558103U, // FCMLTv4i16rz
|
|
551655255U, // FCMLTv4i32rz
|
|
553752407U, // FCMLTv8i16rz
|
|
3223374490U, // FCMNE_PPzZ0_D
|
|
1640041114U, // FCMNE_PPzZ0_H
|
|
3223407258U, // FCMNE_PPzZ0_S
|
|
3223374490U, // FCMNE_PPzZZ_D
|
|
1640041114U, // FCMNE_PPzZZ_H
|
|
3223407258U, // FCMNE_PPzZZ_S
|
|
54547163U, // FCMPDri
|
|
807424731U, // FCMPDrr
|
|
54545097U, // FCMPEDri
|
|
807422665U, // FCMPEDrr
|
|
54545097U, // FCMPEHri
|
|
807422665U, // FCMPEHrr
|
|
54545097U, // FCMPESri
|
|
807422665U, // FCMPESrr
|
|
54547163U, // FCMPHri
|
|
807424731U, // FCMPHrr
|
|
54547163U, // FCMPSri
|
|
807424731U, // FCMPSrr
|
|
3223376472U, // FCMUO_PPzZZ_D
|
|
1640043096U, // FCMUO_PPzZZ_H
|
|
3223409240U, // FCMUO_PPzZZ_S
|
|
2153245U, // FCPY_ZPmI_D
|
|
272702237U, // FCPY_ZPmI_H
|
|
2186013U, // FCPY_ZPmI_S
|
|
807423995U, // FCSELDrrr
|
|
807423995U, // FCSELHrrr
|
|
807423995U, // FCSELSrrr
|
|
807425306U, // FCVTASUWDr
|
|
807425306U, // FCVTASUWHr
|
|
807425306U, // FCVTASUWSr
|
|
807425306U, // FCVTASUXDr
|
|
807425306U, // FCVTASUXHr
|
|
807425306U, // FCVTASUXSr
|
|
807425306U, // FCVTASv1f16
|
|
807425306U, // FCVTASv1i32
|
|
807425306U, // FCVTASv1i64
|
|
545363226U, // FCVTASv2f32
|
|
547460378U, // FCVTASv2f64
|
|
549557530U, // FCVTASv4f16
|
|
551654682U, // FCVTASv4f32
|
|
553751834U, // FCVTASv8f16
|
|
807426199U, // FCVTAUUWDr
|
|
807426199U, // FCVTAUUWHr
|
|
807426199U, // FCVTAUUWSr
|
|
807426199U, // FCVTAUUXDr
|
|
807426199U, // FCVTAUUXHr
|
|
807426199U, // FCVTAUUXSr
|
|
807426199U, // FCVTAUv1f16
|
|
807426199U, // FCVTAUv1i32
|
|
807426199U, // FCVTAUv1i64
|
|
545364119U, // FCVTAUv2f32
|
|
547461271U, // FCVTAUv2f64
|
|
549558423U, // FCVTAUv4f16
|
|
551655575U, // FCVTAUv4f32
|
|
553752727U, // FCVTAUv8f16
|
|
807426148U, // FCVTDHr
|
|
807426148U, // FCVTDSr
|
|
807426148U, // FCVTHDr
|
|
807426148U, // FCVTHSr
|
|
2185095U, // FCVTLT_ZPmZ_HtoS
|
|
2152327U, // FCVTLT_ZPmZ_StoD
|
|
547459298U, // FCVTLv2i32
|
|
551653602U, // FCVTLv4i16
|
|
547455322U, // FCVTLv4i32
|
|
551649626U, // FCVTLv8i16
|
|
807425443U, // FCVTMSUWDr
|
|
807425443U, // FCVTMSUWHr
|
|
807425443U, // FCVTMSUWSr
|
|
807425443U, // FCVTMSUXDr
|
|
807425443U, // FCVTMSUXHr
|
|
807425443U, // FCVTMSUXSr
|
|
807425443U, // FCVTMSv1f16
|
|
807425443U, // FCVTMSv1i32
|
|
807425443U, // FCVTMSv1i64
|
|
545363363U, // FCVTMSv2f32
|
|
547460515U, // FCVTMSv2f64
|
|
549557667U, // FCVTMSv4f16
|
|
551654819U, // FCVTMSv4f32
|
|
553751971U, // FCVTMSv8f16
|
|
807426215U, // FCVTMUUWDr
|
|
807426215U, // FCVTMUUWHr
|
|
807426215U, // FCVTMUUWSr
|
|
807426215U, // FCVTMUUXDr
|
|
807426215U, // FCVTMUUXHr
|
|
807426215U, // FCVTMUUXSr
|
|
807426215U, // FCVTMUv1f16
|
|
807426215U, // FCVTMUv1i32
|
|
807426215U, // FCVTMUv1i64
|
|
545364135U, // FCVTMUv2f32
|
|
547461287U, // FCVTMUv2f64
|
|
549558439U, // FCVTMUv4f16
|
|
551655591U, // FCVTMUv4f32
|
|
553752743U, // FCVTMUv8f16
|
|
807425469U, // FCVTNSUWDr
|
|
807425469U, // FCVTNSUWHr
|
|
807425469U, // FCVTNSUWSr
|
|
807425469U, // FCVTNSUXDr
|
|
807425469U, // FCVTNSUXHr
|
|
807425469U, // FCVTNSUXSr
|
|
807425469U, // FCVTNSv1f16
|
|
807425469U, // FCVTNSv1i32
|
|
807425469U, // FCVTNSv1i64
|
|
545363389U, // FCVTNSv2f32
|
|
547460541U, // FCVTNSv2f64
|
|
549557693U, // FCVTNSv4f16
|
|
551654845U, // FCVTNSv4f32
|
|
553751997U, // FCVTNSv8f16
|
|
2185175U, // FCVTNT_ZPmZ_DtoS
|
|
541136855U, // FCVTNT_ZPmZ_StoH
|
|
807426223U, // FCVTNUUWDr
|
|
807426223U, // FCVTNUUWHr
|
|
807426223U, // FCVTNUUWSr
|
|
807426223U, // FCVTNUUXDr
|
|
807426223U, // FCVTNUUXHr
|
|
807426223U, // FCVTNUUXSr
|
|
807426223U, // FCVTNUv1f16
|
|
807426223U, // FCVTNUv1i32
|
|
807426223U, // FCVTNUv1i64
|
|
545364143U, // FCVTNUv2f32
|
|
547461295U, // FCVTNUv2f64
|
|
549558447U, // FCVTNUv4f16
|
|
551655599U, // FCVTNUv4f32
|
|
553752751U, // FCVTNUv8f16
|
|
545362409U, // FCVTNv2i32
|
|
549556713U, // FCVTNv4i16
|
|
2967601569U, // FCVTNv4i32
|
|
2969698721U, // FCVTNv8i16
|
|
807425516U, // FCVTPSUWDr
|
|
807425516U, // FCVTPSUWHr
|
|
807425516U, // FCVTPSUWSr
|
|
807425516U, // FCVTPSUXDr
|
|
807425516U, // FCVTPSUXHr
|
|
807425516U, // FCVTPSUXSr
|
|
807425516U, // FCVTPSv1f16
|
|
807425516U, // FCVTPSv1i32
|
|
807425516U, // FCVTPSv1i64
|
|
545363436U, // FCVTPSv2f32
|
|
547460588U, // FCVTPSv2f64
|
|
549557740U, // FCVTPSv4f16
|
|
551654892U, // FCVTPSv4f32
|
|
553752044U, // FCVTPSv8f16
|
|
807426231U, // FCVTPUUWDr
|
|
807426231U, // FCVTPUUWHr
|
|
807426231U, // FCVTPUUWSr
|
|
807426231U, // FCVTPUUXDr
|
|
807426231U, // FCVTPUUXHr
|
|
807426231U, // FCVTPUUXSr
|
|
807426231U, // FCVTPUv1f16
|
|
807426231U, // FCVTPUv1i32
|
|
807426231U, // FCVTPUv1i64
|
|
545364151U, // FCVTPUv2f32
|
|
547461303U, // FCVTPUv2f64
|
|
549558455U, // FCVTPUv4f16
|
|
551655607U, // FCVTPUv4f32
|
|
553752759U, // FCVTPUv8f16
|
|
807426148U, // FCVTSDr
|
|
807426148U, // FCVTSHr
|
|
2185229U, // FCVTXNT_ZPmZ_DtoS
|
|
807424543U, // FCVTXNv1i64
|
|
545362463U, // FCVTXNv2f32
|
|
2967601623U, // FCVTXNv4f32
|
|
2185997U, // FCVTX_ZPmZ_DtoS
|
|
807425569U, // FCVTZSSWDri
|
|
807425569U, // FCVTZSSWHri
|
|
807425569U, // FCVTZSSWSri
|
|
807425569U, // FCVTZSSXDri
|
|
807425569U, // FCVTZSSXHri
|
|
807425569U, // FCVTZSSXSri
|
|
807425569U, // FCVTZSUWDr
|
|
807425569U, // FCVTZSUWHr
|
|
807425569U, // FCVTZSUWSr
|
|
807425569U, // FCVTZSUXDr
|
|
807425569U, // FCVTZSUXHr
|
|
807425569U, // FCVTZSUXSr
|
|
2151969U, // FCVTZS_ZPmZ_DtoD
|
|
2184737U, // FCVTZS_ZPmZ_DtoS
|
|
2151969U, // FCVTZS_ZPmZ_HtoD
|
|
272700961U, // FCVTZS_ZPmZ_HtoH
|
|
2184737U, // FCVTZS_ZPmZ_HtoS
|
|
2151969U, // FCVTZS_ZPmZ_StoD
|
|
2184737U, // FCVTZS_ZPmZ_StoS
|
|
807425569U, // FCVTZSd
|
|
807425569U, // FCVTZSh
|
|
807425569U, // FCVTZSs
|
|
807425569U, // FCVTZSv1f16
|
|
807425569U, // FCVTZSv1i32
|
|
807425569U, // FCVTZSv1i64
|
|
545363489U, // FCVTZSv2f32
|
|
547460641U, // FCVTZSv2f64
|
|
545363489U, // FCVTZSv2i32_shift
|
|
547460641U, // FCVTZSv2i64_shift
|
|
549557793U, // FCVTZSv4f16
|
|
551654945U, // FCVTZSv4f32
|
|
549557793U, // FCVTZSv4i16_shift
|
|
551654945U, // FCVTZSv4i32_shift
|
|
553752097U, // FCVTZSv8f16
|
|
553752097U, // FCVTZSv8i16_shift
|
|
807426239U, // FCVTZUSWDri
|
|
807426239U, // FCVTZUSWHri
|
|
807426239U, // FCVTZUSWSri
|
|
807426239U, // FCVTZUSXDri
|
|
807426239U, // FCVTZUSXHri
|
|
807426239U, // FCVTZUSXSri
|
|
807426239U, // FCVTZUUWDr
|
|
807426239U, // FCVTZUUWHr
|
|
807426239U, // FCVTZUUWSr
|
|
807426239U, // FCVTZUUXDr
|
|
807426239U, // FCVTZUUXHr
|
|
807426239U, // FCVTZUUXSr
|
|
2152639U, // FCVTZU_ZPmZ_DtoD
|
|
2185407U, // FCVTZU_ZPmZ_DtoS
|
|
2152639U, // FCVTZU_ZPmZ_HtoD
|
|
272701631U, // FCVTZU_ZPmZ_HtoH
|
|
2185407U, // FCVTZU_ZPmZ_HtoS
|
|
2152639U, // FCVTZU_ZPmZ_StoD
|
|
2185407U, // FCVTZU_ZPmZ_StoS
|
|
807426239U, // FCVTZUd
|
|
807426239U, // FCVTZUh
|
|
807426239U, // FCVTZUs
|
|
807426239U, // FCVTZUv1f16
|
|
807426239U, // FCVTZUv1i32
|
|
807426239U, // FCVTZUv1i64
|
|
545364159U, // FCVTZUv2f32
|
|
547461311U, // FCVTZUv2f64
|
|
545364159U, // FCVTZUv2i32_shift
|
|
547461311U, // FCVTZUv2i64_shift
|
|
549558463U, // FCVTZUv4f16
|
|
551655615U, // FCVTZUv4f32
|
|
549558463U, // FCVTZUv4i16_shift
|
|
551655615U, // FCVTZUv4i32_shift
|
|
553752767U, // FCVTZUv8f16
|
|
553752767U, // FCVTZUv8i16_shift
|
|
541136996U, // FCVT_ZPmZ_DtoH
|
|
2185316U, // FCVT_ZPmZ_DtoS
|
|
2152548U, // FCVT_ZPmZ_HtoD
|
|
2185316U, // FCVT_ZPmZ_HtoS
|
|
2152548U, // FCVT_ZPmZ_StoD
|
|
541136996U, // FCVT_ZPmZ_StoH
|
|
807426287U, // FDIVDrr
|
|
807426287U, // FDIVHrr
|
|
3223377102U, // FDIVR_ZPmZ_D
|
|
3519091918U, // FDIVR_ZPmZ_H
|
|
3223409870U, // FDIVR_ZPmZ_S
|
|
807426287U, // FDIVSrr
|
|
3223378159U, // FDIV_ZPmZ_D
|
|
3519092975U, // FDIV_ZPmZ_H
|
|
3223410927U, // FDIV_ZPmZ_S
|
|
545364207U, // FDIVv2f32
|
|
547461359U, // FDIVv2f64
|
|
549558511U, // FDIVv4f16
|
|
551655663U, // FDIVv4f32
|
|
553752815U, // FDIVv8f16
|
|
807457593U, // FDUP_ZI_D
|
|
56693561U, // FDUP_ZI_H
|
|
807490361U, // FDUP_ZI_S
|
|
2418066235U, // FEXPA_ZZ_D
|
|
1642136379U, // FEXPA_ZZ_H
|
|
4028711739U, // FEXPA_ZZ_S
|
|
807425577U, // FJCVTZS
|
|
2147572U, // FLOGB_ZPmZ_D
|
|
272696564U, // FLOGB_ZPmZ_H
|
|
2180340U, // FLOGB_ZPmZ_S
|
|
807422453U, // FMADDDrrr
|
|
807422453U, // FMADDHrrr
|
|
807422453U, // FMADDSrrr
|
|
3223374190U, // FMAD_ZPmZZ_D
|
|
3519089006U, // FMAD_ZPmZZ_H
|
|
3223406958U, // FMAD_ZPmZZ_S
|
|
807426747U, // FMAXDrr
|
|
807426747U, // FMAXHrr
|
|
807424343U, // FMAXNMDrr
|
|
807424343U, // FMAXNMHrr
|
|
3223376618U, // FMAXNMP_ZPmZZ_D
|
|
3519091434U, // FMAXNMP_ZPmZZ_H
|
|
3223409386U, // FMAXNMP_ZPmZZ_S
|
|
545362666U, // FMAXNMPv2f32
|
|
547459818U, // FMAXNMPv2f64
|
|
538989290U, // FMAXNMPv2i16p
|
|
538989290U, // FMAXNMPv2i32p
|
|
538989290U, // FMAXNMPv2i64p
|
|
549556970U, // FMAXNMPv4f16
|
|
551654122U, // FMAXNMPv4f32
|
|
553751274U, // FMAXNMPv8f16
|
|
807424343U, // FMAXNMSrr
|
|
1646434586U, // FMAXNMV_VPZ_D
|
|
1648548122U, // FMAXNMV_VPZ_H
|
|
1638078746U, // FMAXNMV_VPZ_S
|
|
538990874U, // FMAXNMVv4i16v
|
|
538990874U, // FMAXNMVv4i32v
|
|
538990874U, // FMAXNMVv8i16v
|
|
3223376215U, // FMAXNM_ZPmI_D
|
|
3519091031U, // FMAXNM_ZPmI_H
|
|
3223408983U, // FMAXNM_ZPmI_S
|
|
3223376215U, // FMAXNM_ZPmZ_D
|
|
3519091031U, // FMAXNM_ZPmZ_H
|
|
3223408983U, // FMAXNM_ZPmZ_S
|
|
545362263U, // FMAXNMv2f32
|
|
547459415U, // FMAXNMv2f64
|
|
549556567U, // FMAXNMv4f16
|
|
551653719U, // FMAXNMv4f32
|
|
553750871U, // FMAXNMv8f16
|
|
3223376715U, // FMAXP_ZPmZZ_D
|
|
3519091531U, // FMAXP_ZPmZZ_H
|
|
3223409483U, // FMAXP_ZPmZZ_S
|
|
545362763U, // FMAXPv2f32
|
|
547459915U, // FMAXPv2f64
|
|
538989387U, // FMAXPv2i16p
|
|
538989387U, // FMAXPv2i32p
|
|
538989387U, // FMAXPv2i64p
|
|
549557067U, // FMAXPv4f16
|
|
551654219U, // FMAXPv4f32
|
|
553751371U, // FMAXPv8f16
|
|
807426747U, // FMAXSrr
|
|
1646434647U, // FMAXV_VPZ_D
|
|
1648548183U, // FMAXV_VPZ_H
|
|
1638078807U, // FMAXV_VPZ_S
|
|
538990935U, // FMAXVv4i16v
|
|
538990935U, // FMAXVv4i32v
|
|
538990935U, // FMAXVv8i16v
|
|
3223378619U, // FMAX_ZPmI_D
|
|
3519093435U, // FMAX_ZPmI_H
|
|
3223411387U, // FMAX_ZPmI_S
|
|
3223378619U, // FMAX_ZPmZ_D
|
|
3519093435U, // FMAX_ZPmZ_H
|
|
3223411387U, // FMAX_ZPmZ_S
|
|
545364667U, // FMAXv2f32
|
|
547461819U, // FMAXv2f64
|
|
549558971U, // FMAXv4f16
|
|
551656123U, // FMAXv4f32
|
|
553753275U, // FMAXv8f16
|
|
807424402U, // FMINDrr
|
|
807424402U, // FMINHrr
|
|
807424335U, // FMINNMDrr
|
|
807424335U, // FMINNMHrr
|
|
3223376609U, // FMINNMP_ZPmZZ_D
|
|
3519091425U, // FMINNMP_ZPmZZ_H
|
|
3223409377U, // FMINNMP_ZPmZZ_S
|
|
545362657U, // FMINNMPv2f32
|
|
547459809U, // FMINNMPv2f64
|
|
538989281U, // FMINNMPv2i16p
|
|
538989281U, // FMINNMPv2i32p
|
|
538989281U, // FMINNMPv2i64p
|
|
549556961U, // FMINNMPv4f16
|
|
551654113U, // FMINNMPv4f32
|
|
553751265U, // FMINNMPv8f16
|
|
807424335U, // FMINNMSrr
|
|
1646434577U, // FMINNMV_VPZ_D
|
|
1648548113U, // FMINNMV_VPZ_H
|
|
1638078737U, // FMINNMV_VPZ_S
|
|
538990865U, // FMINNMVv4i16v
|
|
538990865U, // FMINNMVv4i32v
|
|
538990865U, // FMINNMVv8i16v
|
|
3223376207U, // FMINNM_ZPmI_D
|
|
3519091023U, // FMINNM_ZPmI_H
|
|
3223408975U, // FMINNM_ZPmI_S
|
|
3223376207U, // FMINNM_ZPmZ_D
|
|
3519091023U, // FMINNM_ZPmZ_H
|
|
3223408975U, // FMINNM_ZPmZ_S
|
|
545362255U, // FMINNMv2f32
|
|
547459407U, // FMINNMv2f64
|
|
549556559U, // FMINNMv4f16
|
|
551653711U, // FMINNMv4f32
|
|
553750863U, // FMINNMv8f16
|
|
3223376633U, // FMINP_ZPmZZ_D
|
|
3519091449U, // FMINP_ZPmZZ_H
|
|
3223409401U, // FMINP_ZPmZZ_S
|
|
545362681U, // FMINPv2f32
|
|
547459833U, // FMINPv2f64
|
|
538989305U, // FMINPv2i16p
|
|
538989305U, // FMINPv2i32p
|
|
538989305U, // FMINPv2i64p
|
|
549556985U, // FMINPv4f16
|
|
551654137U, // FMINPv4f32
|
|
553751289U, // FMINPv8f16
|
|
807424402U, // FMINSrr
|
|
1646434595U, // FMINV_VPZ_D
|
|
1648548131U, // FMINV_VPZ_H
|
|
1638078755U, // FMINV_VPZ_S
|
|
538990883U, // FMINVv4i16v
|
|
538990883U, // FMINVv4i32v
|
|
538990883U, // FMINVv8i16v
|
|
3223376274U, // FMIN_ZPmI_D
|
|
3519091090U, // FMIN_ZPmI_H
|
|
3223409042U, // FMIN_ZPmI_S
|
|
3223376274U, // FMIN_ZPmZ_D
|
|
3519091090U, // FMIN_ZPmZ_H
|
|
3223409042U, // FMIN_ZPmZ_S
|
|
545362322U, // FMINv2f32
|
|
547459474U, // FMINv2f64
|
|
549556626U, // FMINv4f16
|
|
551653778U, // FMINv4f32
|
|
553750930U, // FMINv8f16
|
|
2961309886U, // FMLAL2lanev4f16
|
|
2967601342U, // FMLAL2lanev8f16
|
|
2961309886U, // FMLAL2v4f16
|
|
2967601342U, // FMLAL2v8f16
|
|
2686534964U, // FMLALB_ZZZI_SHH
|
|
2686534964U, // FMLALB_ZZZ_SHH
|
|
2686539457U, // FMLALT_ZZZI_SHH
|
|
2686539457U, // FMLALT_ZZZ_SHH
|
|
2961313581U, // FMLALlanev4f16
|
|
2967605037U, // FMLALlanev8f16
|
|
2961313581U, // FMLALv4f16
|
|
2967605037U, // FMLALv8f16
|
|
3223372505U, // FMLA_ZPmZZ_D
|
|
3519087321U, // FMLA_ZPmZZ_H
|
|
3223405273U, // FMLA_ZPmZZ_S
|
|
1075888857U, // FMLA_ZZZI_D
|
|
2185298649U, // FMLA_ZZZI_H
|
|
1344357081U, // FMLA_ZZZI_S
|
|
270746329U, // FMLAv1i16_indexed
|
|
270746329U, // FMLAv1i32_indexed
|
|
270746329U, // FMLAv1i64_indexed
|
|
2961310425U, // FMLAv2f32
|
|
2963407577U, // FMLAv2f64
|
|
2961310425U, // FMLAv2i32_indexed
|
|
2963407577U, // FMLAv2i64_indexed
|
|
2965504729U, // FMLAv4f16
|
|
2967601881U, // FMLAv4f32
|
|
2965504729U, // FMLAv4i16_indexed
|
|
2967601881U, // FMLAv4i32_indexed
|
|
2969699033U, // FMLAv8f16
|
|
2969699033U, // FMLAv8i16_indexed
|
|
2961310018U, // FMLSL2lanev4f16
|
|
2967601474U, // FMLSL2lanev8f16
|
|
2961310018U, // FMLSL2v4f16
|
|
2967601474U, // FMLSL2v8f16
|
|
2686535261U, // FMLSLB_ZZZI_SHH
|
|
2686535261U, // FMLSLB_ZZZ_SHH
|
|
2686539631U, // FMLSLT_ZZZI_SHH
|
|
2686539631U, // FMLSLT_ZZZ_SHH
|
|
2961313983U, // FMLSLlanev4f16
|
|
2967605439U, // FMLSLlanev8f16
|
|
2961313983U, // FMLSLv4f16
|
|
2967605439U, // FMLSLv8f16
|
|
3223377295U, // FMLS_ZPmZZ_D
|
|
3519092111U, // FMLS_ZPmZZ_H
|
|
3223410063U, // FMLS_ZPmZZ_S
|
|
1075893647U, // FMLS_ZZZI_D
|
|
2185303439U, // FMLS_ZZZI_H
|
|
1344361871U, // FMLS_ZZZI_S
|
|
270751119U, // FMLSv1i16_indexed
|
|
270751119U, // FMLSv1i32_indexed
|
|
270751119U, // FMLSv1i64_indexed
|
|
2961315215U, // FMLSv2f32
|
|
2963412367U, // FMLSv2f64
|
|
2961315215U, // FMLSv2i32_indexed
|
|
2963412367U, // FMLSv2i64_indexed
|
|
2965509519U, // FMLSv4f16
|
|
2967606671U, // FMLSv4f32
|
|
2965509519U, // FMLSv4i16_indexed
|
|
2967606671U, // FMLSv4i32_indexed
|
|
2969703823U, // FMLSv8f16
|
|
2969703823U, // FMLSv8i16_indexed
|
|
1075888864U, // FMMLA_ZZZ_D
|
|
1344357088U, // FMMLA_ZZZ_S
|
|
2168570647U, // FMOPA_MPPZZ_D
|
|
2170667799U, // FMOPA_MPPZZ_S
|
|
2168575445U, // FMOPS_MPPZZ_D
|
|
2170672597U, // FMOPS_MPPZZ_S
|
|
538990911U, // FMOVDXHighr
|
|
807426367U, // FMOVDXr
|
|
807426367U, // FMOVDi
|
|
807426367U, // FMOVDr
|
|
807426367U, // FMOVHWr
|
|
807426367U, // FMOVHXr
|
|
807426367U, // FMOVHi
|
|
807426367U, // FMOVHr
|
|
807426367U, // FMOVSWr
|
|
807426367U, // FMOVSi
|
|
807426367U, // FMOVSr
|
|
807426367U, // FMOVWHr
|
|
807426367U, // FMOVWSr
|
|
864131391U, // FMOVXDHighr
|
|
807426367U, // FMOVXDr
|
|
807426367U, // FMOVXHr
|
|
813799743U, // FMOVv2f32_ns
|
|
815896895U, // FMOVv2f64_ns
|
|
817994047U, // FMOVv4f16_ns
|
|
820091199U, // FMOVv4f32_ns
|
|
822188351U, // FMOVv8f16_ns
|
|
3223373810U, // FMSB_ZPmZZ_D
|
|
3519088626U, // FMSB_ZPmZZ_H
|
|
3223406578U, // FMSB_ZPmZZ_S
|
|
807422067U, // FMSUBDrrr
|
|
807422067U, // FMSUBHrrr
|
|
807422067U, // FMSUBSrrr
|
|
807424233U, // FMULDrr
|
|
807424233U, // FMULHrr
|
|
807424233U, // FMULSrr
|
|
807426806U, // FMULX16
|
|
807426806U, // FMULX32
|
|
807426806U, // FMULX64
|
|
3223378678U, // FMULX_ZPmZ_D
|
|
3519093494U, // FMULX_ZPmZ_H
|
|
3223411446U, // FMULX_ZPmZ_S
|
|
807426806U, // FMULXv1i16_indexed
|
|
807426806U, // FMULXv1i32_indexed
|
|
807426806U, // FMULXv1i64_indexed
|
|
545364726U, // FMULXv2f32
|
|
547461878U, // FMULXv2f64
|
|
545364726U, // FMULXv2i32_indexed
|
|
547461878U, // FMULXv2i64_indexed
|
|
549559030U, // FMULXv4f16
|
|
551656182U, // FMULXv4f32
|
|
549559030U, // FMULXv4i16_indexed
|
|
551656182U, // FMULXv4i32_indexed
|
|
553753334U, // FMULXv8f16
|
|
553753334U, // FMULXv8i16_indexed
|
|
3223376105U, // FMUL_ZPmI_D
|
|
3519090921U, // FMUL_ZPmI_H
|
|
3223408873U, // FMUL_ZPmI_S
|
|
3223376105U, // FMUL_ZPmZ_D
|
|
3519090921U, // FMUL_ZPmZ_H
|
|
3223408873U, // FMUL_ZPmZ_S
|
|
2418069737U, // FMUL_ZZZI_D
|
|
2179010793U, // FMUL_ZZZI_H
|
|
4028715241U, // FMUL_ZZZI_S
|
|
2418069737U, // FMUL_ZZZ_D
|
|
2179010793U, // FMUL_ZZZ_H
|
|
4028715241U, // FMUL_ZZZ_S
|
|
807424233U, // FMULv1i16_indexed
|
|
807424233U, // FMULv1i32_indexed
|
|
807424233U, // FMULv1i64_indexed
|
|
545362153U, // FMULv2f32
|
|
547459305U, // FMULv2f64
|
|
545362153U, // FMULv2i32_indexed
|
|
547459305U, // FMULv2i64_indexed
|
|
549556457U, // FMULv4f16
|
|
551653609U, // FMULv4f32
|
|
549556457U, // FMULv4i16_indexed
|
|
551653609U, // FMULv4i32_indexed
|
|
553750761U, // FMULv8f16
|
|
553750761U, // FMULv8i16_indexed
|
|
807422771U, // FNEGDr
|
|
807422771U, // FNEGHr
|
|
807422771U, // FNEGSr
|
|
2149171U, // FNEG_ZPmZ_D
|
|
272698163U, // FNEG_ZPmZ_H
|
|
2181939U, // FNEG_ZPmZ_S
|
|
545360691U, // FNEGv2f32
|
|
547457843U, // FNEGv2f64
|
|
549554995U, // FNEGv4f16
|
|
551652147U, // FNEGv4f32
|
|
553749299U, // FNEGv8f16
|
|
807422460U, // FNMADDDrrr
|
|
807422460U, // FNMADDHrrr
|
|
807422460U, // FNMADDSrrr
|
|
3223374196U, // FNMAD_ZPmZZ_D
|
|
3519089012U, // FNMAD_ZPmZZ_H
|
|
3223406964U, // FNMAD_ZPmZZ_S
|
|
3223372534U, // FNMLA_ZPmZZ_D
|
|
3519087350U, // FNMLA_ZPmZZ_H
|
|
3223405302U, // FNMLA_ZPmZZ_S
|
|
3223377301U, // FNMLS_ZPmZZ_D
|
|
3519092117U, // FNMLS_ZPmZZ_H
|
|
3223410069U, // FNMLS_ZPmZZ_S
|
|
3223373816U, // FNMSB_ZPmZZ_D
|
|
3519088632U, // FNMSB_ZPmZZ_H
|
|
3223406584U, // FNMSB_ZPmZZ_S
|
|
807422074U, // FNMSUBDrrr
|
|
807422074U, // FNMSUBHrrr
|
|
807422074U, // FNMSUBSrrr
|
|
807424239U, // FNMULDrr
|
|
807424239U, // FNMULHrr
|
|
807424239U, // FNMULSrr
|
|
2418068145U, // FRECPE_ZZ_D
|
|
1642138289U, // FRECPE_ZZ_H
|
|
4028713649U, // FRECPE_ZZ_S
|
|
807422641U, // FRECPEv1f16
|
|
807422641U, // FRECPEv1i32
|
|
807422641U, // FRECPEv1i64
|
|
545360561U, // FRECPEv2f32
|
|
547457713U, // FRECPEv2f64
|
|
549554865U, // FRECPEv4f16
|
|
551652017U, // FRECPEv4f32
|
|
553749169U, // FRECPEv8f16
|
|
807425484U, // FRECPS16
|
|
807425484U, // FRECPS32
|
|
807425484U, // FRECPS64
|
|
2418070988U, // FRECPS_ZZZ_D
|
|
2179012044U, // FRECPS_ZZZ_H
|
|
4028716492U, // FRECPS_ZZZ_S
|
|
545363404U, // FRECPSv2f32
|
|
547460556U, // FRECPSv2f64
|
|
549557708U, // FRECPSv4f16
|
|
551654860U, // FRECPSv4f32
|
|
553752012U, // FRECPSv8f16
|
|
2153213U, // FRECPX_ZPmZ_D
|
|
272702205U, // FRECPX_ZPmZ_H
|
|
2185981U, // FRECPX_ZPmZ_S
|
|
807426813U, // FRECPXv1f16
|
|
807426813U, // FRECPXv1i32
|
|
807426813U, // FRECPXv1i64
|
|
807426721U, // FRINT32XDr
|
|
807426721U, // FRINT32XSr
|
|
545364641U, // FRINT32Xv2f32
|
|
547461793U, // FRINT32Xv2f64
|
|
551656097U, // FRINT32Xv4f32
|
|
807426851U, // FRINT32ZDr
|
|
807426851U, // FRINT32ZSr
|
|
545364771U, // FRINT32Zv2f32
|
|
547461923U, // FRINT32Zv2f64
|
|
551656227U, // FRINT32Zv4f32
|
|
807426731U, // FRINT64XDr
|
|
807426731U, // FRINT64XSr
|
|
545364651U, // FRINT64Xv2f32
|
|
547461803U, // FRINT64Xv2f64
|
|
551656107U, // FRINT64Xv4f32
|
|
807426861U, // FRINT64ZDr
|
|
807426861U, // FRINT64ZSr
|
|
545364781U, // FRINT64Zv2f32
|
|
547461933U, // FRINT64Zv2f64
|
|
551656237U, // FRINT64Zv4f32
|
|
807420794U, // FRINTADr
|
|
807420794U, // FRINTAHr
|
|
807420794U, // FRINTASr
|
|
2147194U, // FRINTA_ZPmZ_D
|
|
272696186U, // FRINTA_ZPmZ_H
|
|
2179962U, // FRINTA_ZPmZ_S
|
|
545358714U, // FRINTAv2f32
|
|
547455866U, // FRINTAv2f64
|
|
549553018U, // FRINTAv4f16
|
|
551650170U, // FRINTAv4f32
|
|
553747322U, // FRINTAv8f16
|
|
807423732U, // FRINTIDr
|
|
807423732U, // FRINTIHr
|
|
807423732U, // FRINTISr
|
|
2150132U, // FRINTI_ZPmZ_D
|
|
272699124U, // FRINTI_ZPmZ_H
|
|
2182900U, // FRINTI_ZPmZ_S
|
|
545361652U, // FRINTIv2f32
|
|
547458804U, // FRINTIv2f64
|
|
549555956U, // FRINTIv4f16
|
|
551653108U, // FRINTIv4f32
|
|
553750260U, // FRINTIv8f16
|
|
807424357U, // FRINTMDr
|
|
807424357U, // FRINTMHr
|
|
807424357U, // FRINTMSr
|
|
2150757U, // FRINTM_ZPmZ_D
|
|
272699749U, // FRINTM_ZPmZ_H
|
|
2183525U, // FRINTM_ZPmZ_S
|
|
545362277U, // FRINTMv2f32
|
|
547459429U, // FRINTMv2f64
|
|
549556581U, // FRINTMv4f16
|
|
551653733U, // FRINTMv4f32
|
|
553750885U, // FRINTMv8f16
|
|
807424480U, // FRINTNDr
|
|
807424480U, // FRINTNHr
|
|
807424480U, // FRINTNSr
|
|
2150880U, // FRINTN_ZPmZ_D
|
|
272699872U, // FRINTN_ZPmZ_H
|
|
2183648U, // FRINTN_ZPmZ_S
|
|
545362400U, // FRINTNv2f32
|
|
547459552U, // FRINTNv2f64
|
|
549556704U, // FRINTNv4f16
|
|
551653856U, // FRINTNv4f32
|
|
553751008U, // FRINTNv8f16
|
|
807424812U, // FRINTPDr
|
|
807424812U, // FRINTPHr
|
|
807424812U, // FRINTPSr
|
|
2151212U, // FRINTP_ZPmZ_D
|
|
272700204U, // FRINTP_ZPmZ_H
|
|
2183980U, // FRINTP_ZPmZ_S
|
|
545362732U, // FRINTPv2f32
|
|
547459884U, // FRINTPv2f64
|
|
549557036U, // FRINTPv4f16
|
|
551654188U, // FRINTPv4f32
|
|
553751340U, // FRINTPv8f16
|
|
807426821U, // FRINTXDr
|
|
807426821U, // FRINTXHr
|
|
807426821U, // FRINTXSr
|
|
2153221U, // FRINTX_ZPmZ_D
|
|
272702213U, // FRINTX_ZPmZ_H
|
|
2185989U, // FRINTX_ZPmZ_S
|
|
545364741U, // FRINTXv2f32
|
|
547461893U, // FRINTXv2f64
|
|
549559045U, // FRINTXv4f16
|
|
551656197U, // FRINTXv4f32
|
|
553753349U, // FRINTXv8f16
|
|
807426928U, // FRINTZDr
|
|
807426928U, // FRINTZHr
|
|
807426928U, // FRINTZSr
|
|
2153328U, // FRINTZ_ZPmZ_D
|
|
272702320U, // FRINTZ_ZPmZ_H
|
|
2186096U, // FRINTZ_ZPmZ_S
|
|
545364848U, // FRINTZv2f32
|
|
547462000U, // FRINTZv2f64
|
|
549559152U, // FRINTZv4f16
|
|
551656304U, // FRINTZv4f32
|
|
553753456U, // FRINTZv8f16
|
|
2418068190U, // FRSQRTE_ZZ_D
|
|
1642138334U, // FRSQRTE_ZZ_H
|
|
4028713694U, // FRSQRTE_ZZ_S
|
|
807422686U, // FRSQRTEv1f16
|
|
807422686U, // FRSQRTEv1i32
|
|
807422686U, // FRSQRTEv1i64
|
|
545360606U, // FRSQRTEv2f32
|
|
547457758U, // FRSQRTEv2f64
|
|
549554910U, // FRSQRTEv4f16
|
|
551652062U, // FRSQRTEv4f32
|
|
553749214U, // FRSQRTEv8f16
|
|
807425555U, // FRSQRTS16
|
|
807425555U, // FRSQRTS32
|
|
807425555U, // FRSQRTS64
|
|
2418071059U, // FRSQRTS_ZZZ_D
|
|
2179012115U, // FRSQRTS_ZZZ_H
|
|
4028716563U, // FRSQRTS_ZZZ_S
|
|
545363475U, // FRSQRTSv2f32
|
|
547460627U, // FRSQRTSv2f64
|
|
549557779U, // FRSQRTSv4f16
|
|
551654931U, // FRSQRTSv4f32
|
|
553752083U, // FRSQRTSv8f16
|
|
3223374459U, // FSCALE_ZPmZ_D
|
|
3519089275U, // FSCALE_ZPmZ_H
|
|
3223407227U, // FSCALE_ZPmZ_S
|
|
807426111U, // FSQRTDr
|
|
807426111U, // FSQRTHr
|
|
807426111U, // FSQRTSr
|
|
2152511U, // FSQRT_ZPmZ_D
|
|
272701503U, // FSQRT_ZPmZ_H
|
|
2185279U, // FSQRT_ZPmZ_S
|
|
545364031U, // FSQRTv2f32
|
|
547461183U, // FSQRTv2f64
|
|
549558335U, // FSQRTv4f16
|
|
551655487U, // FSQRTv4f32
|
|
553752639U, // FSQRTv8f16
|
|
807422047U, // FSUBDrr
|
|
807422047U, // FSUBHrr
|
|
3223376820U, // FSUBR_ZPmI_D
|
|
3519091636U, // FSUBR_ZPmI_H
|
|
3223409588U, // FSUBR_ZPmI_S
|
|
3223376820U, // FSUBR_ZPmZ_D
|
|
3519091636U, // FSUBR_ZPmZ_H
|
|
3223409588U, // FSUBR_ZPmZ_S
|
|
807422047U, // FSUBSrr
|
|
3223373919U, // FSUB_ZPmI_D
|
|
3519088735U, // FSUB_ZPmI_H
|
|
3223406687U, // FSUB_ZPmI_S
|
|
3223373919U, // FSUB_ZPmZ_D
|
|
3519088735U, // FSUB_ZPmZ_H
|
|
3223406687U, // FSUB_ZPmZ_S
|
|
2418067551U, // FSUB_ZZZ_D
|
|
2179008607U, // FSUB_ZZZ_H
|
|
4028713055U, // FSUB_ZZZ_S
|
|
545359967U, // FSUBv2f32
|
|
547457119U, // FSUBv2f64
|
|
549554271U, // FSUBv4f16
|
|
551651423U, // FSUBv4f32
|
|
553748575U, // FSUBv8f16
|
|
2418067835U, // FTMAD_ZZI_D
|
|
2179008891U, // FTMAD_ZZI_H
|
|
4028713339U, // FTMAD_ZZI_S
|
|
2418069756U, // FTSMUL_ZZZ_D
|
|
2179010812U, // FTSMUL_ZZZ_H
|
|
4028715260U, // FTSMUL_ZZZ_S
|
|
2418069512U, // FTSSEL_ZZZ_D
|
|
2179010568U, // FTSSEL_ZZZ_H
|
|
4028715016U, // FTSSEL_ZZZ_S
|
|
1134937033U, // GLD1B_D_IMM_REAL
|
|
329630665U, // GLD1B_D_REAL
|
|
329630665U, // GLD1B_D_SXTW_REAL
|
|
329630665U, // GLD1B_D_UXTW_REAL
|
|
1403388873U, // GLD1B_S_IMM_REAL
|
|
329647049U, // GLD1B_S_SXTW_REAL
|
|
329647049U, // GLD1B_S_UXTW_REAL
|
|
1134938398U, // GLD1D_IMM_REAL
|
|
329632030U, // GLD1D_REAL
|
|
329632030U, // GLD1D_SCALED_REAL
|
|
329632030U, // GLD1D_SXTW_REAL
|
|
329632030U, // GLD1D_SXTW_SCALED_REAL
|
|
329632030U, // GLD1D_UXTW_REAL
|
|
329632030U, // GLD1D_UXTW_SCALED_REAL
|
|
1134938983U, // GLD1H_D_IMM_REAL
|
|
329632615U, // GLD1H_D_REAL
|
|
329632615U, // GLD1H_D_SCALED_REAL
|
|
329632615U, // GLD1H_D_SXTW_REAL
|
|
329632615U, // GLD1H_D_SXTW_SCALED_REAL
|
|
329632615U, // GLD1H_D_UXTW_REAL
|
|
329632615U, // GLD1H_D_UXTW_SCALED_REAL
|
|
1403390823U, // GLD1H_S_IMM_REAL
|
|
329648999U, // GLD1H_S_SXTW_REAL
|
|
329648999U, // GLD1H_S_SXTW_SCALED_REAL
|
|
329648999U, // GLD1H_S_UXTW_REAL
|
|
329648999U, // GLD1H_S_UXTW_SCALED_REAL
|
|
1134938048U, // GLD1SB_D_IMM_REAL
|
|
329631680U, // GLD1SB_D_REAL
|
|
329631680U, // GLD1SB_D_SXTW_REAL
|
|
329631680U, // GLD1SB_D_UXTW_REAL
|
|
1403389888U, // GLD1SB_S_IMM_REAL
|
|
329648064U, // GLD1SB_S_SXTW_REAL
|
|
329648064U, // GLD1SB_S_UXTW_REAL
|
|
1134939674U, // GLD1SH_D_IMM_REAL
|
|
329633306U, // GLD1SH_D_REAL
|
|
329633306U, // GLD1SH_D_SCALED_REAL
|
|
329633306U, // GLD1SH_D_SXTW_REAL
|
|
329633306U, // GLD1SH_D_SXTW_SCALED_REAL
|
|
329633306U, // GLD1SH_D_UXTW_REAL
|
|
329633306U, // GLD1SH_D_UXTW_SCALED_REAL
|
|
1403391514U, // GLD1SH_S_IMM_REAL
|
|
329649690U, // GLD1SH_S_SXTW_REAL
|
|
329649690U, // GLD1SH_S_SXTW_SCALED_REAL
|
|
329649690U, // GLD1SH_S_UXTW_REAL
|
|
329649690U, // GLD1SH_S_UXTW_SCALED_REAL
|
|
1134942767U, // GLD1SW_D_IMM_REAL
|
|
329636399U, // GLD1SW_D_REAL
|
|
329636399U, // GLD1SW_D_SCALED_REAL
|
|
329636399U, // GLD1SW_D_SXTW_REAL
|
|
329636399U, // GLD1SW_D_SXTW_SCALED_REAL
|
|
329636399U, // GLD1SW_D_UXTW_REAL
|
|
329636399U, // GLD1SW_D_UXTW_SCALED_REAL
|
|
1134942572U, // GLD1W_D_IMM_REAL
|
|
329636204U, // GLD1W_D_REAL
|
|
329636204U, // GLD1W_D_SCALED_REAL
|
|
329636204U, // GLD1W_D_SXTW_REAL
|
|
329636204U, // GLD1W_D_SXTW_SCALED_REAL
|
|
329636204U, // GLD1W_D_UXTW_REAL
|
|
329636204U, // GLD1W_D_UXTW_SCALED_REAL
|
|
1403394412U, // GLD1W_IMM_REAL
|
|
329652588U, // GLD1W_SXTW_REAL
|
|
329652588U, // GLD1W_SXTW_SCALED_REAL
|
|
329652588U, // GLD1W_UXTW_REAL
|
|
329652588U, // GLD1W_UXTW_SCALED_REAL
|
|
1134937039U, // GLDFF1B_D_IMM_REAL
|
|
329630671U, // GLDFF1B_D_REAL
|
|
329630671U, // GLDFF1B_D_SXTW_REAL
|
|
329630671U, // GLDFF1B_D_UXTW_REAL
|
|
1403388879U, // GLDFF1B_S_IMM_REAL
|
|
329647055U, // GLDFF1B_S_SXTW_REAL
|
|
329647055U, // GLDFF1B_S_UXTW_REAL
|
|
1134938404U, // GLDFF1D_IMM_REAL
|
|
329632036U, // GLDFF1D_REAL
|
|
329632036U, // GLDFF1D_SCALED_REAL
|
|
329632036U, // GLDFF1D_SXTW_REAL
|
|
329632036U, // GLDFF1D_SXTW_SCALED_REAL
|
|
329632036U, // GLDFF1D_UXTW_REAL
|
|
329632036U, // GLDFF1D_UXTW_SCALED_REAL
|
|
1134938989U, // GLDFF1H_D_IMM_REAL
|
|
329632621U, // GLDFF1H_D_REAL
|
|
329632621U, // GLDFF1H_D_SCALED_REAL
|
|
329632621U, // GLDFF1H_D_SXTW_REAL
|
|
329632621U, // GLDFF1H_D_SXTW_SCALED_REAL
|
|
329632621U, // GLDFF1H_D_UXTW_REAL
|
|
329632621U, // GLDFF1H_D_UXTW_SCALED_REAL
|
|
1403390829U, // GLDFF1H_S_IMM_REAL
|
|
329649005U, // GLDFF1H_S_SXTW_REAL
|
|
329649005U, // GLDFF1H_S_SXTW_SCALED_REAL
|
|
329649005U, // GLDFF1H_S_UXTW_REAL
|
|
329649005U, // GLDFF1H_S_UXTW_SCALED_REAL
|
|
1134938055U, // GLDFF1SB_D_IMM_REAL
|
|
329631687U, // GLDFF1SB_D_REAL
|
|
329631687U, // GLDFF1SB_D_SXTW_REAL
|
|
329631687U, // GLDFF1SB_D_UXTW_REAL
|
|
1403389895U, // GLDFF1SB_S_IMM_REAL
|
|
329648071U, // GLDFF1SB_S_SXTW_REAL
|
|
329648071U, // GLDFF1SB_S_UXTW_REAL
|
|
1134939681U, // GLDFF1SH_D_IMM_REAL
|
|
329633313U, // GLDFF1SH_D_REAL
|
|
329633313U, // GLDFF1SH_D_SCALED_REAL
|
|
329633313U, // GLDFF1SH_D_SXTW_REAL
|
|
329633313U, // GLDFF1SH_D_SXTW_SCALED_REAL
|
|
329633313U, // GLDFF1SH_D_UXTW_REAL
|
|
329633313U, // GLDFF1SH_D_UXTW_SCALED_REAL
|
|
1403391521U, // GLDFF1SH_S_IMM_REAL
|
|
329649697U, // GLDFF1SH_S_SXTW_REAL
|
|
329649697U, // GLDFF1SH_S_SXTW_SCALED_REAL
|
|
329649697U, // GLDFF1SH_S_UXTW_REAL
|
|
329649697U, // GLDFF1SH_S_UXTW_SCALED_REAL
|
|
1134942774U, // GLDFF1SW_D_IMM_REAL
|
|
329636406U, // GLDFF1SW_D_REAL
|
|
329636406U, // GLDFF1SW_D_SCALED_REAL
|
|
329636406U, // GLDFF1SW_D_SXTW_REAL
|
|
329636406U, // GLDFF1SW_D_SXTW_SCALED_REAL
|
|
329636406U, // GLDFF1SW_D_UXTW_REAL
|
|
329636406U, // GLDFF1SW_D_UXTW_SCALED_REAL
|
|
1134942578U, // GLDFF1W_D_IMM_REAL
|
|
329636210U, // GLDFF1W_D_REAL
|
|
329636210U, // GLDFF1W_D_SCALED_REAL
|
|
329636210U, // GLDFF1W_D_SXTW_REAL
|
|
329636210U, // GLDFF1W_D_SXTW_SCALED_REAL
|
|
329636210U, // GLDFF1W_D_UXTW_REAL
|
|
329636210U, // GLDFF1W_D_UXTW_SCALED_REAL
|
|
1403394418U, // GLDFF1W_IMM_REAL
|
|
329652594U, // GLDFF1W_SXTW_REAL
|
|
329652594U, // GLDFF1W_SXTW_SCALED_REAL
|
|
329652594U, // GLDFF1W_UXTW_REAL
|
|
329652594U, // GLDFF1W_UXTW_SCALED_REAL
|
|
807423716U, // GMI
|
|
415658U, // HINT
|
|
3223377807U, // HISTCNT_ZPzZZ_D
|
|
3223410575U, // HISTCNT_ZPzZZ_S
|
|
3760229191U, // HISTSEG_ZZZ
|
|
268064U, // HLT
|
|
264468U, // HVC
|
|
2686469322U, // INCB_XPiI
|
|
2686470573U, // INCD_XPiI
|
|
2686503341U, // INCD_ZPiI
|
|
2686471259U, // INCH_XPiI
|
|
39914587U, // INCH_ZPiI
|
|
3760214654U, // INCP_XP_B
|
|
2418037374U, // INCP_XP_D
|
|
1881166462U, // INCP_XP_H
|
|
4028650110U, // INCP_XP_S
|
|
1075892862U, // INCP_ZP_D
|
|
1648431742U, // INCP_ZP_H
|
|
1344361086U, // INCP_ZP_S
|
|
2686474733U, // INCW_XPiI
|
|
2686540269U, // INCW_ZPiI
|
|
1075878623U, // INDEX_II_B
|
|
807459551U, // INDEX_II_D
|
|
1405164255U, // INDEX_II_H
|
|
807492319U, // INDEX_II_S
|
|
1075878623U, // INDEX_IR_B
|
|
807459551U, // INDEX_IR_D
|
|
331422431U, // INDEX_IR_H
|
|
807492319U, // INDEX_IR_S
|
|
807443167U, // INDEX_RI_B
|
|
807459551U, // INDEX_RI_D
|
|
2191596255U, // INDEX_RI_H
|
|
807492319U, // INDEX_RI_S
|
|
807443167U, // INDEX_RR_B
|
|
807459551U, // INDEX_RR_D
|
|
2191596255U, // INDEX_RR_H
|
|
807492319U, // INDEX_RR_S
|
|
1676051345U, // INSERT_MXIPZ_H_B
|
|
1676051345U, // INSERT_MXIPZ_H_D
|
|
1676051345U, // INSERT_MXIPZ_H_H
|
|
1676051345U, // INSERT_MXIPZ_H_Q
|
|
1676051345U, // INSERT_MXIPZ_H_S
|
|
1676067729U, // INSERT_MXIPZ_V_B
|
|
1676067729U, // INSERT_MXIPZ_V_D
|
|
1676067729U, // INSERT_MXIPZ_V_H
|
|
1676067729U, // INSERT_MXIPZ_V_Q
|
|
1676067729U, // INSERT_MXIPZ_V_S
|
|
270570646U, // INSR_ZR_B
|
|
270587030U, // INSR_ZR_D
|
|
1677792406U, // INSR_ZR_H
|
|
270619798U, // INSR_ZR_S
|
|
1881183382U, // INSR_ZV_B
|
|
2149635222U, // INSR_ZV_D
|
|
1661015190U, // INSR_ZV_H
|
|
2418103446U, // INSR_ZV_S
|
|
2485261739U, // INSvi16gpr
|
|
2753697195U, // INSvi16lane
|
|
2487358891U, // INSvi32gpr
|
|
2755794347U, // INSvi32lane
|
|
2474775979U, // INSvi64gpr
|
|
2743211435U, // INSvi64lane
|
|
2489456043U, // INSvi8gpr
|
|
2757891499U, // INSvi8lane
|
|
807422800U, // IRG
|
|
329709U, // ISB
|
|
3223339907U, // LASTA_RPZ_B
|
|
3223339907U, // LASTA_RPZ_D
|
|
3223339907U, // LASTA_RPZ_H
|
|
3223339907U, // LASTA_RPZ_S
|
|
3223339907U, // LASTA_VPZ_B
|
|
3223339907U, // LASTA_VPZ_D
|
|
3223339907U, // LASTA_VPZ_H
|
|
3223339907U, // LASTA_VPZ_S
|
|
3223341132U, // LASTB_RPZ_B
|
|
3223341132U, // LASTB_RPZ_D
|
|
3223341132U, // LASTB_RPZ_H
|
|
3223341132U, // LASTB_RPZ_S
|
|
3223341132U, // LASTB_VPZ_B
|
|
3223341132U, // LASTB_VPZ_D
|
|
3223341132U, // LASTB_VPZ_H
|
|
3223341132U, // LASTB_VPZ_S
|
|
329712585U, // LD1B
|
|
329630665U, // LD1B_D
|
|
329630665U, // LD1B_D_IMM_REAL
|
|
329728969U, // LD1B_H
|
|
329728969U, // LD1B_H_IMM_REAL
|
|
329712585U, // LD1B_IMM_REAL
|
|
329647049U, // LD1B_S
|
|
329647049U, // LD1B_S_IMM_REAL
|
|
329632030U, // LD1D
|
|
329632030U, // LD1D_IMM_REAL
|
|
491561U, // LD1Fourv16b
|
|
76005417U, // LD1Fourv16b_POST
|
|
524329U, // LD1Fourv1d
|
|
78135337U, // LD1Fourv1d_POST
|
|
557097U, // LD1Fourv2d
|
|
76070953U, // LD1Fourv2d_POST
|
|
589865U, // LD1Fourv2s
|
|
78200873U, // LD1Fourv2s_POST
|
|
622633U, // LD1Fourv4h
|
|
78233641U, // LD1Fourv4h_POST
|
|
655401U, // LD1Fourv4s
|
|
76169257U, // LD1Fourv4s_POST
|
|
688169U, // LD1Fourv8b
|
|
78299177U, // LD1Fourv8b_POST
|
|
720937U, // LD1Fourv8h
|
|
76234793U, // LD1Fourv8h_POST
|
|
329730919U, // LD1H
|
|
329632615U, // LD1H_D
|
|
329632615U, // LD1H_D_IMM_REAL
|
|
329730919U, // LD1H_IMM_REAL
|
|
329648999U, // LD1H_S
|
|
329648999U, // LD1H_S_IMM_REAL
|
|
491561U, // LD1Onev16b
|
|
80199721U, // LD1Onev16b_POST
|
|
524329U, // LD1Onev1d
|
|
82329641U, // LD1Onev1d_POST
|
|
557097U, // LD1Onev2d
|
|
80265257U, // LD1Onev2d_POST
|
|
589865U, // LD1Onev2s
|
|
82395177U, // LD1Onev2s_POST
|
|
622633U, // LD1Onev4h
|
|
82427945U, // LD1Onev4h_POST
|
|
655401U, // LD1Onev4s
|
|
80363561U, // LD1Onev4s_POST
|
|
688169U, // LD1Onev8b
|
|
82493481U, // LD1Onev8b_POST
|
|
720937U, // LD1Onev8h
|
|
80429097U, // LD1Onev8h_POST
|
|
329631532U, // LD1RB_D_IMM
|
|
329729836U, // LD1RB_H_IMM
|
|
329713452U, // LD1RB_IMM
|
|
329647916U, // LD1RB_S_IMM
|
|
329632304U, // LD1RD_IMM
|
|
329633158U, // LD1RH_D_IMM
|
|
329731462U, // LD1RH_IMM
|
|
329649542U, // LD1RH_S_IMM
|
|
329713423U, // LD1RO_B
|
|
329713423U, // LD1RO_B_IMM
|
|
329632288U, // LD1RO_D
|
|
329632288U, // LD1RO_D_IMM
|
|
329731440U, // LD1RO_H
|
|
329731440U, // LD1RO_H_IMM
|
|
329652751U, // LD1RO_W
|
|
329652751U, // LD1RO_W_IMM
|
|
329713444U, // LD1RQ_B
|
|
329713444U, // LD1RQ_B_IMM
|
|
329632296U, // LD1RQ_D
|
|
329632296U, // LD1RQ_D_IMM
|
|
329731454U, // LD1RQ_H
|
|
329731454U, // LD1RQ_H_IMM
|
|
329652759U, // LD1RQ_W
|
|
329652759U, // LD1RQ_W_IMM
|
|
329631743U, // LD1RSB_D_IMM
|
|
329730047U, // LD1RSB_H_IMM
|
|
329648127U, // LD1RSB_S_IMM
|
|
329633356U, // LD1RSH_D_IMM
|
|
329649740U, // LD1RSH_S_IMM
|
|
329636440U, // LD1RSW_IMM
|
|
329636383U, // LD1RW_D_IMM
|
|
329652767U, // LD1RW_IMM
|
|
496522U, // LD1Rv16b
|
|
84398986U, // LD1Rv16b_POST
|
|
529290U, // LD1Rv1d
|
|
82334602U, // LD1Rv1d_POST
|
|
562058U, // LD1Rv2d
|
|
82367370U, // LD1Rv2d_POST
|
|
594826U, // LD1Rv2s
|
|
86594442U, // LD1Rv2s_POST
|
|
627594U, // LD1Rv4h
|
|
88724362U, // LD1Rv4h_POST
|
|
660362U, // LD1Rv4s
|
|
86659978U, // LD1Rv4s_POST
|
|
693130U, // LD1Rv8b
|
|
84595594U, // LD1Rv8b_POST
|
|
725898U, // LD1Rv8h
|
|
88822666U, // LD1Rv8h_POST
|
|
329631680U, // LD1SB_D
|
|
329631680U, // LD1SB_D_IMM_REAL
|
|
329729984U, // LD1SB_H
|
|
329729984U, // LD1SB_H_IMM_REAL
|
|
329648064U, // LD1SB_S
|
|
329648064U, // LD1SB_S_IMM_REAL
|
|
329633306U, // LD1SH_D
|
|
329633306U, // LD1SH_D_IMM_REAL
|
|
329649690U, // LD1SH_S
|
|
329649690U, // LD1SH_S_IMM_REAL
|
|
329636399U, // LD1SW_D
|
|
329636399U, // LD1SW_D_IMM_REAL
|
|
491561U, // LD1Threev16b
|
|
90685481U, // LD1Threev16b_POST
|
|
524329U, // LD1Threev1d
|
|
92815401U, // LD1Threev1d_POST
|
|
557097U, // LD1Threev2d
|
|
90751017U, // LD1Threev2d_POST
|
|
589865U, // LD1Threev2s
|
|
92880937U, // LD1Threev2s_POST
|
|
622633U, // LD1Threev4h
|
|
92913705U, // LD1Threev4h_POST
|
|
655401U, // LD1Threev4s
|
|
90849321U, // LD1Threev4s_POST
|
|
688169U, // LD1Threev8b
|
|
92979241U, // LD1Threev8b_POST
|
|
720937U, // LD1Threev8h
|
|
90914857U, // LD1Threev8h_POST
|
|
491561U, // LD1Twov16b
|
|
78102569U, // LD1Twov16b_POST
|
|
524329U, // LD1Twov1d
|
|
80232489U, // LD1Twov1d_POST
|
|
557097U, // LD1Twov2d
|
|
78168105U, // LD1Twov2d_POST
|
|
589865U, // LD1Twov2s
|
|
80298025U, // LD1Twov2s_POST
|
|
622633U, // LD1Twov4h
|
|
80330793U, // LD1Twov4h_POST
|
|
655401U, // LD1Twov4s
|
|
78266409U, // LD1Twov4s_POST
|
|
688169U, // LD1Twov8b
|
|
80396329U, // LD1Twov8b_POST
|
|
720937U, // LD1Twov8h
|
|
78331945U, // LD1Twov8h_POST
|
|
329652588U, // LD1W
|
|
329636204U, // LD1W_D
|
|
329636204U, // LD1W_D_IMM_REAL
|
|
329652588U, // LD1W_IMM_REAL
|
|
3047596524U, // LD1_MXIPXX_H_B
|
|
3047596538U, // LD1_MXIPXX_H_D
|
|
3047596552U, // LD1_MXIPXX_H_H
|
|
3047596566U, // LD1_MXIPXX_H_Q
|
|
3047596580U, // LD1_MXIPXX_H_S
|
|
3047612908U, // LD1_MXIPXX_V_B
|
|
3047612922U, // LD1_MXIPXX_V_D
|
|
3047612936U, // LD1_MXIPXX_V_H
|
|
3047612950U, // LD1_MXIPXX_V_Q
|
|
3047612964U, // LD1_MXIPXX_V_S
|
|
97222697U, // LD1i16
|
|
99336233U, // LD1i16_POST
|
|
97255465U, // LD1i32
|
|
101466153U, // LD1i32_POST
|
|
97288233U, // LD1i64
|
|
103596073U, // LD1i64_POST
|
|
97321001U, // LD1i8
|
|
105725993U, // LD1i8_POST
|
|
329712646U, // LD2B
|
|
329712646U, // LD2B_IMM
|
|
329632074U, // LD2D
|
|
329632074U, // LD2D_IMM
|
|
329730980U, // LD2H
|
|
329730980U, // LD2H_IMM
|
|
496528U, // LD2Rv16b
|
|
88593296U, // LD2Rv16b_POST
|
|
529296U, // LD2Rv1d
|
|
80237456U, // LD2Rv1d_POST
|
|
562064U, // LD2Rv2d
|
|
80270224U, // LD2Rv2d_POST
|
|
594832U, // LD2Rv2s
|
|
82400144U, // LD2Rv2s_POST
|
|
627600U, // LD2Rv4h
|
|
86627216U, // LD2Rv4h_POST
|
|
660368U, // LD2Rv4s
|
|
82465680U, // LD2Rv4s_POST
|
|
693136U, // LD2Rv8b
|
|
88789904U, // LD2Rv8b_POST
|
|
725904U, // LD2Rv8h
|
|
86725520U, // LD2Rv8h_POST
|
|
491659U, // LD2Twov16b
|
|
78102667U, // LD2Twov16b_POST
|
|
557195U, // LD2Twov2d
|
|
78168203U, // LD2Twov2d_POST
|
|
589963U, // LD2Twov2s
|
|
80298123U, // LD2Twov2s_POST
|
|
622731U, // LD2Twov4h
|
|
80330891U, // LD2Twov4h_POST
|
|
655499U, // LD2Twov4s
|
|
78266507U, // LD2Twov4s_POST
|
|
688267U, // LD2Twov8b
|
|
80396427U, // LD2Twov8b_POST
|
|
721035U, // LD2Twov8h
|
|
78332043U, // LD2Twov8h_POST
|
|
329652640U, // LD2W
|
|
329652640U, // LD2W_IMM
|
|
97222795U, // LD2i16
|
|
101433483U, // LD2i16_POST
|
|
97255563U, // LD2i32
|
|
103563403U, // LD2i32_POST
|
|
97288331U, // LD2i64
|
|
107790475U, // LD2i64_POST
|
|
97321099U, // LD2i8
|
|
99434635U, // LD2i8_POST
|
|
329712667U, // LD3B
|
|
329712667U, // LD3B_IMM
|
|
329632086U, // LD3D
|
|
329632086U, // LD3D_IMM
|
|
329730992U, // LD3H
|
|
329730992U, // LD3H_IMM
|
|
496534U, // LD3Rv16b
|
|
109564822U, // LD3Rv16b_POST
|
|
529302U, // LD3Rv1d
|
|
92820374U, // LD3Rv1d_POST
|
|
562070U, // LD3Rv2d
|
|
92853142U, // LD3Rv2d_POST
|
|
594838U, // LD3Rv2s
|
|
111760278U, // LD3Rv2s_POST
|
|
627606U, // LD3Rv4h
|
|
113890198U, // LD3Rv4h_POST
|
|
660374U, // LD3Rv4s
|
|
111825814U, // LD3Rv4s_POST
|
|
693142U, // LD3Rv8b
|
|
109761430U, // LD3Rv8b_POST
|
|
725910U, // LD3Rv8h
|
|
113988502U, // LD3Rv8h_POST
|
|
492067U, // LD3Threev16b
|
|
90685987U, // LD3Threev16b_POST
|
|
557603U, // LD3Threev2d
|
|
90751523U, // LD3Threev2d_POST
|
|
590371U, // LD3Threev2s
|
|
92881443U, // LD3Threev2s_POST
|
|
623139U, // LD3Threev4h
|
|
92914211U, // LD3Threev4h_POST
|
|
655907U, // LD3Threev4s
|
|
90849827U, // LD3Threev4s_POST
|
|
688675U, // LD3Threev8b
|
|
92979747U, // LD3Threev8b_POST
|
|
721443U, // LD3Threev8h
|
|
90915363U, // LD3Threev8h_POST
|
|
329652652U, // LD3W
|
|
329652652U, // LD3W_IMM
|
|
97223203U, // LD3i16
|
|
116113955U, // LD3i16_POST
|
|
97255971U, // LD3i32
|
|
118243875U, // LD3i32_POST
|
|
97288739U, // LD3i64
|
|
120373795U, // LD3i64_POST
|
|
97321507U, // LD3i8
|
|
122503715U, // LD3i8_POST
|
|
329712693U, // LD4B
|
|
329712693U, // LD4B_IMM
|
|
329632098U, // LD4D
|
|
329632098U, // LD4D_IMM
|
|
492097U, // LD4Fourv16b
|
|
76005953U, // LD4Fourv16b_POST
|
|
557633U, // LD4Fourv2d
|
|
76071489U, // LD4Fourv2d_POST
|
|
590401U, // LD4Fourv2s
|
|
78201409U, // LD4Fourv2s_POST
|
|
623169U, // LD4Fourv4h
|
|
78234177U, // LD4Fourv4h_POST
|
|
655937U, // LD4Fourv4s
|
|
76169793U, // LD4Fourv4s_POST
|
|
688705U, // LD4Fourv8b
|
|
78299713U, // LD4Fourv8b_POST
|
|
721473U, // LD4Fourv8h
|
|
76235329U, // LD4Fourv8h_POST
|
|
329731004U, // LD4H
|
|
329731004U, // LD4H_IMM
|
|
496540U, // LD4Rv16b
|
|
86496156U, // LD4Rv16b_POST
|
|
529308U, // LD4Rv1d
|
|
78140316U, // LD4Rv1d_POST
|
|
562076U, // LD4Rv2d
|
|
78173084U, // LD4Rv2d_POST
|
|
594844U, // LD4Rv2s
|
|
80303004U, // LD4Rv2s_POST
|
|
627612U, // LD4Rv4h
|
|
82432924U, // LD4Rv4h_POST
|
|
660380U, // LD4Rv4s
|
|
80368540U, // LD4Rv4s_POST
|
|
693148U, // LD4Rv8b
|
|
86692764U, // LD4Rv8b_POST
|
|
725916U, // LD4Rv8h
|
|
82531228U, // LD4Rv8h_POST
|
|
329652664U, // LD4W
|
|
329652664U, // LD4W_IMM
|
|
97223233U, // LD4i16
|
|
103531073U, // LD4i16_POST
|
|
97256001U, // LD4i32
|
|
107758145U, // LD4i32_POST
|
|
97288769U, // LD4i64
|
|
124568129U, // LD4i64_POST
|
|
97321537U, // LD4i8
|
|
101532225U, // LD4i8_POST
|
|
885799U, // LD64B
|
|
3223536705U, // LDADDAB
|
|
3223538641U, // LDADDAH
|
|
3223536927U, // LDADDALB
|
|
3223538815U, // LDADDALH
|
|
3223539483U, // LDADDALW
|
|
3223539483U, // LDADDALX
|
|
3223536282U, // LDADDAW
|
|
3223536282U, // LDADDAX
|
|
3223536863U, // LDADDB
|
|
3223538801U, // LDADDH
|
|
3223537108U, // LDADDLB
|
|
3223538915U, // LDADDLH
|
|
3223539660U, // LDADDLW
|
|
3223539660U, // LDADDLX
|
|
3223538122U, // LDADDW
|
|
3223538122U, // LDADDX
|
|
838879079U, // LDAPRB
|
|
838880705U, // LDAPRH
|
|
838882415U, // LDAPRW
|
|
838882415U, // LDAPRX
|
|
838879122U, // LDAPURBi
|
|
838880748U, // LDAPURHi
|
|
838879262U, // LDAPURSBWi
|
|
838879262U, // LDAPURSBXi
|
|
838880875U, // LDAPURSHWi
|
|
838880875U, // LDAPURSHXi
|
|
838883959U, // LDAPURSWi
|
|
838882496U, // LDAPURXi
|
|
838882496U, // LDAPURi
|
|
838879027U, // LDARB
|
|
838880653U, // LDARH
|
|
838882210U, // LDARW
|
|
838882210U, // LDARX
|
|
807424836U, // LDAXPW
|
|
807424836U, // LDAXPX
|
|
838879138U, // LDAXRB
|
|
838880764U, // LDAXRH
|
|
838882540U, // LDAXRW
|
|
838882540U, // LDAXRX
|
|
3223536761U, // LDCLRAB
|
|
3223538698U, // LDCLRAH
|
|
3223537002U, // LDCLRALB
|
|
3223538855U, // LDCLRALH
|
|
3223539557U, // LDCLRALW
|
|
3223539557U, // LDCLRALX
|
|
3223536450U, // LDCLRAW
|
|
3223536450U, // LDCLRAX
|
|
3223537480U, // LDCLRB
|
|
3223539106U, // LDCLRH
|
|
3223537210U, // LDCLRLB
|
|
3223538951U, // LDCLRLH
|
|
3223539866U, // LDCLRLW
|
|
3223539866U, // LDCLRLX
|
|
3223540754U, // LDCLRW
|
|
3223540754U, // LDCLRX
|
|
3223536770U, // LDEORAB
|
|
3223538707U, // LDEORAH
|
|
3223537012U, // LDEORALB
|
|
3223538865U, // LDEORALH
|
|
3223539566U, // LDEORALW
|
|
3223539566U, // LDEORALX
|
|
3223536458U, // LDEORAW
|
|
3223536458U, // LDEORAX
|
|
3223537503U, // LDEORB
|
|
3223539129U, // LDEORH
|
|
3223537219U, // LDEORLB
|
|
3223538960U, // LDEORLH
|
|
3223539874U, // LDEORLW
|
|
3223539874U, // LDEORLX
|
|
3223540830U, // LDEORW
|
|
3223540830U, // LDEORX
|
|
329630671U, // LDFF1B_D_REAL
|
|
329728975U, // LDFF1B_H_REAL
|
|
329712591U, // LDFF1B_REAL
|
|
329647055U, // LDFF1B_S_REAL
|
|
329632036U, // LDFF1D_REAL
|
|
329632621U, // LDFF1H_D_REAL
|
|
329730925U, // LDFF1H_REAL
|
|
329649005U, // LDFF1H_S_REAL
|
|
329631687U, // LDFF1SB_D_REAL
|
|
329729991U, // LDFF1SB_H_REAL
|
|
329648071U, // LDFF1SB_S_REAL
|
|
329633313U, // LDFF1SH_D_REAL
|
|
329649697U, // LDFF1SH_S_REAL
|
|
329636406U, // LDFF1SW_D_REAL
|
|
329636210U, // LDFF1W_D_REAL
|
|
329652594U, // LDFF1W_REAL
|
|
302205742U, // LDG
|
|
838881596U, // LDGM
|
|
838879034U, // LDLARB
|
|
838880660U, // LDLARH
|
|
838882216U, // LDLARW
|
|
838882216U, // LDLARX
|
|
329630679U, // LDNF1B_D_IMM_REAL
|
|
329728983U, // LDNF1B_H_IMM_REAL
|
|
329712599U, // LDNF1B_IMM_REAL
|
|
329647063U, // LDNF1B_S_IMM_REAL
|
|
329632044U, // LDNF1D_IMM_REAL
|
|
329632629U, // LDNF1H_D_IMM_REAL
|
|
329730933U, // LDNF1H_IMM_REAL
|
|
329649013U, // LDNF1H_S_IMM_REAL
|
|
329631696U, // LDNF1SB_D_IMM_REAL
|
|
329730000U, // LDNF1SB_H_IMM_REAL
|
|
329648080U, // LDNF1SB_S_IMM_REAL
|
|
329633322U, // LDNF1SH_D_IMM_REAL
|
|
329649706U, // LDNF1SH_S_IMM_REAL
|
|
329636415U, // LDNF1SW_D_IMM_REAL
|
|
329636218U, // LDNF1W_D_IMM_REAL
|
|
329652602U, // LDNF1W_IMM_REAL
|
|
807424755U, // LDNPDi
|
|
807424755U, // LDNPQi
|
|
807424755U, // LDNPSi
|
|
807424755U, // LDNPWi
|
|
807424755U, // LDNPXi
|
|
329712607U, // LDNT1B_ZRI
|
|
329712607U, // LDNT1B_ZRR
|
|
1134937055U, // LDNT1B_ZZR_D_REAL
|
|
1403388895U, // LDNT1B_ZZR_S_REAL
|
|
329632052U, // LDNT1D_ZRI
|
|
329632052U, // LDNT1D_ZRR
|
|
1134938420U, // LDNT1D_ZZR_D_REAL
|
|
329730941U, // LDNT1H_ZRI
|
|
329730941U, // LDNT1H_ZRR
|
|
1134939005U, // LDNT1H_ZZR_D_REAL
|
|
1403390845U, // LDNT1H_ZZR_S_REAL
|
|
1134938073U, // LDNT1SB_ZZR_D_REAL
|
|
1403389913U, // LDNT1SB_ZZR_S_REAL
|
|
1134939699U, // LDNT1SH_ZZR_D_REAL
|
|
1403391539U, // LDNT1SH_ZZR_S_REAL
|
|
1134942792U, // LDNT1SW_ZZR_D_REAL
|
|
329652610U, // LDNT1W_ZRI
|
|
329652610U, // LDNT1W_ZRR
|
|
1134942594U, // LDNT1W_ZZR_D_REAL
|
|
1403394434U, // LDNT1W_ZZR_S_REAL
|
|
807424659U, // LDPDi
|
|
270750355U, // LDPDpost
|
|
270750355U, // LDPDpre
|
|
807424659U, // LDPQi
|
|
270750355U, // LDPQpost
|
|
270750355U, // LDPQpre
|
|
807426641U, // LDPSWi
|
|
270752337U, // LDPSWpost
|
|
270752337U, // LDPSWpre
|
|
807424659U, // LDPSi
|
|
270750355U, // LDPSpost
|
|
270750355U, // LDPSpre
|
|
807424659U, // LDPWi
|
|
270750355U, // LDPWpost
|
|
270750355U, // LDPWpre
|
|
807424659U, // LDPXi
|
|
270750355U, // LDPXpost
|
|
270750355U, // LDPXpre
|
|
838877817U, // LDRAAindexed
|
|
302203513U, // LDRAAwriteback
|
|
838878315U, // LDRABindexed
|
|
302204011U, // LDRABwriteback
|
|
302204738U, // LDRBBpost
|
|
302204738U, // LDRBBpre
|
|
838879042U, // LDRBBroW
|
|
838879042U, // LDRBBroX
|
|
838879042U, // LDRBBui
|
|
302207968U, // LDRBpost
|
|
302207968U, // LDRBpre
|
|
838882272U, // LDRBroW
|
|
838882272U, // LDRBroX
|
|
838882272U, // LDRBui
|
|
1075860448U, // LDRDl
|
|
302207968U, // LDRDpost
|
|
302207968U, // LDRDpre
|
|
838882272U, // LDRDroW
|
|
838882272U, // LDRDroX
|
|
838882272U, // LDRDui
|
|
302206364U, // LDRHHpost
|
|
302206364U, // LDRHHpre
|
|
838880668U, // LDRHHroW
|
|
838880668U, // LDRHHroX
|
|
838880668U, // LDRHHui
|
|
302207968U, // LDRHpost
|
|
302207968U, // LDRHpre
|
|
838882272U, // LDRHroW
|
|
838882272U, // LDRHroX
|
|
838882272U, // LDRHui
|
|
1075860448U, // LDRQl
|
|
302207968U, // LDRQpost
|
|
302207968U, // LDRQpre
|
|
838882272U, // LDRQroW
|
|
838882272U, // LDRQroX
|
|
838882272U, // LDRQui
|
|
302204935U, // LDRSBWpost
|
|
302204935U, // LDRSBWpre
|
|
838879239U, // LDRSBWroW
|
|
838879239U, // LDRSBWroX
|
|
838879239U, // LDRSBWui
|
|
302204935U, // LDRSBXpost
|
|
302204935U, // LDRSBXpre
|
|
838879239U, // LDRSBXroW
|
|
838879239U, // LDRSBXroX
|
|
838879239U, // LDRSBXui
|
|
302206548U, // LDRSHWpost
|
|
302206548U, // LDRSHWpre
|
|
838880852U, // LDRSHWroW
|
|
838880852U, // LDRSHWroX
|
|
838880852U, // LDRSHWui
|
|
302206548U, // LDRSHXpost
|
|
302206548U, // LDRSHXpre
|
|
838880852U, // LDRSHXroW
|
|
838880852U, // LDRSHXroX
|
|
838880852U, // LDRSHXui
|
|
1075862112U, // LDRSWl
|
|
302209632U, // LDRSWpost
|
|
302209632U, // LDRSWpre
|
|
838883936U, // LDRSWroW
|
|
838883936U, // LDRSWroX
|
|
838883936U, // LDRSWui
|
|
1075860448U, // LDRSl
|
|
302207968U, // LDRSpost
|
|
302207968U, // LDRSpre
|
|
838882272U, // LDRSroW
|
|
838882272U, // LDRSroX
|
|
838882272U, // LDRSui
|
|
1075860448U, // LDRWl
|
|
302207968U, // LDRWpost
|
|
302207968U, // LDRWpre
|
|
838882272U, // LDRWroW
|
|
838882272U, // LDRWroX
|
|
838882272U, // LDRWui
|
|
1075860448U, // LDRXl
|
|
302207968U, // LDRXpost
|
|
302207968U, // LDRXpre
|
|
838882272U, // LDRXroW
|
|
838882272U, // LDRXroX
|
|
838882272U, // LDRXui
|
|
839767008U, // LDR_PXI
|
|
922592U, // LDR_ZA
|
|
839767008U, // LDR_ZXI
|
|
3223536786U, // LDSETAB
|
|
3223538723U, // LDSETAH
|
|
3223537030U, // LDSETALB
|
|
3223538883U, // LDSETALH
|
|
3223539582U, // LDSETALW
|
|
3223539582U, // LDSETALX
|
|
3223536498U, // LDSETAW
|
|
3223536498U, // LDSETAX
|
|
3223537709U, // LDSETB
|
|
3223539317U, // LDSETH
|
|
3223537269U, // LDSETLB
|
|
3223538976U, // LDSETLH
|
|
3223539930U, // LDSETLW
|
|
3223539930U, // LDSETLX
|
|
3223541365U, // LDSETW
|
|
3223541365U, // LDSETX
|
|
3223536795U, // LDSMAXAB
|
|
3223538732U, // LDSMAXAH
|
|
3223537040U, // LDSMAXALB
|
|
3223538893U, // LDSMAXALH
|
|
3223539591U, // LDSMAXALW
|
|
3223539591U, // LDSMAXALX
|
|
3223536535U, // LDSMAXAW
|
|
3223536535U, // LDSMAXAX
|
|
3223537846U, // LDSMAXB
|
|
3223539349U, // LDSMAXH
|
|
3223537278U, // LDSMAXLB
|
|
3223539018U, // LDSMAXLH
|
|
3223539985U, // LDSMAXLW
|
|
3223539985U, // LDSMAXLX
|
|
3223542465U, // LDSMAXW
|
|
3223542465U, // LDSMAXX
|
|
3223536714U, // LDSMINAB
|
|
3223538671U, // LDSMINAH
|
|
3223536972U, // LDSMINALB
|
|
3223538825U, // LDSMINALH
|
|
3223539522U, // LDSMINALW
|
|
3223539522U, // LDSMINALX
|
|
3223536381U, // LDSMINAW
|
|
3223536381U, // LDSMINAX
|
|
3223537321U, // LDSMINB
|
|
3223539038U, // LDSMINH
|
|
3223537183U, // LDSMINLB
|
|
3223538924U, // LDSMINLH
|
|
3223539828U, // LDSMINLW
|
|
3223539828U, // LDSMINLX
|
|
3223540120U, // LDSMINW
|
|
3223540120U, // LDSMINX
|
|
838879087U, // LDTRBi
|
|
838880713U, // LDTRHi
|
|
838879246U, // LDTRSBWi
|
|
838879246U, // LDTRSBXi
|
|
838880859U, // LDTRSHWi
|
|
838880859U, // LDTRSHXi
|
|
838883943U, // LDTRSWi
|
|
838882460U, // LDTRWi
|
|
838882460U, // LDTRXi
|
|
3223536805U, // LDUMAXAB
|
|
3223538742U, // LDUMAXAH
|
|
3223537051U, // LDUMAXALB
|
|
3223538904U, // LDUMAXALH
|
|
3223539601U, // LDUMAXALW
|
|
3223539601U, // LDUMAXALX
|
|
3223536544U, // LDUMAXAW
|
|
3223536544U, // LDUMAXAX
|
|
3223537855U, // LDUMAXB
|
|
3223539358U, // LDUMAXH
|
|
3223537288U, // LDUMAXLB
|
|
3223539028U, // LDUMAXLH
|
|
3223539994U, // LDUMAXLW
|
|
3223539994U, // LDUMAXLX
|
|
3223542473U, // LDUMAXW
|
|
3223542473U, // LDUMAXX
|
|
3223536724U, // LDUMINAB
|
|
3223538681U, // LDUMINAH
|
|
3223536983U, // LDUMINALB
|
|
3223538836U, // LDUMINALH
|
|
3223539532U, // LDUMINALW
|
|
3223539532U, // LDUMINALX
|
|
3223536390U, // LDUMINAW
|
|
3223536390U, // LDUMINAX
|
|
3223537330U, // LDUMINB
|
|
3223539047U, // LDUMINH
|
|
3223537193U, // LDUMINLB
|
|
3223538934U, // LDUMINLH
|
|
3223539837U, // LDUMINLW
|
|
3223539837U, // LDUMINLX
|
|
3223540128U, // LDUMINW
|
|
3223540128U, // LDUMINX
|
|
838879107U, // LDURBBi
|
|
838882483U, // LDURBi
|
|
838882483U, // LDURDi
|
|
838880733U, // LDURHHi
|
|
838882483U, // LDURHi
|
|
838882483U, // LDURQi
|
|
838879254U, // LDURSBWi
|
|
838879254U, // LDURSBXi
|
|
838880867U, // LDURSHWi
|
|
838880867U, // LDURSHXi
|
|
838883951U, // LDURSWi
|
|
838882483U, // LDURSi
|
|
838882483U, // LDURWi
|
|
838882483U, // LDURXi
|
|
807424864U, // LDXPW
|
|
807424864U, // LDXPX
|
|
838879146U, // LDXRB
|
|
838880772U, // LDXRH
|
|
838882547U, // LDXRW
|
|
838882547U, // LDXRX
|
|
3223360594U, // LSLR_ZPmZ_B
|
|
3223376978U, // LSLR_ZPmZ_D
|
|
3519091794U, // LSLR_ZPmZ_H
|
|
3223409746U, // LSLR_ZPmZ_S
|
|
807424186U, // LSLVWr
|
|
807424186U, // LSLVXr
|
|
3223359674U, // LSL_WIDE_ZPmZ_B
|
|
3519090874U, // LSL_WIDE_ZPmZ_H
|
|
3223408826U, // LSL_WIDE_ZPmZ_S
|
|
3760230586U, // LSL_WIDE_ZZZ_B
|
|
2179010746U, // LSL_WIDE_ZZZ_H
|
|
4028715194U, // LSL_WIDE_ZZZ_S
|
|
3223359674U, // LSL_ZPmI_B
|
|
3223376058U, // LSL_ZPmI_D
|
|
3519090874U, // LSL_ZPmI_H
|
|
3223408826U, // LSL_ZPmI_S
|
|
3223359674U, // LSL_ZPmZ_B
|
|
3223376058U, // LSL_ZPmZ_D
|
|
3519090874U, // LSL_ZPmZ_H
|
|
3223408826U, // LSL_ZPmZ_S
|
|
3760230586U, // LSL_ZZI_B
|
|
2418069690U, // LSL_ZZI_D
|
|
2179010746U, // LSL_ZZI_H
|
|
4028715194U, // LSL_ZZI_S
|
|
3223360641U, // LSRR_ZPmZ_B
|
|
3223377025U, // LSRR_ZPmZ_D
|
|
3519091841U, // LSRR_ZPmZ_H
|
|
3223409793U, // LSRR_ZPmZ_S
|
|
807425164U, // LSRVWr
|
|
807425164U, // LSRVXr
|
|
3223360652U, // LSR_WIDE_ZPmZ_B
|
|
3519091852U, // LSR_WIDE_ZPmZ_H
|
|
3223409804U, // LSR_WIDE_ZPmZ_S
|
|
3760231564U, // LSR_WIDE_ZZZ_B
|
|
2179011724U, // LSR_WIDE_ZZZ_H
|
|
4028716172U, // LSR_WIDE_ZZZ_S
|
|
3223360652U, // LSR_ZPmI_B
|
|
3223377036U, // LSR_ZPmI_D
|
|
3519091852U, // LSR_ZPmI_H
|
|
3223409804U, // LSR_ZPmI_S
|
|
3223360652U, // LSR_ZPmZ_B
|
|
3223377036U, // LSR_ZPmZ_D
|
|
3519091852U, // LSR_ZPmZ_H
|
|
3223409804U, // LSR_ZPmZ_S
|
|
3760231564U, // LSR_ZZI_B
|
|
2418070668U, // LSR_ZZI_D
|
|
2179011724U, // LSR_ZZI_H
|
|
4028716172U, // LSR_ZZI_S
|
|
807422454U, // MADDWrrr
|
|
807422454U, // MADDXrrr
|
|
3223357807U, // MAD_ZPmZZ_B
|
|
3223374191U, // MAD_ZPmZZ_D
|
|
3519089007U, // MAD_ZPmZZ_H
|
|
3223406959U, // MAD_ZPmZZ_S
|
|
3223358570U, // MATCH_PPzZZ_B
|
|
1640041578U, // MATCH_PPzZZ_H
|
|
3223356116U, // MLA_ZPmZZ_B
|
|
3223372500U, // MLA_ZPmZZ_D
|
|
3519087316U, // MLA_ZPmZZ_H
|
|
3223405268U, // MLA_ZPmZZ_S
|
|
1075888852U, // MLA_ZZZI_D
|
|
2185298644U, // MLA_ZZZI_H
|
|
1344357076U, // MLA_ZZZI_S
|
|
2959213268U, // MLAv16i8
|
|
2961310420U, // MLAv2i32
|
|
2961310420U, // MLAv2i32_indexed
|
|
2965504724U, // MLAv4i16
|
|
2965504724U, // MLAv4i16_indexed
|
|
2967601876U, // MLAv4i32
|
|
2967601876U, // MLAv4i32_indexed
|
|
2969699028U, // MLAv8i16
|
|
2969699028U, // MLAv8i16_indexed
|
|
2971796180U, // MLAv8i8
|
|
3223360912U, // MLS_ZPmZZ_B
|
|
3223377296U, // MLS_ZPmZZ_D
|
|
3519092112U, // MLS_ZPmZZ_H
|
|
3223410064U, // MLS_ZPmZZ_S
|
|
1075893648U, // MLS_ZZZI_D
|
|
2185303440U, // MLS_ZZZI_H
|
|
1344361872U, // MLS_ZZZI_S
|
|
2959218064U, // MLSv16i8
|
|
2961315216U, // MLSv2i32
|
|
2961315216U, // MLSv2i32_indexed
|
|
2965509520U, // MLSv4i16
|
|
2965509520U, // MLSv4i16_indexed
|
|
2967606672U, // MLSv4i32
|
|
2967606672U, // MLSv4i32_indexed
|
|
2969703824U, // MLSv8i16
|
|
2969703824U, // MLSv8i16_indexed
|
|
2971800976U, // MLSv8i8
|
|
941323U, // MOPSSETGE
|
|
941384U, // MOPSSETGEN
|
|
942272U, // MOPSSETGET
|
|
941745U, // MOPSSETGETN
|
|
3491778300U, // MOVID
|
|
3764489980U, // MOVIv16b_ns
|
|
3500248828U, // MOVIv2d_ns
|
|
3766587132U, // MOVIv2i32
|
|
3766587132U, // MOVIv2s_msl
|
|
3770781436U, // MOVIv4i16
|
|
3772878588U, // MOVIv4i32
|
|
3772878588U, // MOVIv4s_msl
|
|
3777072892U, // MOVIv8b_ns
|
|
3774975740U, // MOVIv8i16
|
|
807423751U, // MOVKWi
|
|
807423751U, // MOVKXi
|
|
3760214553U, // MOVNWi
|
|
3760214553U, // MOVNXi
|
|
2136813U, // MOVPRFX_ZPmZ_B
|
|
2153197U, // MOVPRFX_ZPmZ_D
|
|
272702189U, // MOVPRFX_ZPmZ_H
|
|
2185965U, // MOVPRFX_ZPmZ_S
|
|
3223362285U, // MOVPRFX_ZPzZ_B
|
|
3223378669U, // MOVPRFX_ZPzZ_D
|
|
1640045293U, // MOVPRFX_ZPzZ_H
|
|
3223411437U, // MOVPRFX_ZPzZ_S
|
|
3224230637U, // MOVPRFX_ZZ
|
|
3760216952U, // MOVZWi
|
|
3760216952U, // MOVZXi
|
|
4028651004U, // MRS
|
|
3223357427U, // MSB_ZPmZZ_B
|
|
3223373811U, // MSB_ZPmZZ_D
|
|
3519088627U, // MSB_ZPmZZ_H
|
|
3223406579U, // MSB_ZPmZZ_S
|
|
955537U, // MSR
|
|
971921U, // MSRpstateImm1
|
|
971921U, // MSRpstateImm4
|
|
988305U, // MSRpstatesvcrImm1
|
|
807422068U, // MSUBWrrr
|
|
807422068U, // MSUBXrrr
|
|
3760230634U, // MUL_ZI_B
|
|
2418069738U, // MUL_ZI_D
|
|
2179010794U, // MUL_ZI_H
|
|
4028715242U, // MUL_ZI_S
|
|
3223359722U, // MUL_ZPmZ_B
|
|
3223376106U, // MUL_ZPmZ_D
|
|
3519090922U, // MUL_ZPmZ_H
|
|
3223408874U, // MUL_ZPmZ_S
|
|
2418069738U, // MUL_ZZZI_D
|
|
2179010794U, // MUL_ZZZI_H
|
|
4028715242U, // MUL_ZZZI_S
|
|
3760230634U, // MUL_ZZZ_B
|
|
2418069738U, // MUL_ZZZ_D
|
|
2179010794U, // MUL_ZZZ_H
|
|
4028715242U, // MUL_ZZZ_S
|
|
543265002U, // MULv16i8
|
|
545362154U, // MULv2i32
|
|
545362154U, // MULv2i32_indexed
|
|
549556458U, // MULv4i16
|
|
549556458U, // MULv4i16_indexed
|
|
551653610U, // MULv4i32
|
|
551653610U, // MULv4i32_indexed
|
|
553750762U, // MULv8i16
|
|
553750762U, // MULv8i16_indexed
|
|
555847914U, // MULv8i8
|
|
3766587113U, // MVNIv2i32
|
|
3766587113U, // MVNIv2s_msl
|
|
3770781417U, // MVNIv4i16
|
|
3772878569U, // MVNIv4i32
|
|
3772878569U, // MVNIv4s_msl
|
|
3774975721U, // MVNIv8i16
|
|
3223360860U, // NANDS_PPzPP
|
|
3223357978U, // NAND_PPzPP
|
|
2418069680U, // NBSL_ZZZZ
|
|
2132788U, // NEG_ZPmZ_B
|
|
2149172U, // NEG_ZPmZ_D
|
|
272698164U, // NEG_ZPmZ_H
|
|
2181940U, // NEG_ZPmZ_S
|
|
543263540U, // NEGv16i8
|
|
807422772U, // NEGv1i64
|
|
545360692U, // NEGv2i32
|
|
547457844U, // NEGv2i64
|
|
549554996U, // NEGv4i16
|
|
551652148U, // NEGv4i32
|
|
553749300U, // NEGv8i16
|
|
555846452U, // NEGv8i8
|
|
3223358569U, // NMATCH_PPzZZ_B
|
|
1640041577U, // NMATCH_PPzZZ_H
|
|
3223361031U, // NORS_PPzPP
|
|
3223360613U, // NOR_PPzPP
|
|
2136114U, // NOT_ZPmZ_B
|
|
2152498U, // NOT_ZPmZ_D
|
|
272701490U, // NOT_ZPmZ_H
|
|
2185266U, // NOT_ZPmZ_S
|
|
543266866U, // NOTv16i8
|
|
555849778U, // NOTv8i8
|
|
3223360951U, // ORNS_PPzPP
|
|
807424475U, // ORNWrs
|
|
807424475U, // ORNXrs
|
|
3223359963U, // ORN_PPzPP
|
|
543265243U, // ORNv16i8
|
|
555848155U, // ORNv8i8
|
|
3223361037U, // ORRS_PPzPP
|
|
807425142U, // ORRWri
|
|
807425142U, // ORRWrs
|
|
807425142U, // ORRXri
|
|
807425142U, // ORRXrs
|
|
3223360630U, // ORR_PPzPP
|
|
2418070646U, // ORR_ZI
|
|
3223360630U, // ORR_ZPmZ_B
|
|
3223377014U, // ORR_ZPmZ_D
|
|
3519091830U, // ORR_ZPmZ_H
|
|
3223409782U, // ORR_ZPmZ_S
|
|
2418070646U, // ORR_ZZZ
|
|
543265910U, // ORRv16i8
|
|
813831286U, // ORRv2i32
|
|
818025590U, // ORRv4i16
|
|
820122742U, // ORRv4i32
|
|
822219894U, // ORRv8i16
|
|
555848822U, // ORRv8i8
|
|
153938U, // ORV_VPZ_B
|
|
1646434642U, // ORV_VPZ_D
|
|
1648548178U, // ORV_VPZ_H
|
|
1638078802U, // ORV_VPZ_S
|
|
270746259U, // PACDA
|
|
270746840U, // PACDB
|
|
213929U, // PACDZA
|
|
215240U, // PACDZB
|
|
807420592U, // PACGA
|
|
270746302U, // PACIA
|
|
7296U, // PACIA1716
|
|
7261U, // PACIASP
|
|
7252U, // PACIAZ
|
|
270746875U, // PACIB
|
|
7207U, // PACIB1716
|
|
7287U, // PACIBSP
|
|
7270U, // PACIBZ
|
|
213945U, // PACIZA
|
|
215256U, // PACIZB
|
|
35542U, // PFALSE
|
|
3223361620U, // PFIRST_B
|
|
4028679687U, // PMULLB_ZZZ_D
|
|
2273379847U, // PMULLB_ZZZ_H
|
|
128288263U, // PMULLB_ZZZ_Q
|
|
4028684095U, // PMULLT_ZZZ_D
|
|
2273384255U, // PMULLT_ZZZ_H
|
|
128292671U, // PMULLT_ZZZ_Q
|
|
553746720U, // PMULLv16i8
|
|
130125919U, // PMULLv1i64
|
|
398557472U, // PMULLv2i64
|
|
553750623U, // PMULLv8i8
|
|
3760230646U, // PMUL_ZZZ_B
|
|
543265014U, // PMULv16i8
|
|
555847926U, // PMULv8i8
|
|
3223361680U, // PNEXT_B
|
|
3223378064U, // PNEXT_D
|
|
2176915600U, // PNEXT_H
|
|
3223410832U, // PNEXT_S
|
|
2184135918U, // PRFB_D_PZI
|
|
2215593198U, // PRFB_D_SCALED
|
|
2215593198U, // PRFB_D_SXTW_SCALED
|
|
2215593198U, // PRFB_D_UXTW_SCALED
|
|
2215593198U, // PRFB_PRI
|
|
2215593198U, // PRFB_PRR
|
|
2175747310U, // PRFB_S_PZI
|
|
2215593198U, // PRFB_S_SXTW_SCALED
|
|
2215593198U, // PRFB_S_UXTW_SCALED
|
|
2184137236U, // PRFD_D_PZI
|
|
2215594516U, // PRFD_D_SCALED
|
|
2215594516U, // PRFD_D_SXTW_SCALED
|
|
2215594516U, // PRFD_D_UXTW_SCALED
|
|
2215594516U, // PRFD_PRI
|
|
2215594516U, // PRFD_PRR
|
|
2175748628U, // PRFD_S_PZI
|
|
2215594516U, // PRFD_S_SXTW_SCALED
|
|
2215594516U, // PRFD_S_UXTW_SCALED
|
|
2184137849U, // PRFH_D_PZI
|
|
2215595129U, // PRFH_D_SCALED
|
|
2215595129U, // PRFH_D_SXTW_SCALED
|
|
2215595129U, // PRFH_D_UXTW_SCALED
|
|
2215595129U, // PRFH_PRI
|
|
2215595129U, // PRFH_PRR
|
|
2175749241U, // PRFH_S_PZI
|
|
2215595129U, // PRFH_S_SXTW_SCALED
|
|
2215595129U, // PRFH_S_UXTW_SCALED
|
|
1076859190U, // PRFMl
|
|
839881014U, // PRFMroW
|
|
839881014U, // PRFMroX
|
|
839881014U, // PRFMui
|
|
2215598601U, // PRFS_PRR
|
|
839881069U, // PRFUMi
|
|
2184141321U, // PRFW_D_PZI
|
|
2215598601U, // PRFW_D_SCALED
|
|
2215598601U, // PRFW_D_SXTW_SCALED
|
|
2215598601U, // PRFW_D_UXTW_SCALED
|
|
2215598601U, // PRFW_PRI
|
|
2175752713U, // PRFW_S_PZI
|
|
2215598601U, // PRFW_S_SXTW_SCALED
|
|
2215598601U, // PRFW_S_UXTW_SCALED
|
|
3224227842U, // PSEL_PPPRI_B
|
|
3224227842U, // PSEL_PPPRI_D
|
|
3224227842U, // PSEL_PPPRI_H
|
|
3224227842U, // PSEL_PPPRI_S
|
|
3761100870U, // PTEST_PP
|
|
1881183587U, // PTRUES_B
|
|
1881199971U, // PTRUES_D
|
|
132191587U, // PTRUES_H
|
|
1881232739U, // PTRUES_S
|
|
1881180912U, // PTRUE_B
|
|
1881197296U, // PTRUE_D
|
|
132188912U, // PTRUE_H
|
|
1881230064U, // PTRUE_S
|
|
1736511159U, // PUNPKHI_PP
|
|
1736512048U, // PUNPKLO_PP
|
|
1881179808U, // RADDHNB_ZZZ_B
|
|
2172716704U, // RADDHNB_ZZZ_H
|
|
2418099872U, // RADDHNB_ZZZ_S
|
|
2686490529U, // RADDHNT_ZZZ_B
|
|
2174818209U, // RADDHNT_ZZZ_H
|
|
1075926945U, // RADDHNT_ZZZ_S
|
|
545362314U, // RADDHNv2i64_v2i32
|
|
2967601515U, // RADDHNv2i64_v4i32
|
|
549556618U, // RADDHNv4i32_v4i16
|
|
2969698667U, // RADDHNv4i32_v8i16
|
|
2959212907U, // RADDHNv8i16_v16i8
|
|
555848074U, // RADDHNv8i16_v8i8
|
|
547455102U, // RAX1
|
|
2418065534U, // RAX1_ZZZ_D
|
|
807425690U, // RBITWr
|
|
807425690U, // RBITXr
|
|
2135706U, // RBIT_ZPmZ_B
|
|
2152090U, // RBIT_ZPmZ_D
|
|
272701082U, // RBIT_ZPmZ_H
|
|
2184858U, // RBIT_ZPmZ_S
|
|
543266458U, // RBITv16i8
|
|
555849370U, // RBITv8i8
|
|
3223361012U, // RDFFRS_PPz
|
|
3223360485U, // RDFFR_PPz_REAL
|
|
37861U, // RDFFR_P_REAL
|
|
807424267U, // RDVLI_XI
|
|
22128U, // RET
|
|
8592U, // RETAA
|
|
8599U, // RETAB
|
|
807420499U, // REV16Wr
|
|
807420499U, // REV16Xr
|
|
543261267U, // REV16v16i8
|
|
555844179U, // REV16v8i8
|
|
807420036U, // REV32Xr
|
|
543260804U, // REV32v16i8
|
|
549552260U, // REV32v4i16
|
|
553746564U, // REV32v8i16
|
|
555843716U, // REV32v8i8
|
|
543261242U, // REV64v16i8
|
|
545358394U, // REV64v2i32
|
|
549552698U, // REV64v4i16
|
|
551649850U, // REV64v4i32
|
|
553747002U, // REV64v8i16
|
|
555844154U, // REV64v8i8
|
|
2148496U, // REVB_ZPmZ_D
|
|
272697488U, // REVB_ZPmZ_H
|
|
2181264U, // REVB_ZPmZ_S
|
|
541428297U, // REVD_ZPmZ
|
|
2150031U, // REVH_ZPmZ_D
|
|
2182799U, // REVH_ZPmZ_S
|
|
2153107U, // REVW_ZPmZ_D
|
|
807426282U, // REVWr
|
|
807426282U, // REVXr
|
|
3760232682U, // REV_PP_B
|
|
2418071786U, // REV_PP_D
|
|
1642141930U, // REV_PP_H
|
|
4028717290U, // REV_PP_S
|
|
3760232682U, // REV_ZZ_B
|
|
2418071786U, // REV_ZZ_D
|
|
1642141930U, // REV_ZZ_H
|
|
4028717290U, // REV_ZZ_S
|
|
807422721U, // RMIF
|
|
807425130U, // RORVWr
|
|
807425130U, // RORVXr
|
|
1881179855U, // RSHRNB_ZZI_B
|
|
2172716751U, // RSHRNB_ZZI_H
|
|
2418099919U, // RSHRNB_ZZI_S
|
|
2686490564U, // RSHRNT_ZZI_B
|
|
2174818244U, // RSHRNT_ZZI_H
|
|
1075926980U, // RSHRNT_ZZI_S
|
|
2959212936U, // RSHRNv16i8_shift
|
|
545362379U, // RSHRNv2i32_shift
|
|
549556683U, // RSHRNv4i16_shift
|
|
2967601544U, // RSHRNv4i32_shift
|
|
2969698696U, // RSHRNv8i16_shift
|
|
555848139U, // RSHRNv8i8_shift
|
|
1881179799U, // RSUBHNB_ZZZ_B
|
|
2172716695U, // RSUBHNB_ZZZ_H
|
|
2418099863U, // RSUBHNB_ZZZ_S
|
|
2686490520U, // RSUBHNT_ZZZ_B
|
|
2174818200U, // RSUBHNT_ZZZ_H
|
|
1075926936U, // RSUBHNT_ZZZ_S
|
|
545362306U, // RSUBHNv2i64_v2i32
|
|
2967601506U, // RSUBHNv2i64_v4i32
|
|
549556610U, // RSUBHNv4i32_v4i16
|
|
2969698658U, // RSUBHNv4i32_v8i16
|
|
2959212898U, // RSUBHNv8i16_v16i8
|
|
555848066U, // RSUBHNv8i16_v8i8
|
|
1344324879U, // SABALB_ZZZ_D
|
|
2281768207U, // SABALB_ZZZ_H
|
|
2686534927U, // SABALB_ZZZ_S
|
|
1344329382U, // SABALT_ZZZ_D
|
|
2281772710U, // SABALT_ZZZ_H
|
|
2686539430U, // SABALT_ZZZ_S
|
|
2969698468U, // SABALv16i8_v8i16
|
|
2963410701U, // SABALv2i32_v2i64
|
|
2967605005U, // SABALv4i16_v4i32
|
|
2963407012U, // SABALv4i32_v2i64
|
|
2967601316U, // SABALv8i16_v4i32
|
|
2969702157U, // SABALv8i8_v8i16
|
|
1344307847U, // SABA_ZZZ_B
|
|
1075888775U, // SABA_ZZZ_D
|
|
2185298567U, // SABA_ZZZ_H
|
|
1344356999U, // SABA_ZZZ_S
|
|
2959213191U, // SABAv16i8
|
|
2961310343U, // SABAv2i32
|
|
2965504647U, // SABAv4i16
|
|
2967601799U, // SABAv4i32
|
|
2969698951U, // SABAv8i16
|
|
2971796103U, // SABAv8i8
|
|
4028679620U, // SABDLB_ZZZ_D
|
|
2273379780U, // SABDLB_ZZZ_H
|
|
1881228740U, // SABDLB_ZZZ_S
|
|
4028684023U, // SABDLT_ZZZ_D
|
|
2273384183U, // SABDLT_ZZZ_H
|
|
1881233143U, // SABDLT_ZZZ_S
|
|
553746662U, // SABDLv16i8_v8i16
|
|
547459006U, // SABDLv2i32_v2i64
|
|
551653310U, // SABDLv4i16_v4i32
|
|
547455206U, // SABDLv4i32_v2i64
|
|
551649510U, // SABDLv8i16_v4i32
|
|
553750462U, // SABDLv8i8_v8i16
|
|
3223357832U, // SABD_ZPmZ_B
|
|
3223374216U, // SABD_ZPmZ_D
|
|
3519089032U, // SABD_ZPmZ_H
|
|
3223406984U, // SABD_ZPmZ_S
|
|
543263112U, // SABDv16i8
|
|
545360264U, // SABDv2i32
|
|
549554568U, // SABDv4i16
|
|
551651720U, // SABDv4i32
|
|
553748872U, // SABDv8i16
|
|
555846024U, // SABDv8i8
|
|
3223376548U, // SADALP_ZPmZ_D
|
|
3519091364U, // SADALP_ZPmZ_H
|
|
3223409316U, // SADALP_ZPmZ_S
|
|
2969703076U, // SADALPv16i8_v8i16
|
|
3089240740U, // SADALPv2i32_v1i64
|
|
2961314468U, // SADALPv4i16_v2i32
|
|
2963411620U, // SADALPv4i32_v2i64
|
|
2967605924U, // SADALPv8i16_v4i32
|
|
2965508772U, // SADALPv8i8_v4i16
|
|
4028683846U, // SADDLBT_ZZZ_D
|
|
2273384006U, // SADDLBT_ZZZ_H
|
|
1881232966U, // SADDLBT_ZZZ_S
|
|
4028679645U, // SADDLB_ZZZ_D
|
|
2273379805U, // SADDLB_ZZZ_H
|
|
1881228765U, // SADDLB_ZZZ_S
|
|
553751220U, // SADDLPv16i8_v8i16
|
|
673288884U, // SADDLPv2i32_v1i64
|
|
545362612U, // SADDLPv4i16_v2i32
|
|
547459764U, // SADDLPv4i32_v2i64
|
|
551654068U, // SADDLPv8i16_v4i32
|
|
549556916U, // SADDLPv8i8_v4i16
|
|
4028684039U, // SADDLT_ZZZ_D
|
|
2273384199U, // SADDLT_ZZZ_H
|
|
1881233159U, // SADDLT_ZZZ_S
|
|
538990849U, // SADDLVv16i8v
|
|
538990849U, // SADDLVv4i16v
|
|
538990849U, // SADDLVv4i32v
|
|
538990849U, // SADDLVv8i16v
|
|
538990849U, // SADDLVv8i8v
|
|
553746678U, // SADDLv16i8_v8i16
|
|
547459044U, // SADDLv2i32_v2i64
|
|
551653348U, // SADDLv4i16_v4i32
|
|
547455222U, // SADDLv4i32_v2i64
|
|
551649526U, // SADDLv8i16_v4i32
|
|
553750500U, // SADDLv8i8_v8i16
|
|
1745000662U, // SADDV_VPZ_B
|
|
1648531670U, // SADDV_VPZ_H
|
|
1638045910U, // SADDV_VPZ_S
|
|
2418067622U, // SADDWB_ZZZ_D
|
|
2179008678U, // SADDWB_ZZZ_H
|
|
4028713126U, // SADDWB_ZZZ_S
|
|
2418071674U, // SADDWT_ZZZ_D
|
|
2179012730U, // SADDWT_ZZZ_H
|
|
4028717178U, // SADDWT_ZZZ_S
|
|
553746952U, // SADDWv16i8_v8i16
|
|
547461627U, // SADDWv2i32_v2i64
|
|
551655931U, // SADDWv4i16_v4i32
|
|
547455496U, // SADDWv4i32_v2i64
|
|
551649800U, // SADDWv8i16_v4i32
|
|
553753083U, // SADDWv8i8_v8i16
|
|
8605U, // SB
|
|
1075889590U, // SBCLB_ZZZ_D
|
|
1344357814U, // SBCLB_ZZZ_S
|
|
1075893993U, // SBCLT_ZZZ_D
|
|
1344362217U, // SBCLT_ZZZ_S
|
|
807425348U, // SBCSWr
|
|
807425348U, // SBCSXr
|
|
807422191U, // SBCWr
|
|
807422191U, // SBCXr
|
|
807424298U, // SBFMWri
|
|
807424298U, // SBFMXri
|
|
3760231108U, // SCLAMP_ZZZ_B
|
|
2418070212U, // SCLAMP_ZZZ_D
|
|
2179011268U, // SCLAMP_ZZZ_H
|
|
4028715716U, // SCLAMP_ZZZ_S
|
|
807422727U, // SCVTFSWDri
|
|
807422727U, // SCVTFSWHri
|
|
807422727U, // SCVTFSWSri
|
|
807422727U, // SCVTFSXDri
|
|
807422727U, // SCVTFSXHri
|
|
807422727U, // SCVTFSXSri
|
|
807422727U, // SCVTFUWDri
|
|
807422727U, // SCVTFUWHri
|
|
807422727U, // SCVTFUWSri
|
|
807422727U, // SCVTFUXDri
|
|
807422727U, // SCVTFUXHri
|
|
807422727U, // SCVTFUXSri
|
|
2149127U, // SCVTF_ZPmZ_DtoD
|
|
541133575U, // SCVTF_ZPmZ_DtoH
|
|
2181895U, // SCVTF_ZPmZ_DtoS
|
|
272698119U, // SCVTF_ZPmZ_HtoH
|
|
2149127U, // SCVTF_ZPmZ_StoD
|
|
541133575U, // SCVTF_ZPmZ_StoH
|
|
2181895U, // SCVTF_ZPmZ_StoS
|
|
807422727U, // SCVTFd
|
|
807422727U, // SCVTFh
|
|
807422727U, // SCVTFs
|
|
807422727U, // SCVTFv1i16
|
|
807422727U, // SCVTFv1i32
|
|
807422727U, // SCVTFv1i64
|
|
545360647U, // SCVTFv2f32
|
|
547457799U, // SCVTFv2f64
|
|
545360647U, // SCVTFv2i32_shift
|
|
547457799U, // SCVTFv2i64_shift
|
|
549554951U, // SCVTFv4f16
|
|
551652103U, // SCVTFv4f32
|
|
549554951U, // SCVTFv4i16_shift
|
|
551652103U, // SCVTFv4i32_shift
|
|
553749255U, // SCVTFv8f16
|
|
553749255U, // SCVTFv8i16_shift
|
|
3223377109U, // SDIVR_ZPmZ_D
|
|
3223409877U, // SDIVR_ZPmZ_S
|
|
807426293U, // SDIVWr
|
|
807426293U, // SDIVXr
|
|
3223378165U, // SDIV_ZPmZ_D
|
|
3223410933U, // SDIV_ZPmZ_S
|
|
2686507044U, // SDOT_ZZZI_D
|
|
1344362532U, // SDOT_ZZZI_S
|
|
2686507044U, // SDOT_ZZZ_D
|
|
1344362532U, // SDOT_ZZZ_S
|
|
2967607332U, // SDOTlanev16i8
|
|
2961315876U, // SDOTlanev8i8
|
|
2967607332U, // SDOTv16i8
|
|
2961315876U, // SDOTv8i8
|
|
3223359485U, // SEL_PPPP
|
|
3223359485U, // SEL_ZPZZ_B
|
|
3223375869U, // SEL_ZPZZ_D
|
|
2176913405U, // SEL_ZPZZ_H
|
|
3223408637U, // SEL_ZPZZ_S
|
|
941331U, // SETE
|
|
941393U, // SETEN
|
|
942281U, // SETET
|
|
941755U, // SETETN
|
|
16971U, // SETF16
|
|
16986U, // SETF8
|
|
8653U, // SETFFR
|
|
941353U, // SETGM
|
|
941418U, // SETGMN
|
|
942306U, // SETGMT
|
|
941783U, // SETGMTN
|
|
942241U, // SETGP
|
|
941452U, // SETGPN
|
|
942340U, // SETGPT
|
|
941821U, // SETGPTN
|
|
941361U, // SETM
|
|
941427U, // SETMN
|
|
942315U, // SETMT
|
|
941793U, // SETMTN
|
|
942249U, // SETP
|
|
941461U, // SETPN
|
|
942349U, // SETPT
|
|
941831U, // SETPTN
|
|
270747880U, // SHA1Crrr
|
|
807422816U, // SHA1Hrr
|
|
270749987U, // SHA1Mrrr
|
|
270750303U, // SHA1Prrr
|
|
2967601153U, // SHA1SU0rrr
|
|
2967601236U, // SHA1SU1rr
|
|
270745754U, // SHA256H2rrr
|
|
270748616U, // SHA256Hrrr
|
|
2967601173U, // SHA256SU0rr
|
|
2967601256U, // SHA256SU1rrr
|
|
270748563U, // SHA512H
|
|
270745744U, // SHA512H2
|
|
2963406858U, // SHA512SU0
|
|
2963406941U, // SHA512SU1
|
|
3223357927U, // SHADD_ZPmZ_B
|
|
3223374311U, // SHADD_ZPmZ_D
|
|
3519089127U, // SHADD_ZPmZ_H
|
|
3223407079U, // SHADD_ZPmZ_S
|
|
543263207U, // SHADDv16i8
|
|
545360359U, // SHADDv2i32
|
|
549554663U, // SHADDv4i16
|
|
551651815U, // SHADDv4i32
|
|
553748967U, // SHADDv8i16
|
|
555846119U, // SHADDv8i8
|
|
553746695U, // SHLLv16i8
|
|
547459145U, // SHLLv2i32
|
|
551653449U, // SHLLv4i16
|
|
547455239U, // SHLLv4i32
|
|
551649543U, // SHLLv8i16
|
|
553750601U, // SHLLv8i8
|
|
807424018U, // SHLd
|
|
543264786U, // SHLv16i8_shift
|
|
545361938U, // SHLv2i32_shift
|
|
547459090U, // SHLv2i64_shift
|
|
549556242U, // SHLv4i16_shift
|
|
551653394U, // SHLv4i32_shift
|
|
553750546U, // SHLv8i16_shift
|
|
555847698U, // SHLv8i8_shift
|
|
1881179837U, // SHRNB_ZZI_B
|
|
2172716733U, // SHRNB_ZZI_H
|
|
2418099901U, // SHRNB_ZZI_S
|
|
2686490546U, // SHRNT_ZZI_B
|
|
2174818226U, // SHRNT_ZZI_H
|
|
1075926962U, // SHRNT_ZZI_S
|
|
2959212918U, // SHRNv16i8_shift
|
|
545362363U, // SHRNv2i32_shift
|
|
549556667U, // SHRNv4i16_shift
|
|
2967601526U, // SHRNv4i32_shift
|
|
2969698678U, // SHRNv8i16_shift
|
|
555848123U, // SHRNv8i8_shift
|
|
3223360443U, // SHSUBR_ZPmZ_B
|
|
3223376827U, // SHSUBR_ZPmZ_D
|
|
3519091643U, // SHSUBR_ZPmZ_H
|
|
3223409595U, // SHSUBR_ZPmZ_S
|
|
3223357541U, // SHSUB_ZPmZ_B
|
|
3223373925U, // SHSUB_ZPmZ_D
|
|
3519088741U, // SHSUB_ZPmZ_H
|
|
3223406693U, // SHSUB_ZPmZ_S
|
|
543262821U, // SHSUBv16i8
|
|
545359973U, // SHSUBv2i32
|
|
549554277U, // SHSUBv4i16
|
|
551651429U, // SHSUBv4i32
|
|
553748581U, // SHSUBv8i16
|
|
555845733U, // SHSUBv8i8
|
|
1344311007U, // SLI_ZZI_B
|
|
1075891935U, // SLI_ZZI_D
|
|
2185301727U, // SLI_ZZI_H
|
|
1344360159U, // SLI_ZZI_S
|
|
270749407U, // SLId
|
|
2959216351U, // SLIv16i8_shift
|
|
2961313503U, // SLIv2i32_shift
|
|
2963410655U, // SLIv2i64_shift
|
|
2965507807U, // SLIv4i16_shift
|
|
2967604959U, // SLIv4i32_shift
|
|
2969702111U, // SLIv8i16_shift
|
|
2971799263U, // SLIv8i8_shift
|
|
2967601267U, // SM3PARTW1
|
|
2967601688U, // SM3PARTW2
|
|
551649351U, // SM3SS1
|
|
2967601761U, // SM3TT1A
|
|
2967602165U, // SM3TT1B
|
|
2967601770U, // SM3TT2A
|
|
2967602194U, // SM3TT2B
|
|
2967603791U, // SM4E
|
|
4028717844U, // SM4EKEY_ZZZ_S
|
|
551656212U, // SM4ENCKEY
|
|
4028713551U, // SM4E_ZZZ_S
|
|
807423956U, // SMADDLrrr
|
|
3223360338U, // SMAXP_ZPmZ_B
|
|
3223376722U, // SMAXP_ZPmZ_D
|
|
3519091538U, // SMAXP_ZPmZ_H
|
|
3223409490U, // SMAXP_ZPmZ_S
|
|
543265618U, // SMAXPv16i8
|
|
545362770U, // SMAXPv2i32
|
|
549557074U, // SMAXPv4i16
|
|
551654226U, // SMAXPv4i32
|
|
553751378U, // SMAXPv8i16
|
|
555848530U, // SMAXPv8i8
|
|
153950U, // SMAXV_VPZ_B
|
|
1646434654U, // SMAXV_VPZ_D
|
|
1648548190U, // SMAXV_VPZ_H
|
|
1638078814U, // SMAXV_VPZ_S
|
|
538990942U, // SMAXVv16i8v
|
|
538990942U, // SMAXVv4i16v
|
|
538990942U, // SMAXVv4i32v
|
|
538990942U, // SMAXVv8i16v
|
|
538990942U, // SMAXVv8i8v
|
|
3760233155U, // SMAX_ZI_B
|
|
2418072259U, // SMAX_ZI_D
|
|
2179013315U, // SMAX_ZI_H
|
|
4028717763U, // SMAX_ZI_S
|
|
3223362243U, // SMAX_ZPmZ_B
|
|
3223378627U, // SMAX_ZPmZ_D
|
|
3519093443U, // SMAX_ZPmZ_H
|
|
3223411395U, // SMAX_ZPmZ_S
|
|
543267523U, // SMAXv16i8
|
|
545364675U, // SMAXv2i32
|
|
549558979U, // SMAXv4i16
|
|
551656131U, // SMAXv4i32
|
|
553753283U, // SMAXv8i16
|
|
555850435U, // SMAXv8i8
|
|
264456U, // SMC
|
|
3223360256U, // SMINP_ZPmZ_B
|
|
3223376640U, // SMINP_ZPmZ_D
|
|
3519091456U, // SMINP_ZPmZ_H
|
|
3223409408U, // SMINP_ZPmZ_S
|
|
543265536U, // SMINPv16i8
|
|
545362688U, // SMINPv2i32
|
|
549556992U, // SMINPv4i16
|
|
551654144U, // SMINPv4i32
|
|
553751296U, // SMINPv8i16
|
|
555848448U, // SMINPv8i8
|
|
153898U, // SMINV_VPZ_B
|
|
1646434602U, // SMINV_VPZ_D
|
|
1648548138U, // SMINV_VPZ_H
|
|
1638078762U, // SMINV_VPZ_S
|
|
538990890U, // SMINVv16i8v
|
|
538990890U, // SMINVv4i16v
|
|
538990890U, // SMINVv4i32v
|
|
538990890U, // SMINVv8i16v
|
|
538990890U, // SMINVv8i8v
|
|
3760230810U, // SMIN_ZI_B
|
|
2418069914U, // SMIN_ZI_D
|
|
2179010970U, // SMIN_ZI_H
|
|
4028715418U, // SMIN_ZI_S
|
|
3223359898U, // SMIN_ZPmZ_B
|
|
3223376282U, // SMIN_ZPmZ_D
|
|
3519091098U, // SMIN_ZPmZ_H
|
|
3223409050U, // SMIN_ZPmZ_S
|
|
543265178U, // SMINv16i8
|
|
545362330U, // SMINv2i32
|
|
549556634U, // SMINv4i16
|
|
551653786U, // SMINv4i32
|
|
553750938U, // SMINv8i16
|
|
555848090U, // SMINv8i8
|
|
1344324924U, // SMLALB_ZZZI_D
|
|
2686534972U, // SMLALB_ZZZI_S
|
|
1344324924U, // SMLALB_ZZZ_D
|
|
2281768252U, // SMLALB_ZZZ_H
|
|
2686534972U, // SMLALB_ZZZ_S
|
|
1344329417U, // SMLALT_ZZZI_D
|
|
2686539465U, // SMLALT_ZZZI_S
|
|
1344329417U, // SMLALT_ZZZ_D
|
|
2281772745U, // SMLALT_ZZZ_H
|
|
2686539465U, // SMLALT_ZZZ_S
|
|
2969698502U, // SMLALv16i8_v8i16
|
|
2963410740U, // SMLALv2i32_indexed
|
|
2963410740U, // SMLALv2i32_v2i64
|
|
2967605044U, // SMLALv4i16_indexed
|
|
2967605044U, // SMLALv4i16_v4i32
|
|
2963407046U, // SMLALv4i32_indexed
|
|
2963407046U, // SMLALv4i32_v2i64
|
|
2967601350U, // SMLALv8i16_indexed
|
|
2967601350U, // SMLALv8i16_v4i32
|
|
2969702196U, // SMLALv8i8_v8i16
|
|
1344325221U, // SMLSLB_ZZZI_D
|
|
2686535269U, // SMLSLB_ZZZI_S
|
|
1344325221U, // SMLSLB_ZZZ_D
|
|
2281768549U, // SMLSLB_ZZZ_H
|
|
2686535269U, // SMLSLB_ZZZ_S
|
|
1344329591U, // SMLSLT_ZZZI_D
|
|
2686539639U, // SMLSLT_ZZZI_S
|
|
1344329591U, // SMLSLT_ZZZ_D
|
|
2281772919U, // SMLSLT_ZZZ_H
|
|
2686539639U, // SMLSLT_ZZZ_S
|
|
2969698634U, // SMLSLv16i8_v8i16
|
|
2963411142U, // SMLSLv2i32_indexed
|
|
2963411142U, // SMLSLv2i32_v2i64
|
|
2967605446U, // SMLSLv4i16_indexed
|
|
2967605446U, // SMLSLv4i16_v4i32
|
|
2963407178U, // SMLSLv4i32_indexed
|
|
2963407178U, // SMLSLv4i32_v2i64
|
|
2967601482U, // SMLSLv8i16_indexed
|
|
2967601482U, // SMLSLv8i16_v4i32
|
|
2969702598U, // SMLSLv8i8_v8i16
|
|
2967601896U, // SMMLA
|
|
1344357096U, // SMMLA_ZZZ
|
|
138527519U, // SMOPA_MPPZZ_D
|
|
140624671U, // SMOPA_MPPZZ_S
|
|
138532317U, // SMOPS_MPPZZ_D
|
|
140629469U, // SMOPS_MPPZZ_S
|
|
538990917U, // SMOVvi16to32
|
|
538990917U, // SMOVvi16to32_idx0
|
|
538990917U, // SMOVvi16to64
|
|
538990917U, // SMOVvi16to64_idx0
|
|
538990917U, // SMOVvi32to64
|
|
538990917U, // SMOVvi32to64_idx0
|
|
538990917U, // SMOVvi8to32
|
|
538990917U, // SMOVvi8to32_idx0
|
|
538990917U, // SMOVvi8to64
|
|
538990917U, // SMOVvi8to64_idx0
|
|
807423904U, // SMSUBLrrr
|
|
3223358780U, // SMULH_ZPmZ_B
|
|
3223375164U, // SMULH_ZPmZ_D
|
|
3519089980U, // SMULH_ZPmZ_H
|
|
3223407932U, // SMULH_ZPmZ_S
|
|
3760229692U, // SMULH_ZZZ_B
|
|
2418068796U, // SMULH_ZZZ_D
|
|
2179009852U, // SMULH_ZZZ_H
|
|
4028714300U, // SMULH_ZZZ_S
|
|
807423292U, // SMULHrr
|
|
4028679695U, // SMULLB_ZZZI_D
|
|
1881228815U, // SMULLB_ZZZI_S
|
|
4028679695U, // SMULLB_ZZZ_D
|
|
2273379855U, // SMULLB_ZZZ_H
|
|
1881228815U, // SMULLB_ZZZ_S
|
|
4028684103U, // SMULLT_ZZZI_D
|
|
1881233223U, // SMULLT_ZZZI_S
|
|
4028684103U, // SMULLT_ZZZ_D
|
|
2273384263U, // SMULLT_ZZZ_H
|
|
1881233223U, // SMULLT_ZZZ_S
|
|
553746728U, // SMULLv16i8_v8i16
|
|
547459174U, // SMULLv2i32_indexed
|
|
547459174U, // SMULLv2i32_v2i64
|
|
551653478U, // SMULLv4i16_indexed
|
|
551653478U, // SMULLv4i16_v4i32
|
|
547455272U, // SMULLv4i32_indexed
|
|
547455272U, // SMULLv4i32_v2i64
|
|
551649576U, // SMULLv8i16_indexed
|
|
551649576U, // SMULLv8i16_v4i32
|
|
553750630U, // SMULLv8i8_v8i16
|
|
3223358037U, // SPLICE_ZPZZ_B
|
|
3223374421U, // SPLICE_ZPZZ_D
|
|
2176911957U, // SPLICE_ZPZZ_H
|
|
3223407189U, // SPLICE_ZPZZ_S
|
|
3223358037U, // SPLICE_ZPZ_B
|
|
3223374421U, // SPLICE_ZPZ_D
|
|
2176911957U, // SPLICE_ZPZ_H
|
|
3223407189U, // SPLICE_ZPZ_S
|
|
2135336U, // SQABS_ZPmZ_B
|
|
2151720U, // SQABS_ZPmZ_D
|
|
272700712U, // SQABS_ZPmZ_H
|
|
2184488U, // SQABS_ZPmZ_S
|
|
543266088U, // SQABSv16i8
|
|
807425320U, // SQABSv1i16
|
|
807425320U, // SQABSv1i32
|
|
807425320U, // SQABSv1i64
|
|
807425320U, // SQABSv1i8
|
|
545363240U, // SQABSv2i32
|
|
547460392U, // SQABSv2i64
|
|
549557544U, // SQABSv4i16
|
|
551654696U, // SQABSv4i32
|
|
553751848U, // SQABSv8i16
|
|
555849000U, // SQABSv8i8
|
|
3760228869U, // SQADD_ZI_B
|
|
2418067973U, // SQADD_ZI_D
|
|
2179009029U, // SQADD_ZI_H
|
|
4028713477U, // SQADD_ZI_S
|
|
3223357957U, // SQADD_ZPmZ_B
|
|
3223374341U, // SQADD_ZPmZ_D
|
|
3519089157U, // SQADD_ZPmZ_H
|
|
3223407109U, // SQADD_ZPmZ_S
|
|
3760228869U, // SQADD_ZZZ_B
|
|
2418067973U, // SQADD_ZZZ_D
|
|
2179009029U, // SQADD_ZZZ_H
|
|
4028713477U, // SQADD_ZZZ_S
|
|
543263237U, // SQADDv16i8
|
|
807422469U, // SQADDv1i16
|
|
807422469U, // SQADDv1i32
|
|
807422469U, // SQADDv1i64
|
|
807422469U, // SQADDv1i8
|
|
545360389U, // SQADDv2i32
|
|
547457541U, // SQADDv2i64
|
|
549554693U, // SQADDv4i16
|
|
551651845U, // SQADDv4i32
|
|
553748997U, // SQADDv8i16
|
|
555846149U, // SQADDv8i8
|
|
3760228802U, // SQCADD_ZZI_B
|
|
2418067906U, // SQCADD_ZZI_D
|
|
2179008962U, // SQCADD_ZZI_H
|
|
4028713410U, // SQCADD_ZZI_S
|
|
2686469304U, // SQDECB_XPiI
|
|
807421112U, // SQDECB_XPiWdI
|
|
2686470555U, // SQDECD_XPiI
|
|
807422363U, // SQDECD_XPiWdI
|
|
2686503323U, // SQDECD_ZPiI
|
|
2686471241U, // SQDECH_XPiI
|
|
807423049U, // SQDECH_XPiWdI
|
|
39914569U, // SQDECH_ZPiI
|
|
3760214636U, // SQDECP_XPWd_B
|
|
2418037356U, // SQDECP_XPWd_D
|
|
1881166444U, // SQDECP_XPWd_H
|
|
4028650092U, // SQDECP_XPWd_S
|
|
3760214636U, // SQDECP_XP_B
|
|
2418037356U, // SQDECP_XP_D
|
|
1881166444U, // SQDECP_XP_H
|
|
4028650092U, // SQDECP_XP_S
|
|
1075892844U, // SQDECP_ZP_D
|
|
1648431724U, // SQDECP_ZP_H
|
|
1344361068U, // SQDECP_ZP_S
|
|
2686474715U, // SQDECW_XPiI
|
|
807426523U, // SQDECW_XPiWdI
|
|
2686540251U, // SQDECW_ZPiI
|
|
1344329266U, // SQDMLALBT_ZZZ_D
|
|
2281772594U, // SQDMLALBT_ZZZ_H
|
|
2686539314U, // SQDMLALBT_ZZZ_S
|
|
1344324905U, // SQDMLALB_ZZZI_D
|
|
2686534953U, // SQDMLALB_ZZZI_S
|
|
1344324905U, // SQDMLALB_ZZZ_D
|
|
2281768233U, // SQDMLALB_ZZZ_H
|
|
2686534953U, // SQDMLALB_ZZZ_S
|
|
1344329398U, // SQDMLALT_ZZZI_D
|
|
2686539446U, // SQDMLALT_ZZZI_S
|
|
1344329398U, // SQDMLALT_ZZZ_D
|
|
2281772726U, // SQDMLALT_ZZZ_H
|
|
2686539446U, // SQDMLALT_ZZZ_S
|
|
270749476U, // SQDMLALi16
|
|
270749476U, // SQDMLALi32
|
|
270749476U, // SQDMLALv1i32_indexed
|
|
270749476U, // SQDMLALv1i64_indexed
|
|
2963410724U, // SQDMLALv2i32_indexed
|
|
2963410724U, // SQDMLALv2i32_v2i64
|
|
2967605028U, // SQDMLALv4i16_indexed
|
|
2967605028U, // SQDMLALv4i16_v4i32
|
|
2963407028U, // SQDMLALv4i32_indexed
|
|
2963407028U, // SQDMLALv4i32_v2i64
|
|
2967601332U, // SQDMLALv8i16_indexed
|
|
2967601332U, // SQDMLALv8i16_v4i32
|
|
1344329295U, // SQDMLSLBT_ZZZ_D
|
|
2281772623U, // SQDMLSLBT_ZZZ_H
|
|
2686539343U, // SQDMLSLBT_ZZZ_S
|
|
1344325203U, // SQDMLSLB_ZZZI_D
|
|
2686535251U, // SQDMLSLB_ZZZI_S
|
|
1344325203U, // SQDMLSLB_ZZZ_D
|
|
2281768531U, // SQDMLSLB_ZZZ_H
|
|
2686535251U, // SQDMLSLB_ZZZ_S
|
|
1344329573U, // SQDMLSLT_ZZZI_D
|
|
2686539621U, // SQDMLSLT_ZZZI_S
|
|
1344329573U, // SQDMLSLT_ZZZ_D
|
|
2281772901U, // SQDMLSLT_ZZZ_H
|
|
2686539621U, // SQDMLSLT_ZZZ_S
|
|
270749878U, // SQDMLSLi16
|
|
270749878U, // SQDMLSLi32
|
|
270749878U, // SQDMLSLv1i32_indexed
|
|
270749878U, // SQDMLSLv1i64_indexed
|
|
2963411126U, // SQDMLSLv2i32_indexed
|
|
2963411126U, // SQDMLSLv2i32_v2i64
|
|
2967605430U, // SQDMLSLv4i16_indexed
|
|
2967605430U, // SQDMLSLv4i16_v4i32
|
|
2963407160U, // SQDMLSLv4i32_indexed
|
|
2963407160U, // SQDMLSLv4i32_v2i64
|
|
2967601464U, // SQDMLSLv8i16_indexed
|
|
2967601464U, // SQDMLSLv8i16_v4i32
|
|
2418068777U, // SQDMULH_ZZZI_D
|
|
2179009833U, // SQDMULH_ZZZI_H
|
|
4028714281U, // SQDMULH_ZZZI_S
|
|
3760229673U, // SQDMULH_ZZZ_B
|
|
2418068777U, // SQDMULH_ZZZ_D
|
|
2179009833U, // SQDMULH_ZZZ_H
|
|
4028714281U, // SQDMULH_ZZZ_S
|
|
807423273U, // SQDMULHv1i16
|
|
807423273U, // SQDMULHv1i16_indexed
|
|
807423273U, // SQDMULHv1i32
|
|
807423273U, // SQDMULHv1i32_indexed
|
|
545361193U, // SQDMULHv2i32
|
|
545361193U, // SQDMULHv2i32_indexed
|
|
549555497U, // SQDMULHv4i16
|
|
549555497U, // SQDMULHv4i16_indexed
|
|
551652649U, // SQDMULHv4i32
|
|
551652649U, // SQDMULHv4i32_indexed
|
|
553749801U, // SQDMULHv8i16
|
|
553749801U, // SQDMULHv8i16_indexed
|
|
4028679677U, // SQDMULLB_ZZZI_D
|
|
1881228797U, // SQDMULLB_ZZZI_S
|
|
4028679677U, // SQDMULLB_ZZZ_D
|
|
2273379837U, // SQDMULLB_ZZZ_H
|
|
1881228797U, // SQDMULLB_ZZZ_S
|
|
4028684085U, // SQDMULLT_ZZZI_D
|
|
1881233205U, // SQDMULLT_ZZZI_S
|
|
4028684085U, // SQDMULLT_ZZZ_D
|
|
2273384245U, // SQDMULLT_ZZZ_H
|
|
1881233205U, // SQDMULLT_ZZZ_S
|
|
807424086U, // SQDMULLi16
|
|
807424086U, // SQDMULLi32
|
|
807424086U, // SQDMULLv1i32_indexed
|
|
807424086U, // SQDMULLv1i64_indexed
|
|
547459158U, // SQDMULLv2i32_indexed
|
|
547459158U, // SQDMULLv2i32_v2i64
|
|
551653462U, // SQDMULLv4i16_indexed
|
|
551653462U, // SQDMULLv4i16_v4i32
|
|
547455254U, // SQDMULLv4i32_indexed
|
|
547455254U, // SQDMULLv4i32_v2i64
|
|
551649558U, // SQDMULLv8i16_indexed
|
|
551649558U, // SQDMULLv8i16_v4i32
|
|
2686469320U, // SQINCB_XPiI
|
|
807421128U, // SQINCB_XPiWdI
|
|
2686470571U, // SQINCD_XPiI
|
|
807422379U, // SQINCD_XPiWdI
|
|
2686503339U, // SQINCD_ZPiI
|
|
2686471257U, // SQINCH_XPiI
|
|
807423065U, // SQINCH_XPiWdI
|
|
39914585U, // SQINCH_ZPiI
|
|
3760214652U, // SQINCP_XPWd_B
|
|
2418037372U, // SQINCP_XPWd_D
|
|
1881166460U, // SQINCP_XPWd_H
|
|
4028650108U, // SQINCP_XPWd_S
|
|
3760214652U, // SQINCP_XP_B
|
|
2418037372U, // SQINCP_XP_D
|
|
1881166460U, // SQINCP_XP_H
|
|
4028650108U, // SQINCP_XP_S
|
|
1075892860U, // SQINCP_ZP_D
|
|
1648431740U, // SQINCP_ZP_H
|
|
1344361084U, // SQINCP_ZP_S
|
|
2686474731U, // SQINCW_XPiI
|
|
807426539U, // SQINCW_XPiWdI
|
|
2686540267U, // SQINCW_ZPiI
|
|
2132793U, // SQNEG_ZPmZ_B
|
|
2149177U, // SQNEG_ZPmZ_D
|
|
272698169U, // SQNEG_ZPmZ_H
|
|
2181945U, // SQNEG_ZPmZ_S
|
|
543263545U, // SQNEGv16i8
|
|
807422777U, // SQNEGv1i16
|
|
807422777U, // SQNEGv1i32
|
|
807422777U, // SQNEGv1i64
|
|
807422777U, // SQNEGv1i8
|
|
545360697U, // SQNEGv2i32
|
|
547457849U, // SQNEGv2i64
|
|
549555001U, // SQNEGv4i16
|
|
551652153U, // SQNEGv4i32
|
|
553749305U, // SQNEGv8i16
|
|
555846457U, // SQNEGv8i8
|
|
2185300954U, // SQRDCMLAH_ZZZI_H
|
|
1344359386U, // SQRDCMLAH_ZZZI_S
|
|
1344310234U, // SQRDCMLAH_ZZZ_B
|
|
1075891162U, // SQRDCMLAH_ZZZ_D
|
|
2185300954U, // SQRDCMLAH_ZZZ_H
|
|
1344359386U, // SQRDCMLAH_ZZZ_S
|
|
1075891173U, // SQRDMLAH_ZZZI_D
|
|
2185300965U, // SQRDMLAH_ZZZI_H
|
|
1344359397U, // SQRDMLAH_ZZZI_S
|
|
1344310245U, // SQRDMLAH_ZZZ_B
|
|
1075891173U, // SQRDMLAH_ZZZ_D
|
|
2185300965U, // SQRDMLAH_ZZZ_H
|
|
1344359397U, // SQRDMLAH_ZZZ_S
|
|
270748645U, // SQRDMLAHi16_indexed
|
|
270748645U, // SQRDMLAHi32_indexed
|
|
270748645U, // SQRDMLAHv1i16
|
|
270748645U, // SQRDMLAHv1i32
|
|
2961312741U, // SQRDMLAHv2i32
|
|
2961312741U, // SQRDMLAHv2i32_indexed
|
|
2965507045U, // SQRDMLAHv4i16
|
|
2965507045U, // SQRDMLAHv4i16_indexed
|
|
2967604197U, // SQRDMLAHv4i32
|
|
2967604197U, // SQRDMLAHv4i32_indexed
|
|
2969701349U, // SQRDMLAHv8i16
|
|
2969701349U, // SQRDMLAHv8i16_indexed
|
|
1075891778U, // SQRDMLSH_ZZZI_D
|
|
2185301570U, // SQRDMLSH_ZZZI_H
|
|
1344360002U, // SQRDMLSH_ZZZI_S
|
|
1344310850U, // SQRDMLSH_ZZZ_B
|
|
1075891778U, // SQRDMLSH_ZZZ_D
|
|
2185301570U, // SQRDMLSH_ZZZ_H
|
|
1344360002U, // SQRDMLSH_ZZZ_S
|
|
270749250U, // SQRDMLSHi16_indexed
|
|
270749250U, // SQRDMLSHi32_indexed
|
|
270749250U, // SQRDMLSHv1i16
|
|
270749250U, // SQRDMLSHv1i32
|
|
2961313346U, // SQRDMLSHv2i32
|
|
2961313346U, // SQRDMLSHv2i32_indexed
|
|
2965507650U, // SQRDMLSHv4i16
|
|
2965507650U, // SQRDMLSHv4i16_indexed
|
|
2967604802U, // SQRDMLSHv4i32
|
|
2967604802U, // SQRDMLSHv4i32_indexed
|
|
2969701954U, // SQRDMLSHv8i16
|
|
2969701954U, // SQRDMLSHv8i16_indexed
|
|
2418068786U, // SQRDMULH_ZZZI_D
|
|
2179009842U, // SQRDMULH_ZZZI_H
|
|
4028714290U, // SQRDMULH_ZZZI_S
|
|
3760229682U, // SQRDMULH_ZZZ_B
|
|
2418068786U, // SQRDMULH_ZZZ_D
|
|
2179009842U, // SQRDMULH_ZZZ_H
|
|
4028714290U, // SQRDMULH_ZZZ_S
|
|
807423282U, // SQRDMULHv1i16
|
|
807423282U, // SQRDMULHv1i16_indexed
|
|
807423282U, // SQRDMULHv1i32
|
|
807423282U, // SQRDMULHv1i32_indexed
|
|
545361202U, // SQRDMULHv2i32
|
|
545361202U, // SQRDMULHv2i32_indexed
|
|
549555506U, // SQRDMULHv4i16
|
|
549555506U, // SQRDMULHv4i16_indexed
|
|
551652658U, // SQRDMULHv4i32
|
|
551652658U, // SQRDMULHv4i32_indexed
|
|
553749810U, // SQRDMULHv8i16
|
|
553749810U, // SQRDMULHv8i16_indexed
|
|
3223360553U, // SQRSHLR_ZPmZ_B
|
|
3223376937U, // SQRSHLR_ZPmZ_D
|
|
3519091753U, // SQRSHLR_ZPmZ_H
|
|
3223409705U, // SQRSHLR_ZPmZ_S
|
|
3223359518U, // SQRSHL_ZPmZ_B
|
|
3223375902U, // SQRSHL_ZPmZ_D
|
|
3519090718U, // SQRSHL_ZPmZ_H
|
|
3223408670U, // SQRSHL_ZPmZ_S
|
|
543264798U, // SQRSHLv16i8
|
|
807424030U, // SQRSHLv1i16
|
|
807424030U, // SQRSHLv1i32
|
|
807424030U, // SQRSHLv1i64
|
|
807424030U, // SQRSHLv1i8
|
|
545361950U, // SQRSHLv2i32
|
|
547459102U, // SQRSHLv2i64
|
|
549556254U, // SQRSHLv4i16
|
|
551653406U, // SQRSHLv4i32
|
|
553750558U, // SQRSHLv8i16
|
|
555847710U, // SQRSHLv8i8
|
|
1881179853U, // SQRSHRNB_ZZI_B
|
|
2172716749U, // SQRSHRNB_ZZI_H
|
|
2418099917U, // SQRSHRNB_ZZI_S
|
|
2686490562U, // SQRSHRNT_ZZI_B
|
|
2174818242U, // SQRSHRNT_ZZI_H
|
|
1075926978U, // SQRSHRNT_ZZI_S
|
|
807424457U, // SQRSHRNb
|
|
807424457U, // SQRSHRNh
|
|
807424457U, // SQRSHRNs
|
|
2959212934U, // SQRSHRNv16i8_shift
|
|
545362377U, // SQRSHRNv2i32_shift
|
|
549556681U, // SQRSHRNv4i16_shift
|
|
2967601542U, // SQRSHRNv4i32_shift
|
|
2969698694U, // SQRSHRNv8i16_shift
|
|
555848137U, // SQRSHRNv8i8_shift
|
|
1881179899U, // SQRSHRUNB_ZZI_B
|
|
2172716795U, // SQRSHRUNB_ZZI_H
|
|
2418099963U, // SQRSHRUNB_ZZI_S
|
|
2686490617U, // SQRSHRUNT_ZZI_B
|
|
2174818297U, // SQRSHRUNT_ZZI_H
|
|
1075927033U, // SQRSHRUNT_ZZI_S
|
|
807424519U, // SQRSHRUNb
|
|
807424519U, // SQRSHRUNh
|
|
807424519U, // SQRSHRUNs
|
|
2959212995U, // SQRSHRUNv16i8_shift
|
|
545362439U, // SQRSHRUNv2i32_shift
|
|
549556743U, // SQRSHRUNv4i16_shift
|
|
2967601603U, // SQRSHRUNv4i32_shift
|
|
2969698755U, // SQRSHRUNv8i16_shift
|
|
555848199U, // SQRSHRUNv8i8_shift
|
|
3223360537U, // SQSHLR_ZPmZ_B
|
|
3223376921U, // SQSHLR_ZPmZ_D
|
|
3519091737U, // SQSHLR_ZPmZ_H
|
|
3223409689U, // SQSHLR_ZPmZ_S
|
|
3223361695U, // SQSHLU_ZPmI_B
|
|
3223378079U, // SQSHLU_ZPmI_D
|
|
3519092895U, // SQSHLU_ZPmI_H
|
|
3223410847U, // SQSHLU_ZPmI_S
|
|
807426207U, // SQSHLUb
|
|
807426207U, // SQSHLUd
|
|
807426207U, // SQSHLUh
|
|
807426207U, // SQSHLUs
|
|
543266975U, // SQSHLUv16i8_shift
|
|
545364127U, // SQSHLUv2i32_shift
|
|
547461279U, // SQSHLUv2i64_shift
|
|
549558431U, // SQSHLUv4i16_shift
|
|
551655583U, // SQSHLUv4i32_shift
|
|
553752735U, // SQSHLUv8i16_shift
|
|
555849887U, // SQSHLUv8i8_shift
|
|
3223359504U, // SQSHL_ZPmI_B
|
|
3223375888U, // SQSHL_ZPmI_D
|
|
3519090704U, // SQSHL_ZPmI_H
|
|
3223408656U, // SQSHL_ZPmI_S
|
|
3223359504U, // SQSHL_ZPmZ_B
|
|
3223375888U, // SQSHL_ZPmZ_D
|
|
3519090704U, // SQSHL_ZPmZ_H
|
|
3223408656U, // SQSHL_ZPmZ_S
|
|
807424016U, // SQSHLb
|
|
807424016U, // SQSHLd
|
|
807424016U, // SQSHLh
|
|
807424016U, // SQSHLs
|
|
543264784U, // SQSHLv16i8
|
|
543264784U, // SQSHLv16i8_shift
|
|
807424016U, // SQSHLv1i16
|
|
807424016U, // SQSHLv1i32
|
|
807424016U, // SQSHLv1i64
|
|
807424016U, // SQSHLv1i8
|
|
545361936U, // SQSHLv2i32
|
|
545361936U, // SQSHLv2i32_shift
|
|
547459088U, // SQSHLv2i64
|
|
547459088U, // SQSHLv2i64_shift
|
|
549556240U, // SQSHLv4i16
|
|
549556240U, // SQSHLv4i16_shift
|
|
551653392U, // SQSHLv4i32
|
|
551653392U, // SQSHLv4i32_shift
|
|
553750544U, // SQSHLv8i16
|
|
553750544U, // SQSHLv8i16_shift
|
|
555847696U, // SQSHLv8i8
|
|
555847696U, // SQSHLv8i8_shift
|
|
1881179835U, // SQSHRNB_ZZI_B
|
|
2172716731U, // SQSHRNB_ZZI_H
|
|
2418099899U, // SQSHRNB_ZZI_S
|
|
2686490544U, // SQSHRNT_ZZI_B
|
|
2174818224U, // SQSHRNT_ZZI_H
|
|
1075926960U, // SQSHRNT_ZZI_S
|
|
807424441U, // SQSHRNb
|
|
807424441U, // SQSHRNh
|
|
807424441U, // SQSHRNs
|
|
2959212916U, // SQSHRNv16i8_shift
|
|
545362361U, // SQSHRNv2i32_shift
|
|
549556665U, // SQSHRNv4i16_shift
|
|
2967601524U, // SQSHRNv4i32_shift
|
|
2969698676U, // SQSHRNv8i16_shift
|
|
555848121U, // SQSHRNv8i8_shift
|
|
1881179889U, // SQSHRUNB_ZZI_B
|
|
2172716785U, // SQSHRUNB_ZZI_H
|
|
2418099953U, // SQSHRUNB_ZZI_S
|
|
2686490607U, // SQSHRUNT_ZZI_B
|
|
2174818287U, // SQSHRUNT_ZZI_H
|
|
1075927023U, // SQSHRUNT_ZZI_S
|
|
807424510U, // SQSHRUNb
|
|
807424510U, // SQSHRUNh
|
|
807424510U, // SQSHRUNs
|
|
2959212985U, // SQSHRUNv16i8_shift
|
|
545362430U, // SQSHRUNv2i32_shift
|
|
549556734U, // SQSHRUNv4i16_shift
|
|
2967601593U, // SQSHRUNv4i32_shift
|
|
2969698745U, // SQSHRUNv8i16_shift
|
|
555848190U, // SQSHRUNv8i8_shift
|
|
3223360459U, // SQSUBR_ZPmZ_B
|
|
3223376843U, // SQSUBR_ZPmZ_D
|
|
3519091659U, // SQSUBR_ZPmZ_H
|
|
3223409611U, // SQSUBR_ZPmZ_S
|
|
3760228482U, // SQSUB_ZI_B
|
|
2418067586U, // SQSUB_ZI_D
|
|
2179008642U, // SQSUB_ZI_H
|
|
4028713090U, // SQSUB_ZI_S
|
|
3223357570U, // SQSUB_ZPmZ_B
|
|
3223373954U, // SQSUB_ZPmZ_D
|
|
3519088770U, // SQSUB_ZPmZ_H
|
|
3223406722U, // SQSUB_ZPmZ_S
|
|
3760228482U, // SQSUB_ZZZ_B
|
|
2418067586U, // SQSUB_ZZZ_D
|
|
2179008642U, // SQSUB_ZZZ_H
|
|
4028713090U, // SQSUB_ZZZ_S
|
|
543262850U, // SQSUBv16i8
|
|
807422082U, // SQSUBv1i16
|
|
807422082U, // SQSUBv1i32
|
|
807422082U, // SQSUBv1i64
|
|
807422082U, // SQSUBv1i8
|
|
545360002U, // SQSUBv2i32
|
|
547457154U, // SQSUBv2i64
|
|
549554306U, // SQSUBv4i16
|
|
551651458U, // SQSUBv4i32
|
|
553748610U, // SQSUBv8i16
|
|
555845762U, // SQSUBv8i8
|
|
1881179873U, // SQXTNB_ZZ_B
|
|
1635845857U, // SQXTNB_ZZ_H
|
|
2418099937U, // SQXTNB_ZZ_S
|
|
2686490591U, // SQXTNT_ZZ_B
|
|
1637947359U, // SQXTNT_ZZ_H
|
|
1075927007U, // SQXTNT_ZZ_S
|
|
2959212969U, // SQXTNv16i8
|
|
807424496U, // SQXTNv1i16
|
|
807424496U, // SQXTNv1i32
|
|
807424496U, // SQXTNv1i8
|
|
545362416U, // SQXTNv2i32
|
|
549556720U, // SQXTNv4i16
|
|
2967601577U, // SQXTNv4i32
|
|
2969698729U, // SQXTNv8i16
|
|
555848176U, // SQXTNv8i8
|
|
1881179910U, // SQXTUNB_ZZ_B
|
|
1635845894U, // SQXTUNB_ZZ_H
|
|
2418099974U, // SQXTUNB_ZZ_S
|
|
2686490628U, // SQXTUNT_ZZ_B
|
|
1637947396U, // SQXTUNT_ZZ_H
|
|
1075927044U, // SQXTUNT_ZZ_S
|
|
2959213006U, // SQXTUNv16i8
|
|
807424529U, // SQXTUNv1i16
|
|
807424529U, // SQXTUNv1i32
|
|
807424529U, // SQXTUNv1i8
|
|
545362449U, // SQXTUNv2i32
|
|
549556753U, // SQXTUNv4i16
|
|
2967601614U, // SQXTUNv4i32
|
|
2969698766U, // SQXTUNv8i16
|
|
555848209U, // SQXTUNv8i8
|
|
3223357911U, // SRHADD_ZPmZ_B
|
|
3223374295U, // SRHADD_ZPmZ_D
|
|
3519089111U, // SRHADD_ZPmZ_H
|
|
3223407063U, // SRHADD_ZPmZ_S
|
|
543263191U, // SRHADDv16i8
|
|
545360343U, // SRHADDv2i32
|
|
549554647U, // SRHADDv4i16
|
|
551651799U, // SRHADDv4i32
|
|
553748951U, // SRHADDv8i16
|
|
555846103U, // SRHADDv8i8
|
|
1344311023U, // SRI_ZZI_B
|
|
1075891951U, // SRI_ZZI_D
|
|
2185301743U, // SRI_ZZI_H
|
|
1344360175U, // SRI_ZZI_S
|
|
270749423U, // SRId
|
|
2959216367U, // SRIv16i8_shift
|
|
2961313519U, // SRIv2i32_shift
|
|
2963410671U, // SRIv2i64_shift
|
|
2965507823U, // SRIv4i16_shift
|
|
2967604975U, // SRIv4i32_shift
|
|
2969702127U, // SRIv8i16_shift
|
|
2971799279U, // SRIv8i8_shift
|
|
3223360571U, // SRSHLR_ZPmZ_B
|
|
3223376955U, // SRSHLR_ZPmZ_D
|
|
3519091771U, // SRSHLR_ZPmZ_H
|
|
3223409723U, // SRSHLR_ZPmZ_S
|
|
3223359534U, // SRSHL_ZPmZ_B
|
|
3223375918U, // SRSHL_ZPmZ_D
|
|
3519090734U, // SRSHL_ZPmZ_H
|
|
3223408686U, // SRSHL_ZPmZ_S
|
|
543264814U, // SRSHLv16i8
|
|
807424046U, // SRSHLv1i64
|
|
545361966U, // SRSHLv2i32
|
|
547459118U, // SRSHLv2i64
|
|
549556270U, // SRSHLv4i16
|
|
551653422U, // SRSHLv4i32
|
|
553750574U, // SRSHLv8i16
|
|
555847726U, // SRSHLv8i8
|
|
3223360499U, // SRSHR_ZPmI_B
|
|
3223376883U, // SRSHR_ZPmI_D
|
|
3519091699U, // SRSHR_ZPmI_H
|
|
3223409651U, // SRSHR_ZPmI_S
|
|
807425011U, // SRSHRd
|
|
543265779U, // SRSHRv16i8_shift
|
|
545362931U, // SRSHRv2i32_shift
|
|
547460083U, // SRSHRv2i64_shift
|
|
549557235U, // SRSHRv4i16_shift
|
|
551654387U, // SRSHRv4i32_shift
|
|
553751539U, // SRSHRv8i16_shift
|
|
555848691U, // SRSHRv8i8_shift
|
|
1344308050U, // SRSRA_ZZI_B
|
|
1075888978U, // SRSRA_ZZI_D
|
|
2185298770U, // SRSRA_ZZI_H
|
|
1344357202U, // SRSRA_ZZI_S
|
|
270746450U, // SRSRAd
|
|
2959213394U, // SRSRAv16i8_shift
|
|
2961310546U, // SRSRAv2i32_shift
|
|
2963407698U, // SRSRAv2i64_shift
|
|
2965504850U, // SRSRAv4i16_shift
|
|
2967602002U, // SRSRAv4i32_shift
|
|
2969699154U, // SRSRAv8i16_shift
|
|
2971796306U, // SRSRAv8i8_shift
|
|
4028679661U, // SSHLLB_ZZI_D
|
|
2273379821U, // SSHLLB_ZZI_H
|
|
1881228781U, // SSHLLB_ZZI_S
|
|
4028684069U, // SSHLLT_ZZI_D
|
|
2273384229U, // SSHLLT_ZZI_H
|
|
1881233189U, // SSHLLT_ZZI_S
|
|
553746694U, // SSHLLv16i8_shift
|
|
547459144U, // SSHLLv2i32_shift
|
|
551653448U, // SSHLLv4i16_shift
|
|
547455238U, // SSHLLv4i32_shift
|
|
551649542U, // SSHLLv8i16_shift
|
|
553750600U, // SSHLLv8i8_shift
|
|
543264828U, // SSHLv16i8
|
|
807424060U, // SSHLv1i64
|
|
545361980U, // SSHLv2i32
|
|
547459132U, // SSHLv2i64
|
|
549556284U, // SSHLv4i16
|
|
551653436U, // SSHLv4i32
|
|
553750588U, // SSHLv8i16
|
|
555847740U, // SSHLv8i8
|
|
807425025U, // SSHRd
|
|
543265793U, // SSHRv16i8_shift
|
|
545362945U, // SSHRv2i32_shift
|
|
547460097U, // SSHRv2i64_shift
|
|
549557249U, // SSHRv4i16_shift
|
|
551654401U, // SSHRv4i32_shift
|
|
553751553U, // SSHRv8i16_shift
|
|
555848705U, // SSHRv8i8_shift
|
|
1344308064U, // SSRA_ZZI_B
|
|
1075888992U, // SSRA_ZZI_D
|
|
2185298784U, // SSRA_ZZI_H
|
|
1344357216U, // SSRA_ZZI_S
|
|
270746464U, // SSRAd
|
|
2959213408U, // SSRAv16i8_shift
|
|
2961310560U, // SSRAv2i32_shift
|
|
2963407712U, // SSRAv2i64_shift
|
|
2965504864U, // SSRAv4i16_shift
|
|
2967602016U, // SSRAv4i32_shift
|
|
2969699168U, // SSRAv8i16_shift
|
|
2971796320U, // SSRAv8i8_shift
|
|
1107674095U, // SST1B_D_IMM
|
|
302367727U, // SST1B_D_REAL
|
|
302367727U, // SST1B_D_SXTW
|
|
302367727U, // SST1B_D_UXTW
|
|
1376125935U, // SST1B_S_IMM
|
|
302384111U, // SST1B_S_SXTW
|
|
302384111U, // SST1B_S_UXTW
|
|
1107675460U, // SST1D_IMM
|
|
302369092U, // SST1D_REAL
|
|
302369092U, // SST1D_SCALED_SCALED_REAL
|
|
302369092U, // SST1D_SXTW
|
|
302369092U, // SST1D_SXTW_SCALED
|
|
302369092U, // SST1D_UXTW
|
|
302369092U, // SST1D_UXTW_SCALED
|
|
1107676045U, // SST1H_D_IMM
|
|
302369677U, // SST1H_D_REAL
|
|
302369677U, // SST1H_D_SCALED_SCALED_REAL
|
|
302369677U, // SST1H_D_SXTW
|
|
302369677U, // SST1H_D_SXTW_SCALED
|
|
302369677U, // SST1H_D_UXTW
|
|
302369677U, // SST1H_D_UXTW_SCALED
|
|
1376127885U, // SST1H_S_IMM
|
|
302386061U, // SST1H_S_SXTW
|
|
302386061U, // SST1H_S_SXTW_SCALED
|
|
302386061U, // SST1H_S_UXTW
|
|
302386061U, // SST1H_S_UXTW_SCALED
|
|
1107679634U, // SST1W_D_IMM
|
|
302373266U, // SST1W_D_REAL
|
|
302373266U, // SST1W_D_SCALED_SCALED_REAL
|
|
302373266U, // SST1W_D_SXTW
|
|
302373266U, // SST1W_D_SXTW_SCALED
|
|
302373266U, // SST1W_D_UXTW
|
|
302373266U, // SST1W_D_UXTW_SCALED
|
|
1376131474U, // SST1W_IMM
|
|
302389650U, // SST1W_SXTW
|
|
302389650U, // SST1W_SXTW_SCALED
|
|
302389650U, // SST1W_UXTW
|
|
302389650U, // SST1W_UXTW_SCALED
|
|
4028683837U, // SSUBLBT_ZZZ_D
|
|
2273383997U, // SSUBLBT_ZZZ_H
|
|
1881232957U, // SSUBLBT_ZZZ_S
|
|
4028679590U, // SSUBLB_ZZZ_D
|
|
2273379750U, // SSUBLB_ZZZ_H
|
|
1881228710U, // SSUBLB_ZZZ_S
|
|
4028680245U, // SSUBLTB_ZZZ_D
|
|
2273380405U, // SSUBLTB_ZZZ_H
|
|
1881229365U, // SSUBLTB_ZZZ_S
|
|
4028683993U, // SSUBLT_ZZZ_D
|
|
2273384153U, // SSUBLT_ZZZ_H
|
|
1881233113U, // SSUBLT_ZZZ_S
|
|
553746646U, // SSUBLv16i8_v8i16
|
|
547458992U, // SSUBLv2i32_v2i64
|
|
551653296U, // SSUBLv4i16_v4i32
|
|
547455190U, // SSUBLv4i32_v2i64
|
|
551649494U, // SSUBLv8i16_v4i32
|
|
553750448U, // SSUBLv8i8_v8i16
|
|
2418067606U, // SSUBWB_ZZZ_D
|
|
2179008662U, // SSUBWB_ZZZ_H
|
|
4028713110U, // SSUBWB_ZZZ_S
|
|
2418071658U, // SSUBWT_ZZZ_D
|
|
2179012714U, // SSUBWT_ZZZ_H
|
|
4028717162U, // SSUBWT_ZZZ_S
|
|
553746936U, // SSUBWv16i8_v8i16
|
|
547461572U, // SSUBWv2i32_v2i64
|
|
551655876U, // SSUBWv4i16_v4i32
|
|
547455480U, // SSUBWv4i32_v2i64
|
|
551649784U, // SSUBWv8i16_v4i32
|
|
553753028U, // SSUBWv8i8_v8i16
|
|
302449647U, // ST1B
|
|
302367727U, // ST1B_D
|
|
302367727U, // ST1B_D_IMM
|
|
302466031U, // ST1B_H
|
|
302466031U, // ST1B_H_IMM
|
|
302449647U, // ST1B_IMM
|
|
302384111U, // ST1B_S
|
|
302384111U, // ST1B_S_IMM
|
|
302369092U, // ST1D
|
|
302369092U, // ST1D_IMM
|
|
491599U, // ST1Fourv16b
|
|
76005455U, // ST1Fourv16b_POST
|
|
524367U, // ST1Fourv1d
|
|
78135375U, // ST1Fourv1d_POST
|
|
557135U, // ST1Fourv2d
|
|
76070991U, // ST1Fourv2d_POST
|
|
589903U, // ST1Fourv2s
|
|
78200911U, // ST1Fourv2s_POST
|
|
622671U, // ST1Fourv4h
|
|
78233679U, // ST1Fourv4h_POST
|
|
655439U, // ST1Fourv4s
|
|
76169295U, // ST1Fourv4s_POST
|
|
688207U, // ST1Fourv8b
|
|
78299215U, // ST1Fourv8b_POST
|
|
720975U, // ST1Fourv8h
|
|
76234831U, // ST1Fourv8h_POST
|
|
302467981U, // ST1H
|
|
302369677U, // ST1H_D
|
|
302369677U, // ST1H_D_IMM
|
|
302467981U, // ST1H_IMM
|
|
302386061U, // ST1H_S
|
|
302386061U, // ST1H_S_IMM
|
|
491599U, // ST1Onev16b
|
|
80199759U, // ST1Onev16b_POST
|
|
524367U, // ST1Onev1d
|
|
82329679U, // ST1Onev1d_POST
|
|
557135U, // ST1Onev2d
|
|
80265295U, // ST1Onev2d_POST
|
|
589903U, // ST1Onev2s
|
|
82395215U, // ST1Onev2s_POST
|
|
622671U, // ST1Onev4h
|
|
82427983U, // ST1Onev4h_POST
|
|
655439U, // ST1Onev4s
|
|
80363599U, // ST1Onev4s_POST
|
|
688207U, // ST1Onev8b
|
|
82493519U, // ST1Onev8b_POST
|
|
720975U, // ST1Onev8h
|
|
80429135U, // ST1Onev8h_POST
|
|
491599U, // ST1Threev16b
|
|
90685519U, // ST1Threev16b_POST
|
|
524367U, // ST1Threev1d
|
|
92815439U, // ST1Threev1d_POST
|
|
557135U, // ST1Threev2d
|
|
90751055U, // ST1Threev2d_POST
|
|
589903U, // ST1Threev2s
|
|
92880975U, // ST1Threev2s_POST
|
|
622671U, // ST1Threev4h
|
|
92913743U, // ST1Threev4h_POST
|
|
655439U, // ST1Threev4s
|
|
90849359U, // ST1Threev4s_POST
|
|
688207U, // ST1Threev8b
|
|
92979279U, // ST1Threev8b_POST
|
|
720975U, // ST1Threev8h
|
|
90914895U, // ST1Threev8h_POST
|
|
491599U, // ST1Twov16b
|
|
78102607U, // ST1Twov16b_POST
|
|
524367U, // ST1Twov1d
|
|
80232527U, // ST1Twov1d_POST
|
|
557135U, // ST1Twov2d
|
|
78168143U, // ST1Twov2d_POST
|
|
589903U, // ST1Twov2s
|
|
80298063U, // ST1Twov2s_POST
|
|
622671U, // ST1Twov4h
|
|
80330831U, // ST1Twov4h_POST
|
|
655439U, // ST1Twov4s
|
|
78266447U, // ST1Twov4s_POST
|
|
688207U, // ST1Twov8b
|
|
80396367U, // ST1Twov8b_POST
|
|
720975U, // ST1Twov8h
|
|
78331983U, // ST1Twov8h_POST
|
|
302389650U, // ST1W
|
|
302373266U, // ST1W_D
|
|
302373266U, // ST1W_D_IMM
|
|
302389650U, // ST1W_IMM
|
|
1168548339U, // ST1_MXIPXX_H_B
|
|
1168548353U, // ST1_MXIPXX_H_D
|
|
1168548367U, // ST1_MXIPXX_H_H
|
|
1168548381U, // ST1_MXIPXX_H_Q
|
|
1168548395U, // ST1_MXIPXX_H_S
|
|
1168564723U, // ST1_MXIPXX_V_B
|
|
1168564737U, // ST1_MXIPXX_V_D
|
|
1168564751U, // ST1_MXIPXX_V_H
|
|
1168564765U, // ST1_MXIPXX_V_Q
|
|
1168564779U, // ST1_MXIPXX_V_S
|
|
1032271U, // ST1i16
|
|
1407942735U, // ST1i16_POST
|
|
1048655U, // ST1i32
|
|
1676410959U, // ST1i32_POST
|
|
1065039U, // ST1i64
|
|
1944879183U, // ST1i64_POST
|
|
1081423U, // ST1i8
|
|
2213347407U, // ST1i8_POST
|
|
302449676U, // ST2B
|
|
302449676U, // ST2B_IMM
|
|
302369104U, // ST2D
|
|
302369104U, // ST2D_IMM
|
|
838880021U, // ST2GOffset
|
|
302205717U, // ST2GPostIndex
|
|
302205717U, // ST2GPreIndex
|
|
302468010U, // ST2H
|
|
302468010U, // ST2H_IMM
|
|
492019U, // ST2Twov16b
|
|
78103027U, // ST2Twov16b_POST
|
|
557555U, // ST2Twov2d
|
|
78168563U, // ST2Twov2d_POST
|
|
590323U, // ST2Twov2s
|
|
80298483U, // ST2Twov2s_POST
|
|
623091U, // ST2Twov4h
|
|
80331251U, // ST2Twov4h_POST
|
|
655859U, // ST2Twov4s
|
|
78266867U, // ST2Twov4s_POST
|
|
688627U, // ST2Twov8b
|
|
80396787U, // ST2Twov8b_POST
|
|
721395U, // ST2Twov8h
|
|
78332403U, // ST2Twov8h_POST
|
|
302389670U, // ST2W
|
|
302389670U, // ST2W_IMM
|
|
1032691U, // ST2i16
|
|
1676378611U, // ST2i16_POST
|
|
1049075U, // ST2i32
|
|
1944846835U, // ST2i32_POST
|
|
1065459U, // ST2i64
|
|
2481750515U, // ST2i64_POST
|
|
1081843U, // ST2i8
|
|
1408041459U, // ST2i8_POST
|
|
302449697U, // ST3B
|
|
302449697U, // ST3B_IMM
|
|
302369116U, // ST3D
|
|
302369116U, // ST3D_IMM
|
|
302468022U, // ST3H
|
|
302468022U, // ST3H_IMM
|
|
492085U, // ST3Threev16b
|
|
90686005U, // ST3Threev16b_POST
|
|
557621U, // ST3Threev2d
|
|
90751541U, // ST3Threev2d_POST
|
|
590389U, // ST3Threev2s
|
|
92881461U, // ST3Threev2s_POST
|
|
623157U, // ST3Threev4h
|
|
92914229U, // ST3Threev4h_POST
|
|
655925U, // ST3Threev4s
|
|
90849845U, // ST3Threev4s_POST
|
|
688693U, // ST3Threev8b
|
|
92979765U, // ST3Threev8b_POST
|
|
721461U, // ST3Threev8h
|
|
90915381U, // ST3Threev8h_POST
|
|
302389682U, // ST3W
|
|
302389682U, // ST3W_IMM
|
|
1032757U, // ST3i16
|
|
2750120501U, // ST3i16_POST
|
|
1049141U, // ST3i32
|
|
3018588725U, // ST3i32_POST
|
|
1065525U, // ST3i64
|
|
3287056949U, // ST3i64_POST
|
|
1081909U, // ST3i8
|
|
3555525173U, // ST3i8_POST
|
|
302449723U, // ST4B
|
|
302449723U, // ST4B_IMM
|
|
302369128U, // ST4D
|
|
302369128U, // ST4D_IMM
|
|
492102U, // ST4Fourv16b
|
|
76005958U, // ST4Fourv16b_POST
|
|
557638U, // ST4Fourv2d
|
|
76071494U, // ST4Fourv2d_POST
|
|
590406U, // ST4Fourv2s
|
|
78201414U, // ST4Fourv2s_POST
|
|
623174U, // ST4Fourv4h
|
|
78234182U, // ST4Fourv4h_POST
|
|
655942U, // ST4Fourv4s
|
|
76169798U, // ST4Fourv4s_POST
|
|
688710U, // ST4Fourv8b
|
|
78299718U, // ST4Fourv8b_POST
|
|
721478U, // ST4Fourv8h
|
|
76235334U, // ST4Fourv8h_POST
|
|
302468034U, // ST4H
|
|
302468034U, // ST4H_IMM
|
|
302389694U, // ST4W
|
|
302389694U, // ST4W_IMM
|
|
1032774U, // ST4i16
|
|
1944814150U, // ST4i16_POST
|
|
1049158U, // ST4i32
|
|
2481717830U, // ST4i32_POST
|
|
1065542U, // ST4i64
|
|
3823927878U, // ST4i64_POST
|
|
1081926U, // ST4i8
|
|
1676476998U, // ST4i8_POST
|
|
885806U, // ST64B
|
|
4028651719U, // ST64BV
|
|
4028645408U, // ST64BV0
|
|
838881602U, // STGM
|
|
838880085U, // STGOffset
|
|
807424670U, // STGPi
|
|
302205781U, // STGPostIndex
|
|
270750366U, // STGPpost
|
|
270750366U, // STGPpre
|
|
302205781U, // STGPreIndex
|
|
838879056U, // STLLRB
|
|
838880682U, // STLLRH
|
|
838882379U, // STLLRW
|
|
838882379U, // STLLRX
|
|
838879064U, // STLRB
|
|
838880690U, // STLRH
|
|
838882392U, // STLRW
|
|
838882392U, // STLRX
|
|
838879114U, // STLURBi
|
|
838880740U, // STLURHi
|
|
838882489U, // STLURWi
|
|
838882489U, // STLURXi
|
|
807424870U, // STLXPW
|
|
807424870U, // STLXPX
|
|
807421873U, // STLXRB
|
|
807423499U, // STLXRH
|
|
807425273U, // STLXRW
|
|
807425273U, // STLXRX
|
|
807424782U, // STNPDi
|
|
807424782U, // STNPQi
|
|
807424782U, // STNPSi
|
|
807424782U, // STNPWi
|
|
807424782U, // STNPXi
|
|
302449639U, // STNT1B_ZRI
|
|
302449639U, // STNT1B_ZRR
|
|
1107674087U, // STNT1B_ZZR_D_REAL
|
|
1376125927U, // STNT1B_ZZR_S_REAL
|
|
302369084U, // STNT1D_ZRI
|
|
302369084U, // STNT1D_ZRR
|
|
1107675452U, // STNT1D_ZZR_D_REAL
|
|
302467973U, // STNT1H_ZRI
|
|
302467973U, // STNT1H_ZRR
|
|
1107676037U, // STNT1H_ZZR_D_REAL
|
|
1376127877U, // STNT1H_ZZR_S_REAL
|
|
302389642U, // STNT1W_ZRI
|
|
302389642U, // STNT1W_ZRR
|
|
1107679626U, // STNT1W_ZZR_D_REAL
|
|
1376131466U, // STNT1W_ZZR_S_REAL
|
|
807424820U, // STPDi
|
|
270750516U, // STPDpost
|
|
270750516U, // STPDpre
|
|
807424820U, // STPQi
|
|
270750516U, // STPQpost
|
|
270750516U, // STPQpre
|
|
807424820U, // STPSi
|
|
270750516U, // STPSpost
|
|
270750516U, // STPSpre
|
|
807424820U, // STPWi
|
|
270750516U, // STPWpost
|
|
270750516U, // STPWpre
|
|
807424820U, // STPXi
|
|
270750516U, // STPXpost
|
|
270750516U, // STPXpre
|
|
302204790U, // STRBBpost
|
|
302204790U, // STRBBpre
|
|
838879094U, // STRBBroW
|
|
838879094U, // STRBBroX
|
|
838879094U, // STRBBui
|
|
302208162U, // STRBpost
|
|
302208162U, // STRBpre
|
|
838882466U, // STRBroW
|
|
838882466U, // STRBroX
|
|
838882466U, // STRBui
|
|
302208162U, // STRDpost
|
|
302208162U, // STRDpre
|
|
838882466U, // STRDroW
|
|
838882466U, // STRDroX
|
|
838882466U, // STRDui
|
|
302206416U, // STRHHpost
|
|
302206416U, // STRHHpre
|
|
838880720U, // STRHHroW
|
|
838880720U, // STRHHroX
|
|
838880720U, // STRHHui
|
|
302208162U, // STRHpost
|
|
302208162U, // STRHpre
|
|
838882466U, // STRHroW
|
|
838882466U, // STRHroX
|
|
838882466U, // STRHui
|
|
302208162U, // STRQpost
|
|
302208162U, // STRQpre
|
|
838882466U, // STRQroW
|
|
838882466U, // STRQroX
|
|
838882466U, // STRQui
|
|
302208162U, // STRSpost
|
|
302208162U, // STRSpre
|
|
838882466U, // STRSroW
|
|
838882466U, // STRSroX
|
|
838882466U, // STRSui
|
|
302208162U, // STRWpost
|
|
302208162U, // STRWpre
|
|
838882466U, // STRWroW
|
|
838882466U, // STRWroX
|
|
838882466U, // STRWui
|
|
302208162U, // STRXpost
|
|
302208162U, // STRXpre
|
|
838882466U, // STRXroW
|
|
838882466U, // STRXroX
|
|
838882466U, // STRXui
|
|
839767202U, // STR_PXI
|
|
922786U, // STR_ZA
|
|
839767202U, // STR_ZXI
|
|
838879100U, // STTRBi
|
|
838880726U, // STTRHi
|
|
838882471U, // STTRWi
|
|
838882471U, // STTRXi
|
|
838879131U, // STURBBi
|
|
838882504U, // STURBi
|
|
838882504U, // STURDi
|
|
838880757U, // STURHHi
|
|
838882504U, // STURHi
|
|
838882504U, // STURQi
|
|
838882504U, // STURSi
|
|
838882504U, // STURWi
|
|
838882504U, // STURXi
|
|
807424877U, // STXPW
|
|
807424877U, // STXPX
|
|
807421881U, // STXRB
|
|
807423507U, // STXRH
|
|
807425280U, // STXRW
|
|
807425280U, // STXRX
|
|
838880027U, // STZ2GOffset
|
|
302205723U, // STZ2GPostIndex
|
|
302205723U, // STZ2GPreIndex
|
|
838881608U, // STZGM
|
|
838880090U, // STZGOffset
|
|
302205786U, // STZGPostIndex
|
|
302205786U, // STZGPreIndex
|
|
807422754U, // SUBG
|
|
1881179800U, // SUBHNB_ZZZ_B
|
|
2172716696U, // SUBHNB_ZZZ_H
|
|
2418099864U, // SUBHNB_ZZZ_S
|
|
2686490521U, // SUBHNT_ZZZ_B
|
|
2174818201U, // SUBHNT_ZZZ_H
|
|
1075926937U, // SUBHNT_ZZZ_S
|
|
545362307U, // SUBHNv2i64_v2i32
|
|
2967601507U, // SUBHNv2i64_v4i32
|
|
549556611U, // SUBHNv4i32_v4i16
|
|
2969698659U, // SUBHNv4i32_v8i16
|
|
2959212899U, // SUBHNv8i16_v16i8
|
|
555848067U, // SUBHNv8i16_v8i8
|
|
807424614U, // SUBP
|
|
807425477U, // SUBPS
|
|
3760231349U, // SUBR_ZI_B
|
|
2418070453U, // SUBR_ZI_D
|
|
2179011509U, // SUBR_ZI_H
|
|
4028715957U, // SUBR_ZI_S
|
|
3223360437U, // SUBR_ZPmZ_B
|
|
3223376821U, // SUBR_ZPmZ_D
|
|
3519091637U, // SUBR_ZPmZ_H
|
|
3223409589U, // SUBR_ZPmZ_S
|
|
807425342U, // SUBSWri
|
|
807425342U, // SUBSWrs
|
|
807425342U, // SUBSWrx
|
|
807425342U, // SUBSXri
|
|
807425342U, // SUBSXrs
|
|
807425342U, // SUBSXrx
|
|
807425342U, // SUBSXrx64
|
|
807422048U, // SUBWri
|
|
807422048U, // SUBWrs
|
|
807422048U, // SUBWrx
|
|
807422048U, // SUBXri
|
|
807422048U, // SUBXrs
|
|
807422048U, // SUBXrx
|
|
807422048U, // SUBXrx64
|
|
3760228448U, // SUB_ZI_B
|
|
2418067552U, // SUB_ZI_D
|
|
2179008608U, // SUB_ZI_H
|
|
4028713056U, // SUB_ZI_S
|
|
3223357536U, // SUB_ZPmZ_B
|
|
3223373920U, // SUB_ZPmZ_D
|
|
3519088736U, // SUB_ZPmZ_H
|
|
3223406688U, // SUB_ZPmZ_S
|
|
3760228448U, // SUB_ZZZ_B
|
|
2418067552U, // SUB_ZZZ_D
|
|
2179008608U, // SUB_ZZZ_H
|
|
4028713056U, // SUB_ZZZ_S
|
|
543262816U, // SUBv16i8
|
|
807422048U, // SUBv1i64
|
|
545359968U, // SUBv2i32
|
|
547457120U, // SUBv2i64
|
|
549554272U, // SUBv4i16
|
|
551651424U, // SUBv4i32
|
|
553748576U, // SUBv8i16
|
|
555845728U, // SUBv8i8
|
|
1344362538U, // SUDOT_ZZZI
|
|
2967607338U, // SUDOTlanev16i8
|
|
2961315882U, // SUDOTlanev8i8
|
|
138527526U, // SUMOPA_MPPZZ_D
|
|
140624678U, // SUMOPA_MPPZZ_S
|
|
138532324U, // SUMOPS_MPPZZ_D
|
|
140629476U, // SUMOPS_MPPZZ_S
|
|
4028681920U, // SUNPKHI_ZZ_D
|
|
1736511168U, // SUNPKHI_ZZ_H
|
|
1881231040U, // SUNPKHI_ZZ_S
|
|
4028682809U, // SUNPKLO_ZZ_D
|
|
1736512057U, // SUNPKLO_ZZ_H
|
|
1881231929U, // SUNPKLO_ZZ_S
|
|
3223357964U, // SUQADD_ZPmZ_B
|
|
3223374348U, // SUQADD_ZPmZ_D
|
|
3519089164U, // SUQADD_ZPmZ_H
|
|
3223407116U, // SUQADD_ZPmZ_S
|
|
2959215116U, // SUQADDv16i8
|
|
270748172U, // SUQADDv1i16
|
|
270748172U, // SUQADDv1i32
|
|
270748172U, // SUQADDv1i64
|
|
270748172U, // SUQADDv1i8
|
|
2961312268U, // SUQADDv2i32
|
|
2963409420U, // SUQADDv2i64
|
|
2965506572U, // SUQADDv4i16
|
|
2967603724U, // SUQADDv4i32
|
|
2969700876U, // SUQADDv8i16
|
|
2971798028U, // SUQADDv8i8
|
|
264473U, // SVC
|
|
3223536734U, // SWPAB
|
|
3223538691U, // SWPAH
|
|
3223536994U, // SWPALB
|
|
3223538847U, // SWPALH
|
|
3223539550U, // SWPALW
|
|
3223539550U, // SWPALX
|
|
3223536437U, // SWPAW
|
|
3223536437U, // SWPAX
|
|
3223537438U, // SWPB
|
|
3223539064U, // SWPH
|
|
3223537203U, // SWPLB
|
|
3223538944U, // SWPLH
|
|
3223539860U, // SWPLW
|
|
3223539860U, // SWPLX
|
|
3223540543U, // SWPW
|
|
3223540543U, // SWPX
|
|
2148435U, // SXTB_ZPmZ_D
|
|
272697427U, // SXTB_ZPmZ_H
|
|
2181203U, // SXTB_ZPmZ_S
|
|
2150019U, // SXTH_ZPmZ_D
|
|
2182787U, // SXTH_ZPmZ_S
|
|
2153095U, // SXTW_ZPmZ_D
|
|
807424212U, // SYSLxt
|
|
2119196U, // SYSxt
|
|
2133915U, // TBL_ZZZZ_B
|
|
270585755U, // TBL_ZZZZ_D
|
|
142675867U, // TBL_ZZZZ_H
|
|
539053979U, // TBL_ZZZZ_S
|
|
2133915U, // TBL_ZZZ_B
|
|
270585755U, // TBL_ZZZ_D
|
|
142675867U, // TBL_ZZZ_H
|
|
539053979U, // TBL_ZZZ_S
|
|
811700123U, // TBLv16i8Four
|
|
811700123U, // TBLv16i8One
|
|
811700123U, // TBLv16i8Three
|
|
811700123U, // TBLv16i8Two
|
|
824283035U, // TBLv8i8Four
|
|
824283035U, // TBLv8i8One
|
|
824283035U, // TBLv8i8Three
|
|
824283035U, // TBLv8i8Two
|
|
807426922U, // TBNZW
|
|
807426922U, // TBNZX
|
|
1344314065U, // TBX_ZZZ_B
|
|
1075894993U, // TBX_ZZZ_D
|
|
2185304785U, // TBX_ZZZ_H
|
|
1344363217U, // TBX_ZZZ_S
|
|
1080171217U, // TBXv16i8Four
|
|
1080171217U, // TBXv16i8One
|
|
1080171217U, // TBXv16i8Three
|
|
1080171217U, // TBXv16i8Two
|
|
1092754129U, // TBXv8i8Four
|
|
1092754129U, // TBXv8i8One
|
|
1092754129U, // TBXv8i8Three
|
|
1092754129U, // TBXv8i8Two
|
|
807426906U, // TBZW
|
|
807426906U, // TBZX
|
|
266226U, // TCANCEL
|
|
8670U, // TCOMMIT
|
|
3760226350U, // TRN1_PPP_B
|
|
2418065454U, // TRN1_PPP_D
|
|
2179006510U, // TRN1_PPP_H
|
|
4028710958U, // TRN1_PPP_S
|
|
3760226350U, // TRN1_ZZZ_B
|
|
2418065454U, // TRN1_ZZZ_D
|
|
2179006510U, // TRN1_ZZZ_H
|
|
2193981486U, // TRN1_ZZZ_Q
|
|
4028710958U, // TRN1_ZZZ_S
|
|
543260718U, // TRN1v16i8
|
|
545357870U, // TRN1v2i32
|
|
547455022U, // TRN1v2i64
|
|
549552174U, // TRN1v4i16
|
|
551649326U, // TRN1v4i32
|
|
553746478U, // TRN1v8i16
|
|
555843630U, // TRN1v8i8
|
|
3760226714U, // TRN2_PPP_B
|
|
2418065818U, // TRN2_PPP_D
|
|
2179006874U, // TRN2_PPP_H
|
|
4028711322U, // TRN2_PPP_S
|
|
3760226714U, // TRN2_ZZZ_B
|
|
2418065818U, // TRN2_ZZZ_D
|
|
2179006874U, // TRN2_ZZZ_H
|
|
2193981850U, // TRN2_ZZZ_Q
|
|
4028711322U, // TRN2_ZZZ_S
|
|
543261082U, // TRN2v16i8
|
|
545358234U, // TRN2v2i32
|
|
547455386U, // TRN2v2i64
|
|
549552538U, // TRN2v4i16
|
|
551649690U, // TRN2v4i32
|
|
553746842U, // TRN2v8i16
|
|
555843994U, // TRN2v8i8
|
|
329768U, // TSB
|
|
22583U, // TSTART
|
|
22605U, // TTEST
|
|
1344324887U, // UABALB_ZZZ_D
|
|
2281768215U, // UABALB_ZZZ_H
|
|
2686534935U, // UABALB_ZZZ_S
|
|
1344329390U, // UABALT_ZZZ_D
|
|
2281772718U, // UABALT_ZZZ_H
|
|
2686539438U, // UABALT_ZZZ_S
|
|
2969698476U, // UABALv16i8_v8i16
|
|
2963410708U, // UABALv2i32_v2i64
|
|
2967605012U, // UABALv4i16_v4i32
|
|
2963407020U, // UABALv4i32_v2i64
|
|
2967601324U, // UABALv8i16_v4i32
|
|
2969702164U, // UABALv8i8_v8i16
|
|
1344307853U, // UABA_ZZZ_B
|
|
1075888781U, // UABA_ZZZ_D
|
|
2185298573U, // UABA_ZZZ_H
|
|
1344357005U, // UABA_ZZZ_S
|
|
2959213197U, // UABAv16i8
|
|
2961310349U, // UABAv2i32
|
|
2965504653U, // UABAv4i16
|
|
2967601805U, // UABAv4i32
|
|
2969698957U, // UABAv8i16
|
|
2971796109U, // UABAv8i8
|
|
4028679628U, // UABDLB_ZZZ_D
|
|
2273379788U, // UABDLB_ZZZ_H
|
|
1881228748U, // UABDLB_ZZZ_S
|
|
4028684031U, // UABDLT_ZZZ_D
|
|
2273384191U, // UABDLT_ZZZ_H
|
|
1881233151U, // UABDLT_ZZZ_S
|
|
553746670U, // UABDLv16i8_v8i16
|
|
547459013U, // UABDLv2i32_v2i64
|
|
551653317U, // UABDLv4i16_v4i32
|
|
547455214U, // UABDLv4i32_v2i64
|
|
551649518U, // UABDLv8i16_v4i32
|
|
553750469U, // UABDLv8i8_v8i16
|
|
3223357838U, // UABD_ZPmZ_B
|
|
3223374222U, // UABD_ZPmZ_D
|
|
3519089038U, // UABD_ZPmZ_H
|
|
3223406990U, // UABD_ZPmZ_S
|
|
543263118U, // UABDv16i8
|
|
545360270U, // UABDv2i32
|
|
549554574U, // UABDv4i16
|
|
551651726U, // UABDv4i32
|
|
553748878U, // UABDv8i16
|
|
555846030U, // UABDv8i8
|
|
3223376556U, // UADALP_ZPmZ_D
|
|
3519091372U, // UADALP_ZPmZ_H
|
|
3223409324U, // UADALP_ZPmZ_S
|
|
2969703084U, // UADALPv16i8_v8i16
|
|
3089240748U, // UADALPv2i32_v1i64
|
|
2961314476U, // UADALPv4i16_v2i32
|
|
2963411628U, // UADALPv4i32_v2i64
|
|
2967605932U, // UADALPv8i16_v4i32
|
|
2965508780U, // UADALPv8i8_v4i16
|
|
4028679653U, // UADDLB_ZZZ_D
|
|
2273379813U, // UADDLB_ZZZ_H
|
|
1881228773U, // UADDLB_ZZZ_S
|
|
553751228U, // UADDLPv16i8_v8i16
|
|
673288892U, // UADDLPv2i32_v1i64
|
|
545362620U, // UADDLPv4i16_v2i32
|
|
547459772U, // UADDLPv4i32_v2i64
|
|
551654076U, // UADDLPv8i16_v4i32
|
|
549556924U, // UADDLPv8i8_v4i16
|
|
4028684047U, // UADDLT_ZZZ_D
|
|
2273384207U, // UADDLT_ZZZ_H
|
|
1881233167U, // UADDLT_ZZZ_S
|
|
538990857U, // UADDLVv16i8v
|
|
538990857U, // UADDLVv4i16v
|
|
538990857U, // UADDLVv4i32v
|
|
538990857U, // UADDLVv8i16v
|
|
538990857U, // UADDLVv8i8v
|
|
553746686U, // UADDLv16i8_v8i16
|
|
547459051U, // UADDLv2i32_v2i64
|
|
551653355U, // UADDLv4i16_v4i32
|
|
547455230U, // UADDLv4i32_v2i64
|
|
551649534U, // UADDLv8i16_v4i32
|
|
553750507U, // UADDLv8i8_v8i16
|
|
1745000669U, // UADDV_VPZ_B
|
|
1646434525U, // UADDV_VPZ_D
|
|
1648531677U, // UADDV_VPZ_H
|
|
1638045917U, // UADDV_VPZ_S
|
|
2418067630U, // UADDWB_ZZZ_D
|
|
2179008686U, // UADDWB_ZZZ_H
|
|
4028713134U, // UADDWB_ZZZ_S
|
|
2418071682U, // UADDWT_ZZZ_D
|
|
2179012738U, // UADDWT_ZZZ_H
|
|
4028717186U, // UADDWT_ZZZ_S
|
|
553746960U, // UADDWv16i8_v8i16
|
|
547461634U, // UADDWv2i32_v2i64
|
|
551655938U, // UADDWv4i16_v4i32
|
|
547455504U, // UADDWv4i32_v2i64
|
|
551649808U, // UADDWv8i16_v4i32
|
|
553753090U, // UADDWv8i8_v8i16
|
|
807424304U, // UBFMWri
|
|
807424304U, // UBFMXri
|
|
3760231116U, // UCLAMP_ZZZ_B
|
|
2418070220U, // UCLAMP_ZZZ_D
|
|
2179011276U, // UCLAMP_ZZZ_H
|
|
4028715724U, // UCLAMP_ZZZ_S
|
|
807422734U, // UCVTFSWDri
|
|
807422734U, // UCVTFSWHri
|
|
807422734U, // UCVTFSWSri
|
|
807422734U, // UCVTFSXDri
|
|
807422734U, // UCVTFSXHri
|
|
807422734U, // UCVTFSXSri
|
|
807422734U, // UCVTFUWDri
|
|
807422734U, // UCVTFUWHri
|
|
807422734U, // UCVTFUWSri
|
|
807422734U, // UCVTFUXDri
|
|
807422734U, // UCVTFUXHri
|
|
807422734U, // UCVTFUXSri
|
|
2149134U, // UCVTF_ZPmZ_DtoD
|
|
541133582U, // UCVTF_ZPmZ_DtoH
|
|
2181902U, // UCVTF_ZPmZ_DtoS
|
|
272698126U, // UCVTF_ZPmZ_HtoH
|
|
2149134U, // UCVTF_ZPmZ_StoD
|
|
541133582U, // UCVTF_ZPmZ_StoH
|
|
2181902U, // UCVTF_ZPmZ_StoS
|
|
807422734U, // UCVTFd
|
|
807422734U, // UCVTFh
|
|
807422734U, // UCVTFs
|
|
807422734U, // UCVTFv1i16
|
|
807422734U, // UCVTFv1i32
|
|
807422734U, // UCVTFv1i64
|
|
545360654U, // UCVTFv2f32
|
|
547457806U, // UCVTFv2f64
|
|
545360654U, // UCVTFv2i32_shift
|
|
547457806U, // UCVTFv2i64_shift
|
|
549554958U, // UCVTFv4f16
|
|
551652110U, // UCVTFv4f32
|
|
549554958U, // UCVTFv4i16_shift
|
|
551652110U, // UCVTFv4i32_shift
|
|
553749262U, // UCVTFv8f16
|
|
553749262U, // UCVTFv8i16_shift
|
|
19191U, // UDF
|
|
3223377116U, // UDIVR_ZPmZ_D
|
|
3223409884U, // UDIVR_ZPmZ_S
|
|
807426299U, // UDIVWr
|
|
807426299U, // UDIVXr
|
|
3223378171U, // UDIV_ZPmZ_D
|
|
3223410939U, // UDIV_ZPmZ_S
|
|
2686507051U, // UDOT_ZZZI_D
|
|
1344362539U, // UDOT_ZZZI_S
|
|
2686507051U, // UDOT_ZZZ_D
|
|
1344362539U, // UDOT_ZZZ_S
|
|
2967607339U, // UDOTlanev16i8
|
|
2961315883U, // UDOTlanev8i8
|
|
2967607339U, // UDOTv16i8
|
|
2961315883U, // UDOTv8i8
|
|
3223357934U, // UHADD_ZPmZ_B
|
|
3223374318U, // UHADD_ZPmZ_D
|
|
3519089134U, // UHADD_ZPmZ_H
|
|
3223407086U, // UHADD_ZPmZ_S
|
|
543263214U, // UHADDv16i8
|
|
545360366U, // UHADDv2i32
|
|
549554670U, // UHADDv4i16
|
|
551651822U, // UHADDv4i32
|
|
553748974U, // UHADDv8i16
|
|
555846126U, // UHADDv8i8
|
|
3223360451U, // UHSUBR_ZPmZ_B
|
|
3223376835U, // UHSUBR_ZPmZ_D
|
|
3519091651U, // UHSUBR_ZPmZ_H
|
|
3223409603U, // UHSUBR_ZPmZ_S
|
|
3223357548U, // UHSUB_ZPmZ_B
|
|
3223373932U, // UHSUB_ZPmZ_D
|
|
3519088748U, // UHSUB_ZPmZ_H
|
|
3223406700U, // UHSUB_ZPmZ_S
|
|
543262828U, // UHSUBv16i8
|
|
545359980U, // UHSUBv2i32
|
|
549554284U, // UHSUBv4i16
|
|
551651436U, // UHSUBv4i32
|
|
553748588U, // UHSUBv8i16
|
|
555845740U, // UHSUBv8i8
|
|
807423964U, // UMADDLrrr
|
|
3223360345U, // UMAXP_ZPmZ_B
|
|
3223376729U, // UMAXP_ZPmZ_D
|
|
3519091545U, // UMAXP_ZPmZ_H
|
|
3223409497U, // UMAXP_ZPmZ_S
|
|
543265625U, // UMAXPv16i8
|
|
545362777U, // UMAXPv2i32
|
|
549557081U, // UMAXPv4i16
|
|
551654233U, // UMAXPv4i32
|
|
553751385U, // UMAXPv8i16
|
|
555848537U, // UMAXPv8i8
|
|
153957U, // UMAXV_VPZ_B
|
|
1646434661U, // UMAXV_VPZ_D
|
|
1648548197U, // UMAXV_VPZ_H
|
|
1638078821U, // UMAXV_VPZ_S
|
|
538990949U, // UMAXVv16i8v
|
|
538990949U, // UMAXVv4i16v
|
|
538990949U, // UMAXVv4i32v
|
|
538990949U, // UMAXVv8i16v
|
|
538990949U, // UMAXVv8i8v
|
|
3760233163U, // UMAX_ZI_B
|
|
2418072267U, // UMAX_ZI_D
|
|
2179013323U, // UMAX_ZI_H
|
|
4028717771U, // UMAX_ZI_S
|
|
3223362251U, // UMAX_ZPmZ_B
|
|
3223378635U, // UMAX_ZPmZ_D
|
|
3519093451U, // UMAX_ZPmZ_H
|
|
3223411403U, // UMAX_ZPmZ_S
|
|
543267531U, // UMAXv16i8
|
|
545364683U, // UMAXv2i32
|
|
549558987U, // UMAXv4i16
|
|
551656139U, // UMAXv4i32
|
|
553753291U, // UMAXv8i16
|
|
555850443U, // UMAXv8i8
|
|
3223360263U, // UMINP_ZPmZ_B
|
|
3223376647U, // UMINP_ZPmZ_D
|
|
3519091463U, // UMINP_ZPmZ_H
|
|
3223409415U, // UMINP_ZPmZ_S
|
|
543265543U, // UMINPv16i8
|
|
545362695U, // UMINPv2i32
|
|
549556999U, // UMINPv4i16
|
|
551654151U, // UMINPv4i32
|
|
553751303U, // UMINPv8i16
|
|
555848455U, // UMINPv8i8
|
|
153905U, // UMINV_VPZ_B
|
|
1646434609U, // UMINV_VPZ_D
|
|
1648548145U, // UMINV_VPZ_H
|
|
1638078769U, // UMINV_VPZ_S
|
|
538990897U, // UMINVv16i8v
|
|
538990897U, // UMINVv4i16v
|
|
538990897U, // UMINVv4i32v
|
|
538990897U, // UMINVv8i16v
|
|
538990897U, // UMINVv8i8v
|
|
3760230818U, // UMIN_ZI_B
|
|
2418069922U, // UMIN_ZI_D
|
|
2179010978U, // UMIN_ZI_H
|
|
4028715426U, // UMIN_ZI_S
|
|
3223359906U, // UMIN_ZPmZ_B
|
|
3223376290U, // UMIN_ZPmZ_D
|
|
3519091106U, // UMIN_ZPmZ_H
|
|
3223409058U, // UMIN_ZPmZ_S
|
|
543265186U, // UMINv16i8
|
|
545362338U, // UMINv2i32
|
|
549556642U, // UMINv4i16
|
|
551653794U, // UMINv4i32
|
|
553750946U, // UMINv8i16
|
|
555848098U, // UMINv8i8
|
|
1344324932U, // UMLALB_ZZZI_D
|
|
2686534980U, // UMLALB_ZZZI_S
|
|
1344324932U, // UMLALB_ZZZ_D
|
|
2281768260U, // UMLALB_ZZZ_H
|
|
2686534980U, // UMLALB_ZZZ_S
|
|
1344329425U, // UMLALT_ZZZI_D
|
|
2686539473U, // UMLALT_ZZZI_S
|
|
1344329425U, // UMLALT_ZZZ_D
|
|
2281772753U, // UMLALT_ZZZ_H
|
|
2686539473U, // UMLALT_ZZZ_S
|
|
2969698510U, // UMLALv16i8_v8i16
|
|
2963410747U, // UMLALv2i32_indexed
|
|
2963410747U, // UMLALv2i32_v2i64
|
|
2967605051U, // UMLALv4i16_indexed
|
|
2967605051U, // UMLALv4i16_v4i32
|
|
2963407054U, // UMLALv4i32_indexed
|
|
2963407054U, // UMLALv4i32_v2i64
|
|
2967601358U, // UMLALv8i16_indexed
|
|
2967601358U, // UMLALv8i16_v4i32
|
|
2969702203U, // UMLALv8i8_v8i16
|
|
1344325229U, // UMLSLB_ZZZI_D
|
|
2686535277U, // UMLSLB_ZZZI_S
|
|
1344325229U, // UMLSLB_ZZZ_D
|
|
2281768557U, // UMLSLB_ZZZ_H
|
|
2686535277U, // UMLSLB_ZZZ_S
|
|
1344329599U, // UMLSLT_ZZZI_D
|
|
2686539647U, // UMLSLT_ZZZI_S
|
|
1344329599U, // UMLSLT_ZZZ_D
|
|
2281772927U, // UMLSLT_ZZZ_H
|
|
2686539647U, // UMLSLT_ZZZ_S
|
|
2969698642U, // UMLSLv16i8_v8i16
|
|
2963411149U, // UMLSLv2i32_indexed
|
|
2963411149U, // UMLSLv2i32_v2i64
|
|
2967605453U, // UMLSLv4i16_indexed
|
|
2967605453U, // UMLSLv4i16_v4i32
|
|
2963407186U, // UMLSLv4i32_indexed
|
|
2963407186U, // UMLSLv4i32_v2i64
|
|
2967601490U, // UMLSLv8i16_indexed
|
|
2967601490U, // UMLSLv8i16_v4i32
|
|
2969702605U, // UMLSLv8i8_v8i16
|
|
2967601903U, // UMMLA
|
|
1344357103U, // UMMLA_ZZZ
|
|
138527527U, // UMOPA_MPPZZ_D
|
|
140624679U, // UMOPA_MPPZZ_S
|
|
138532325U, // UMOPS_MPPZZ_D
|
|
140629477U, // UMOPS_MPPZZ_S
|
|
538990923U, // UMOVvi16
|
|
538990923U, // UMOVvi16_idx0
|
|
538990923U, // UMOVvi32
|
|
538990923U, // UMOVvi32_idx0
|
|
538990923U, // UMOVvi64
|
|
538990923U, // UMOVvi64_idx0
|
|
538990923U, // UMOVvi8
|
|
538990923U, // UMOVvi8_idx0
|
|
807423912U, // UMSUBLrrr
|
|
3223358787U, // UMULH_ZPmZ_B
|
|
3223375171U, // UMULH_ZPmZ_D
|
|
3519089987U, // UMULH_ZPmZ_H
|
|
3223407939U, // UMULH_ZPmZ_S
|
|
3760229699U, // UMULH_ZZZ_B
|
|
2418068803U, // UMULH_ZZZ_D
|
|
2179009859U, // UMULH_ZZZ_H
|
|
4028714307U, // UMULH_ZZZ_S
|
|
807423299U, // UMULHrr
|
|
4028679703U, // UMULLB_ZZZI_D
|
|
1881228823U, // UMULLB_ZZZI_S
|
|
4028679703U, // UMULLB_ZZZ_D
|
|
2273379863U, // UMULLB_ZZZ_H
|
|
1881228823U, // UMULLB_ZZZ_S
|
|
4028684111U, // UMULLT_ZZZI_D
|
|
1881233231U, // UMULLT_ZZZI_S
|
|
4028684111U, // UMULLT_ZZZ_D
|
|
2273384271U, // UMULLT_ZZZ_H
|
|
1881233231U, // UMULLT_ZZZ_S
|
|
553746736U, // UMULLv16i8_v8i16
|
|
547459181U, // UMULLv2i32_indexed
|
|
547459181U, // UMULLv2i32_v2i64
|
|
551653485U, // UMULLv4i16_indexed
|
|
551653485U, // UMULLv4i16_v4i32
|
|
547455280U, // UMULLv4i32_indexed
|
|
547455280U, // UMULLv4i32_v2i64
|
|
551649584U, // UMULLv8i16_indexed
|
|
551649584U, // UMULLv8i16_v4i32
|
|
553750637U, // UMULLv8i8_v8i16
|
|
3760228877U, // UQADD_ZI_B
|
|
2418067981U, // UQADD_ZI_D
|
|
2179009037U, // UQADD_ZI_H
|
|
4028713485U, // UQADD_ZI_S
|
|
3223357965U, // UQADD_ZPmZ_B
|
|
3223374349U, // UQADD_ZPmZ_D
|
|
3519089165U, // UQADD_ZPmZ_H
|
|
3223407117U, // UQADD_ZPmZ_S
|
|
3760228877U, // UQADD_ZZZ_B
|
|
2418067981U, // UQADD_ZZZ_D
|
|
2179009037U, // UQADD_ZZZ_H
|
|
4028713485U, // UQADD_ZZZ_S
|
|
543263245U, // UQADDv16i8
|
|
807422477U, // UQADDv1i16
|
|
807422477U, // UQADDv1i32
|
|
807422477U, // UQADDv1i64
|
|
807422477U, // UQADDv1i8
|
|
545360397U, // UQADDv2i32
|
|
547457549U, // UQADDv2i64
|
|
549554701U, // UQADDv4i16
|
|
551651853U, // UQADDv4i32
|
|
553749005U, // UQADDv8i16
|
|
555846157U, // UQADDv8i8
|
|
2686469312U, // UQDECB_WPiI
|
|
2686469312U, // UQDECB_XPiI
|
|
2686470563U, // UQDECD_WPiI
|
|
2686470563U, // UQDECD_XPiI
|
|
2686503331U, // UQDECD_ZPiI
|
|
2686471249U, // UQDECH_WPiI
|
|
2686471249U, // UQDECH_XPiI
|
|
39914577U, // UQDECH_ZPiI
|
|
3760214644U, // UQDECP_WP_B
|
|
2418037364U, // UQDECP_WP_D
|
|
1881166452U, // UQDECP_WP_H
|
|
4028650100U, // UQDECP_WP_S
|
|
3760214644U, // UQDECP_XP_B
|
|
2418037364U, // UQDECP_XP_D
|
|
1881166452U, // UQDECP_XP_H
|
|
4028650100U, // UQDECP_XP_S
|
|
1075892852U, // UQDECP_ZP_D
|
|
1648431732U, // UQDECP_ZP_H
|
|
1344361076U, // UQDECP_ZP_S
|
|
2686474723U, // UQDECW_WPiI
|
|
2686474723U, // UQDECW_XPiI
|
|
2686540259U, // UQDECW_ZPiI
|
|
2686469328U, // UQINCB_WPiI
|
|
2686469328U, // UQINCB_XPiI
|
|
2686470579U, // UQINCD_WPiI
|
|
2686470579U, // UQINCD_XPiI
|
|
2686503347U, // UQINCD_ZPiI
|
|
2686471265U, // UQINCH_WPiI
|
|
2686471265U, // UQINCH_XPiI
|
|
39914593U, // UQINCH_ZPiI
|
|
3760214660U, // UQINCP_WP_B
|
|
2418037380U, // UQINCP_WP_D
|
|
1881166468U, // UQINCP_WP_H
|
|
4028650116U, // UQINCP_WP_S
|
|
3760214660U, // UQINCP_XP_B
|
|
2418037380U, // UQINCP_XP_D
|
|
1881166468U, // UQINCP_XP_H
|
|
4028650116U, // UQINCP_XP_S
|
|
1075892868U, // UQINCP_ZP_D
|
|
1648431748U, // UQINCP_ZP_H
|
|
1344361092U, // UQINCP_ZP_S
|
|
2686474739U, // UQINCW_WPiI
|
|
2686474739U, // UQINCW_XPiI
|
|
2686540275U, // UQINCW_ZPiI
|
|
3223360562U, // UQRSHLR_ZPmZ_B
|
|
3223376946U, // UQRSHLR_ZPmZ_D
|
|
3519091762U, // UQRSHLR_ZPmZ_H
|
|
3223409714U, // UQRSHLR_ZPmZ_S
|
|
3223359526U, // UQRSHL_ZPmZ_B
|
|
3223375910U, // UQRSHL_ZPmZ_D
|
|
3519090726U, // UQRSHL_ZPmZ_H
|
|
3223408678U, // UQRSHL_ZPmZ_S
|
|
543264806U, // UQRSHLv16i8
|
|
807424038U, // UQRSHLv1i16
|
|
807424038U, // UQRSHLv1i32
|
|
807424038U, // UQRSHLv1i64
|
|
807424038U, // UQRSHLv1i8
|
|
545361958U, // UQRSHLv2i32
|
|
547459110U, // UQRSHLv2i64
|
|
549556262U, // UQRSHLv4i16
|
|
551653414U, // UQRSHLv4i32
|
|
553750566U, // UQRSHLv8i16
|
|
555847718U, // UQRSHLv8i8
|
|
1881179863U, // UQRSHRNB_ZZI_B
|
|
2172716759U, // UQRSHRNB_ZZI_H
|
|
2418099927U, // UQRSHRNB_ZZI_S
|
|
2686490572U, // UQRSHRNT_ZZI_B
|
|
2174818252U, // UQRSHRNT_ZZI_H
|
|
1075926988U, // UQRSHRNT_ZZI_S
|
|
807424466U, // UQRSHRNb
|
|
807424466U, // UQRSHRNh
|
|
807424466U, // UQRSHRNs
|
|
2959212944U, // UQRSHRNv16i8_shift
|
|
545362386U, // UQRSHRNv2i32_shift
|
|
549556690U, // UQRSHRNv4i16_shift
|
|
2967601552U, // UQRSHRNv4i32_shift
|
|
2969698704U, // UQRSHRNv8i16_shift
|
|
555848146U, // UQRSHRNv8i8_shift
|
|
3223360545U, // UQSHLR_ZPmZ_B
|
|
3223376929U, // UQSHLR_ZPmZ_D
|
|
3519091745U, // UQSHLR_ZPmZ_H
|
|
3223409697U, // UQSHLR_ZPmZ_S
|
|
3223359511U, // UQSHL_ZPmI_B
|
|
3223375895U, // UQSHL_ZPmI_D
|
|
3519090711U, // UQSHL_ZPmI_H
|
|
3223408663U, // UQSHL_ZPmI_S
|
|
3223359511U, // UQSHL_ZPmZ_B
|
|
3223375895U, // UQSHL_ZPmZ_D
|
|
3519090711U, // UQSHL_ZPmZ_H
|
|
3223408663U, // UQSHL_ZPmZ_S
|
|
807424023U, // UQSHLb
|
|
807424023U, // UQSHLd
|
|
807424023U, // UQSHLh
|
|
807424023U, // UQSHLs
|
|
543264791U, // UQSHLv16i8
|
|
543264791U, // UQSHLv16i8_shift
|
|
807424023U, // UQSHLv1i16
|
|
807424023U, // UQSHLv1i32
|
|
807424023U, // UQSHLv1i64
|
|
807424023U, // UQSHLv1i8
|
|
545361943U, // UQSHLv2i32
|
|
545361943U, // UQSHLv2i32_shift
|
|
547459095U, // UQSHLv2i64
|
|
547459095U, // UQSHLv2i64_shift
|
|
549556247U, // UQSHLv4i16
|
|
549556247U, // UQSHLv4i16_shift
|
|
551653399U, // UQSHLv4i32
|
|
551653399U, // UQSHLv4i32_shift
|
|
553750551U, // UQSHLv8i16
|
|
553750551U, // UQSHLv8i16_shift
|
|
555847703U, // UQSHLv8i8
|
|
555847703U, // UQSHLv8i8_shift
|
|
1881179844U, // UQSHRNB_ZZI_B
|
|
2172716740U, // UQSHRNB_ZZI_H
|
|
2418099908U, // UQSHRNB_ZZI_S
|
|
2686490553U, // UQSHRNT_ZZI_B
|
|
2174818233U, // UQSHRNT_ZZI_H
|
|
1075926969U, // UQSHRNT_ZZI_S
|
|
807424449U, // UQSHRNb
|
|
807424449U, // UQSHRNh
|
|
807424449U, // UQSHRNs
|
|
2959212925U, // UQSHRNv16i8_shift
|
|
545362369U, // UQSHRNv2i32_shift
|
|
549556673U, // UQSHRNv4i16_shift
|
|
2967601533U, // UQSHRNv4i32_shift
|
|
2969698685U, // UQSHRNv8i16_shift
|
|
555848129U, // UQSHRNv8i8_shift
|
|
3223360467U, // UQSUBR_ZPmZ_B
|
|
3223376851U, // UQSUBR_ZPmZ_D
|
|
3519091667U, // UQSUBR_ZPmZ_H
|
|
3223409619U, // UQSUBR_ZPmZ_S
|
|
3760228489U, // UQSUB_ZI_B
|
|
2418067593U, // UQSUB_ZI_D
|
|
2179008649U, // UQSUB_ZI_H
|
|
4028713097U, // UQSUB_ZI_S
|
|
3223357577U, // UQSUB_ZPmZ_B
|
|
3223373961U, // UQSUB_ZPmZ_D
|
|
3519088777U, // UQSUB_ZPmZ_H
|
|
3223406729U, // UQSUB_ZPmZ_S
|
|
3760228489U, // UQSUB_ZZZ_B
|
|
2418067593U, // UQSUB_ZZZ_D
|
|
2179008649U, // UQSUB_ZZZ_H
|
|
4028713097U, // UQSUB_ZZZ_S
|
|
543262857U, // UQSUBv16i8
|
|
807422089U, // UQSUBv1i16
|
|
807422089U, // UQSUBv1i32
|
|
807422089U, // UQSUBv1i64
|
|
807422089U, // UQSUBv1i8
|
|
545360009U, // UQSUBv2i32
|
|
547457161U, // UQSUBv2i64
|
|
549554313U, // UQSUBv4i16
|
|
551651465U, // UQSUBv4i32
|
|
553748617U, // UQSUBv8i16
|
|
555845769U, // UQSUBv8i8
|
|
1881179881U, // UQXTNB_ZZ_B
|
|
1635845865U, // UQXTNB_ZZ_H
|
|
2418099945U, // UQXTNB_ZZ_S
|
|
2686490599U, // UQXTNT_ZZ_B
|
|
1637947367U, // UQXTNT_ZZ_H
|
|
1075927015U, // UQXTNT_ZZ_S
|
|
2959212977U, // UQXTNv16i8
|
|
807424503U, // UQXTNv1i16
|
|
807424503U, // UQXTNv1i32
|
|
807424503U, // UQXTNv1i8
|
|
545362423U, // UQXTNv2i32
|
|
549556727U, // UQXTNv4i16
|
|
2967601585U, // UQXTNv4i32
|
|
2969698737U, // UQXTNv8i16
|
|
555848183U, // UQXTNv8i8
|
|
2181817U, // URECPE_ZPmZ_S
|
|
545360569U, // URECPEv2i32
|
|
551652025U, // URECPEv4i32
|
|
3223357919U, // URHADD_ZPmZ_B
|
|
3223374303U, // URHADD_ZPmZ_D
|
|
3519089119U, // URHADD_ZPmZ_H
|
|
3223407071U, // URHADD_ZPmZ_S
|
|
543263199U, // URHADDv16i8
|
|
545360351U, // URHADDv2i32
|
|
549554655U, // URHADDv4i16
|
|
551651807U, // URHADDv4i32
|
|
553748959U, // URHADDv8i16
|
|
555846111U, // URHADDv8i8
|
|
3223360579U, // URSHLR_ZPmZ_B
|
|
3223376963U, // URSHLR_ZPmZ_D
|
|
3519091779U, // URSHLR_ZPmZ_H
|
|
3223409731U, // URSHLR_ZPmZ_S
|
|
3223359541U, // URSHL_ZPmZ_B
|
|
3223375925U, // URSHL_ZPmZ_D
|
|
3519090741U, // URSHL_ZPmZ_H
|
|
3223408693U, // URSHL_ZPmZ_S
|
|
543264821U, // URSHLv16i8
|
|
807424053U, // URSHLv1i64
|
|
545361973U, // URSHLv2i32
|
|
547459125U, // URSHLv2i64
|
|
549556277U, // URSHLv4i16
|
|
551653429U, // URSHLv4i32
|
|
553750581U, // URSHLv8i16
|
|
555847733U, // URSHLv8i8
|
|
3223360506U, // URSHR_ZPmI_B
|
|
3223376890U, // URSHR_ZPmI_D
|
|
3519091706U, // URSHR_ZPmI_H
|
|
3223409658U, // URSHR_ZPmI_S
|
|
807425018U, // URSHRd
|
|
543265786U, // URSHRv16i8_shift
|
|
545362938U, // URSHRv2i32_shift
|
|
547460090U, // URSHRv2i64_shift
|
|
549557242U, // URSHRv4i16_shift
|
|
551654394U, // URSHRv4i32_shift
|
|
553751546U, // URSHRv8i16_shift
|
|
555848698U, // URSHRv8i8_shift
|
|
2181863U, // URSQRTE_ZPmZ_S
|
|
545360615U, // URSQRTEv2i32
|
|
551652071U, // URSQRTEv4i32
|
|
1344308057U, // URSRA_ZZI_B
|
|
1075888985U, // URSRA_ZZI_D
|
|
2185298777U, // URSRA_ZZI_H
|
|
1344357209U, // URSRA_ZZI_S
|
|
270746457U, // URSRAd
|
|
2959213401U, // URSRAv16i8_shift
|
|
2961310553U, // URSRAv2i32_shift
|
|
2963407705U, // URSRAv2i64_shift
|
|
2965504857U, // URSRAv4i16_shift
|
|
2967602009U, // URSRAv4i32_shift
|
|
2969699161U, // URSRAv8i16_shift
|
|
2971796313U, // URSRAv8i8_shift
|
|
1344362531U, // USDOT_ZZZ
|
|
1344362531U, // USDOT_ZZZI
|
|
2967607331U, // USDOTlanev16i8
|
|
2961315875U, // USDOTlanev8i8
|
|
2967607331U, // USDOTv16i8
|
|
2961315875U, // USDOTv8i8
|
|
4028679669U, // USHLLB_ZZI_D
|
|
2273379829U, // USHLLB_ZZI_H
|
|
1881228789U, // USHLLB_ZZI_S
|
|
4028684077U, // USHLLT_ZZI_D
|
|
2273384237U, // USHLLT_ZZI_H
|
|
1881233197U, // USHLLT_ZZI_S
|
|
553746702U, // USHLLv16i8_shift
|
|
547459151U, // USHLLv2i32_shift
|
|
551653455U, // USHLLv4i16_shift
|
|
547455246U, // USHLLv4i32_shift
|
|
551649550U, // USHLLv8i16_shift
|
|
553750607U, // USHLLv8i8_shift
|
|
543264834U, // USHLv16i8
|
|
807424066U, // USHLv1i64
|
|
545361986U, // USHLv2i32
|
|
547459138U, // USHLv2i64
|
|
549556290U, // USHLv4i16
|
|
551653442U, // USHLv4i32
|
|
553750594U, // USHLv8i16
|
|
555847746U, // USHLv8i8
|
|
807425031U, // USHRd
|
|
543265799U, // USHRv16i8_shift
|
|
545362951U, // USHRv2i32_shift
|
|
547460103U, // USHRv2i64_shift
|
|
549557255U, // USHRv4i16_shift
|
|
551654407U, // USHRv4i32_shift
|
|
553751559U, // USHRv8i16_shift
|
|
555848711U, // USHRv8i8_shift
|
|
2967601895U, // USMMLA
|
|
1344357095U, // USMMLA_ZZZ
|
|
138527518U, // USMOPA_MPPZZ_D
|
|
140624670U, // USMOPA_MPPZZ_S
|
|
138532316U, // USMOPS_MPPZZ_D
|
|
140629468U, // USMOPS_MPPZZ_S
|
|
3223357956U, // USQADD_ZPmZ_B
|
|
3223374340U, // USQADD_ZPmZ_D
|
|
3519089156U, // USQADD_ZPmZ_H
|
|
3223407108U, // USQADD_ZPmZ_S
|
|
2959215108U, // USQADDv16i8
|
|
270748164U, // USQADDv1i16
|
|
270748164U, // USQADDv1i32
|
|
270748164U, // USQADDv1i64
|
|
270748164U, // USQADDv1i8
|
|
2961312260U, // USQADDv2i32
|
|
2963409412U, // USQADDv2i64
|
|
2965506564U, // USQADDv4i16
|
|
2967603716U, // USQADDv4i32
|
|
2969700868U, // USQADDv8i16
|
|
2971798020U, // USQADDv8i8
|
|
1344308070U, // USRA_ZZI_B
|
|
1075888998U, // USRA_ZZI_D
|
|
2185298790U, // USRA_ZZI_H
|
|
1344357222U, // USRA_ZZI_S
|
|
270746470U, // USRAd
|
|
2959213414U, // USRAv16i8_shift
|
|
2961310566U, // USRAv2i32_shift
|
|
2963407718U, // USRAv2i64_shift
|
|
2965504870U, // USRAv4i16_shift
|
|
2967602022U, // USRAv4i32_shift
|
|
2969699174U, // USRAv8i16_shift
|
|
2971796326U, // USRAv8i8_shift
|
|
4028679598U, // USUBLB_ZZZ_D
|
|
2273379758U, // USUBLB_ZZZ_H
|
|
1881228718U, // USUBLB_ZZZ_S
|
|
4028684001U, // USUBLT_ZZZ_D
|
|
2273384161U, // USUBLT_ZZZ_H
|
|
1881233121U, // USUBLT_ZZZ_S
|
|
553746654U, // USUBLv16i8_v8i16
|
|
547458999U, // USUBLv2i32_v2i64
|
|
551653303U, // USUBLv4i16_v4i32
|
|
547455198U, // USUBLv4i32_v2i64
|
|
551649502U, // USUBLv8i16_v4i32
|
|
553750455U, // USUBLv8i8_v8i16
|
|
2418067614U, // USUBWB_ZZZ_D
|
|
2179008670U, // USUBWB_ZZZ_H
|
|
4028713118U, // USUBWB_ZZZ_S
|
|
2418071666U, // USUBWT_ZZZ_D
|
|
2179012722U, // USUBWT_ZZZ_H
|
|
4028717170U, // USUBWT_ZZZ_S
|
|
553746944U, // USUBWv16i8_v8i16
|
|
547461579U, // USUBWv2i32_v2i64
|
|
551655883U, // USUBWv4i16_v4i32
|
|
547455488U, // USUBWv4i32_v2i64
|
|
551649792U, // USUBWv8i16_v4i32
|
|
553753035U, // USUBWv8i8_v8i16
|
|
4028681929U, // UUNPKHI_ZZ_D
|
|
1736511177U, // UUNPKHI_ZZ_H
|
|
1881231049U, // UUNPKHI_ZZ_S
|
|
4028682818U, // UUNPKLO_ZZ_D
|
|
1736512066U, // UUNPKLO_ZZ_H
|
|
1881231938U, // UUNPKLO_ZZ_S
|
|
2148441U, // UXTB_ZPmZ_D
|
|
272697433U, // UXTB_ZPmZ_H
|
|
2181209U, // UXTB_ZPmZ_S
|
|
2150025U, // UXTH_ZPmZ_D
|
|
2182793U, // UXTH_ZPmZ_S
|
|
2153101U, // UXTW_ZPmZ_D
|
|
3760226362U, // UZP1_PPP_B
|
|
2418065466U, // UZP1_PPP_D
|
|
2179006522U, // UZP1_PPP_H
|
|
4028710970U, // UZP1_PPP_S
|
|
3760226362U, // UZP1_ZZZ_B
|
|
2418065466U, // UZP1_ZZZ_D
|
|
2179006522U, // UZP1_ZZZ_H
|
|
2193981498U, // UZP1_ZZZ_Q
|
|
4028710970U, // UZP1_ZZZ_S
|
|
543260730U, // UZP1v16i8
|
|
545357882U, // UZP1v2i32
|
|
547455034U, // UZP1v2i64
|
|
549552186U, // UZP1v4i16
|
|
551649338U, // UZP1v4i32
|
|
553746490U, // UZP1v8i16
|
|
555843642U, // UZP1v8i8
|
|
3760226790U, // UZP2_PPP_B
|
|
2418065894U, // UZP2_PPP_D
|
|
2179006950U, // UZP2_PPP_H
|
|
4028711398U, // UZP2_PPP_S
|
|
3760226790U, // UZP2_ZZZ_B
|
|
2418065894U, // UZP2_ZZZ_D
|
|
2179006950U, // UZP2_ZZZ_H
|
|
2193981926U, // UZP2_ZZZ_Q
|
|
4028711398U, // UZP2_ZZZ_S
|
|
543261158U, // UZP2v16i8
|
|
545358310U, // UZP2v2i32
|
|
547455462U, // UZP2v2i64
|
|
549552614U, // UZP2v4i16
|
|
551649766U, // UZP2v4i32
|
|
553746918U, // UZP2v8i16
|
|
555844070U, // UZP2v8i8
|
|
22122U, // WFET
|
|
22176U, // WFIT
|
|
807438948U, // WHILEGE_PWW_B
|
|
807455332U, // WHILEGE_PWW_D
|
|
2191592036U, // WHILEGE_PWW_H
|
|
807488100U, // WHILEGE_PWW_S
|
|
807438948U, // WHILEGE_PXX_B
|
|
807455332U, // WHILEGE_PXX_D
|
|
2191592036U, // WHILEGE_PXX_H
|
|
807488100U, // WHILEGE_PXX_S
|
|
807442051U, // WHILEGT_PWW_B
|
|
807458435U, // WHILEGT_PWW_D
|
|
2191595139U, // WHILEGT_PWW_H
|
|
807491203U, // WHILEGT_PWW_S
|
|
807442051U, // WHILEGT_PXX_B
|
|
807458435U, // WHILEGT_PXX_D
|
|
2191595139U, // WHILEGT_PXX_H
|
|
807491203U, // WHILEGT_PXX_S
|
|
807440046U, // WHILEHI_PWW_B
|
|
807456430U, // WHILEHI_PWW_D
|
|
2191593134U, // WHILEHI_PWW_H
|
|
807489198U, // WHILEHI_PWW_S
|
|
807440046U, // WHILEHI_PXX_B
|
|
807456430U, // WHILEHI_PXX_D
|
|
2191593134U, // WHILEHI_PXX_H
|
|
807489198U, // WHILEHI_PXX_S
|
|
807441771U, // WHILEHS_PWW_B
|
|
807458155U, // WHILEHS_PWW_D
|
|
2191594859U, // WHILEHS_PWW_H
|
|
807490923U, // WHILEHS_PWW_S
|
|
807441771U, // WHILEHS_PXX_B
|
|
807458155U, // WHILEHS_PXX_D
|
|
2191594859U, // WHILEHS_PXX_H
|
|
807490923U, // WHILEHS_PXX_S
|
|
807438979U, // WHILELE_PWW_B
|
|
807455363U, // WHILELE_PWW_D
|
|
2191592067U, // WHILELE_PWW_H
|
|
807488131U, // WHILELE_PWW_S
|
|
807438979U, // WHILELE_PXX_B
|
|
807455363U, // WHILELE_PXX_D
|
|
2191592067U, // WHILELE_PXX_H
|
|
807488131U, // WHILELE_PXX_S
|
|
807440935U, // WHILELO_PWW_B
|
|
807457319U, // WHILELO_PWW_D
|
|
2191594023U, // WHILELO_PWW_H
|
|
807490087U, // WHILELO_PWW_S
|
|
807440935U, // WHILELO_PXX_B
|
|
807457319U, // WHILELO_PXX_D
|
|
2191594023U, // WHILELO_PXX_H
|
|
807490087U, // WHILELO_PXX_S
|
|
807441798U, // WHILELS_PWW_B
|
|
807458182U, // WHILELS_PWW_D
|
|
2191594886U, // WHILELS_PWW_H
|
|
807490950U, // WHILELS_PWW_S
|
|
807441798U, // WHILELS_PXX_B
|
|
807458182U, // WHILELS_PXX_D
|
|
2191594886U, // WHILELS_PXX_H
|
|
807490950U, // WHILELS_PXX_S
|
|
807442199U, // WHILELT_PWW_B
|
|
807458583U, // WHILELT_PWW_D
|
|
2191595287U, // WHILELT_PWW_H
|
|
807491351U, // WHILELT_PWW_S
|
|
807442199U, // WHILELT_PXX_B
|
|
807458583U, // WHILELT_PXX_D
|
|
2191595287U, // WHILELT_PXX_H
|
|
807491351U, // WHILELT_PXX_S
|
|
807442982U, // WHILERW_PXX_B
|
|
807459366U, // WHILERW_PXX_D
|
|
2191596070U, // WHILERW_PXX_H
|
|
807492134U, // WHILERW_PXX_S
|
|
807441635U, // WHILEWR_PXX_B
|
|
807458019U, // WHILEWR_PXX_D
|
|
2191594723U, // WHILEWR_PXX_H
|
|
807490787U, // WHILEWR_PXX_S
|
|
37868U, // WRFFR
|
|
8608U, // XAFLAG
|
|
547460015U, // XAR
|
|
3760231343U, // XAR_ZZZI_B
|
|
2418070447U, // XAR_ZZZI_D
|
|
2179011503U, // XAR_ZZZI_H
|
|
4028715951U, // XAR_ZZZI_S
|
|
18836U, // XPACD
|
|
20135U, // XPACI
|
|
7279U, // XPACLRI
|
|
2959212971U, // XTNv16i8
|
|
545362418U, // XTNv2i32
|
|
549556722U, // XTNv4i16
|
|
2967601579U, // XTNv4i32
|
|
2969698731U, // XTNv8i16
|
|
555848178U, // XTNv8i8
|
|
1102418U, // ZERO_M
|
|
3760226356U, // ZIP1_PPP_B
|
|
2418065460U, // ZIP1_PPP_D
|
|
2179006516U, // ZIP1_PPP_H
|
|
4028710964U, // ZIP1_PPP_S
|
|
3760226356U, // ZIP1_ZZZ_B
|
|
2418065460U, // ZIP1_ZZZ_D
|
|
2179006516U, // ZIP1_ZZZ_H
|
|
2193981492U, // ZIP1_ZZZ_Q
|
|
4028710964U, // ZIP1_ZZZ_S
|
|
543260724U, // ZIP1v16i8
|
|
545357876U, // ZIP1v2i32
|
|
547455028U, // ZIP1v2i64
|
|
549552180U, // ZIP1v4i16
|
|
551649332U, // ZIP1v4i32
|
|
553746484U, // ZIP1v8i16
|
|
555843636U, // ZIP1v8i8
|
|
3760226784U, // ZIP2_PPP_B
|
|
2418065888U, // ZIP2_PPP_D
|
|
2179006944U, // ZIP2_PPP_H
|
|
4028711392U, // ZIP2_PPP_S
|
|
3760226784U, // ZIP2_ZZZ_B
|
|
2418065888U, // ZIP2_ZZZ_D
|
|
2179006944U, // ZIP2_ZZZ_H
|
|
2193981920U, // ZIP2_ZZZ_Q
|
|
4028711392U, // ZIP2_ZZZ_S
|
|
543261152U, // ZIP2v16i8
|
|
545358304U, // ZIP2v2i32
|
|
547455456U, // ZIP2v2i64
|
|
549552608U, // ZIP2v4i16
|
|
551649760U, // ZIP2v4i32
|
|
553746912U, // ZIP2v8i16
|
|
555844064U, // ZIP2v8i8
|
|
138532308U, // anonymous_13987
|
|
138532309U, // anonymous_13988
|
|
138527510U, // anonymous_5384
|
|
138527511U, // anonymous_5385
|
|
};
|
|
|
|
static const uint32_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_FENCE
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ABS_ZPmZ_UNDEF_B
|
|
0U, // ABS_ZPmZ_UNDEF_D
|
|
0U, // ABS_ZPmZ_UNDEF_H
|
|
0U, // ABS_ZPmZ_UNDEF_S
|
|
0U, // ADDSWrr
|
|
0U, // ADDSXrr
|
|
0U, // ADDWrr
|
|
0U, // ADDXrr
|
|
0U, // ADD_ZPZZ_UNDEF_B
|
|
0U, // ADD_ZPZZ_UNDEF_D
|
|
0U, // ADD_ZPZZ_UNDEF_H
|
|
0U, // ADD_ZPZZ_UNDEF_S
|
|
0U, // ADD_ZPZZ_ZERO_B
|
|
0U, // ADD_ZPZZ_ZERO_D
|
|
0U, // ADD_ZPZZ_ZERO_H
|
|
0U, // ADD_ZPZZ_ZERO_S
|
|
0U, // ADDlowTLS
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // AESIMCrrTied
|
|
0U, // AESMCrrTied
|
|
0U, // ANDSWrr
|
|
0U, // ANDSXrr
|
|
0U, // ANDWrr
|
|
0U, // ANDXrr
|
|
0U, // ASRD_ZPZI_ZERO_B
|
|
0U, // ASRD_ZPZI_ZERO_D
|
|
0U, // ASRD_ZPZI_ZERO_H
|
|
0U, // ASRD_ZPZI_ZERO_S
|
|
0U, // ASR_ZPZI_UNDEF_B
|
|
0U, // ASR_ZPZI_UNDEF_D
|
|
0U, // ASR_ZPZI_UNDEF_H
|
|
0U, // ASR_ZPZI_UNDEF_S
|
|
0U, // ASR_ZPZZ_UNDEF_B
|
|
0U, // ASR_ZPZZ_UNDEF_D
|
|
0U, // ASR_ZPZZ_UNDEF_H
|
|
0U, // ASR_ZPZZ_UNDEF_S
|
|
0U, // ASR_ZPZZ_ZERO_B
|
|
0U, // ASR_ZPZZ_ZERO_D
|
|
0U, // ASR_ZPZZ_ZERO_H
|
|
0U, // ASR_ZPZZ_ZERO_S
|
|
0U, // BICSWrr
|
|
0U, // BICSXrr
|
|
0U, // BICWrr
|
|
0U, // BICXrr
|
|
0U, // BLRNoIP
|
|
0U, // BLR_BTI
|
|
0U, // BLR_RVMARKER
|
|
0U, // BSPv16i8
|
|
0U, // BSPv8i8
|
|
0U, // CATCHRET
|
|
0U, // CLEANUPRET
|
|
0U, // CLS_ZPmZ_UNDEF_B
|
|
0U, // CLS_ZPmZ_UNDEF_D
|
|
0U, // CLS_ZPmZ_UNDEF_H
|
|
0U, // CLS_ZPmZ_UNDEF_S
|
|
0U, // CLZ_ZPmZ_UNDEF_B
|
|
0U, // CLZ_ZPmZ_UNDEF_D
|
|
0U, // CLZ_ZPmZ_UNDEF_H
|
|
0U, // CLZ_ZPmZ_UNDEF_S
|
|
0U, // CMP_SWAP_128
|
|
0U, // CMP_SWAP_128_ACQUIRE
|
|
0U, // CMP_SWAP_128_MONOTONIC
|
|
0U, // CMP_SWAP_128_RELEASE
|
|
0U, // CMP_SWAP_16
|
|
0U, // CMP_SWAP_32
|
|
0U, // CMP_SWAP_64
|
|
0U, // CMP_SWAP_8
|
|
0U, // CNOT_ZPmZ_UNDEF_B
|
|
0U, // CNOT_ZPmZ_UNDEF_D
|
|
0U, // CNOT_ZPmZ_UNDEF_H
|
|
0U, // CNOT_ZPmZ_UNDEF_S
|
|
0U, // CNT_ZPmZ_UNDEF_B
|
|
0U, // CNT_ZPmZ_UNDEF_D
|
|
0U, // CNT_ZPmZ_UNDEF_H
|
|
0U, // CNT_ZPmZ_UNDEF_S
|
|
0U, // CompilerBarrier
|
|
0U, // EMITBKEY
|
|
0U, // EONWrr
|
|
0U, // EONXrr
|
|
0U, // EORWrr
|
|
0U, // EORXrr
|
|
0U, // F128CSEL
|
|
0U, // FABD_ZPZZ_UNDEF_D
|
|
0U, // FABD_ZPZZ_UNDEF_H
|
|
0U, // FABD_ZPZZ_UNDEF_S
|
|
0U, // FABD_ZPZZ_ZERO_D
|
|
0U, // FABD_ZPZZ_ZERO_H
|
|
0U, // FABD_ZPZZ_ZERO_S
|
|
0U, // FABS_ZPmZ_UNDEF_D
|
|
0U, // FABS_ZPmZ_UNDEF_H
|
|
0U, // FABS_ZPmZ_UNDEF_S
|
|
0U, // FADD_ZPZI_UNDEF_D
|
|
0U, // FADD_ZPZI_UNDEF_H
|
|
0U, // FADD_ZPZI_UNDEF_S
|
|
0U, // FADD_ZPZI_ZERO_D
|
|
0U, // FADD_ZPZI_ZERO_H
|
|
0U, // FADD_ZPZI_ZERO_S
|
|
0U, // FADD_ZPZZ_UNDEF_D
|
|
0U, // FADD_ZPZZ_UNDEF_H
|
|
0U, // FADD_ZPZZ_UNDEF_S
|
|
0U, // FADD_ZPZZ_ZERO_D
|
|
0U, // FADD_ZPZZ_ZERO_H
|
|
0U, // FADD_ZPZZ_ZERO_S
|
|
0U, // FCVTZS_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZS_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZS_ZPmZ_StoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoH_UNDEF
|
|
0U, // FCVTZU_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoD_UNDEF
|
|
0U, // FCVTZU_ZPmZ_StoS_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoH_UNDEF
|
|
0U, // FCVT_ZPmZ_DtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoD_UNDEF
|
|
0U, // FCVT_ZPmZ_HtoS_UNDEF
|
|
0U, // FCVT_ZPmZ_StoD_UNDEF
|
|
0U, // FCVT_ZPmZ_StoH_UNDEF
|
|
0U, // FDIVR_ZPZZ_ZERO_D
|
|
0U, // FDIVR_ZPZZ_ZERO_H
|
|
0U, // FDIVR_ZPZZ_ZERO_S
|
|
0U, // FDIV_ZPZZ_UNDEF_D
|
|
0U, // FDIV_ZPZZ_UNDEF_H
|
|
0U, // FDIV_ZPZZ_UNDEF_S
|
|
0U, // FDIV_ZPZZ_ZERO_D
|
|
0U, // FDIV_ZPZZ_ZERO_H
|
|
0U, // FDIV_ZPZZ_ZERO_S
|
|
0U, // FMAXNM_ZPZI_UNDEF_D
|
|
0U, // FMAXNM_ZPZI_UNDEF_H
|
|
0U, // FMAXNM_ZPZI_UNDEF_S
|
|
0U, // FMAXNM_ZPZI_ZERO_D
|
|
0U, // FMAXNM_ZPZI_ZERO_H
|
|
0U, // FMAXNM_ZPZI_ZERO_S
|
|
0U, // FMAXNM_ZPZZ_UNDEF_D
|
|
0U, // FMAXNM_ZPZZ_UNDEF_H
|
|
0U, // FMAXNM_ZPZZ_UNDEF_S
|
|
0U, // FMAXNM_ZPZZ_ZERO_D
|
|
0U, // FMAXNM_ZPZZ_ZERO_H
|
|
0U, // FMAXNM_ZPZZ_ZERO_S
|
|
0U, // FMAX_ZPZI_UNDEF_D
|
|
0U, // FMAX_ZPZI_UNDEF_H
|
|
0U, // FMAX_ZPZI_UNDEF_S
|
|
0U, // FMAX_ZPZI_ZERO_D
|
|
0U, // FMAX_ZPZI_ZERO_H
|
|
0U, // FMAX_ZPZI_ZERO_S
|
|
0U, // FMAX_ZPZZ_UNDEF_D
|
|
0U, // FMAX_ZPZZ_UNDEF_H
|
|
0U, // FMAX_ZPZZ_UNDEF_S
|
|
0U, // FMAX_ZPZZ_ZERO_D
|
|
0U, // FMAX_ZPZZ_ZERO_H
|
|
0U, // FMAX_ZPZZ_ZERO_S
|
|
0U, // FMINNM_ZPZI_UNDEF_D
|
|
0U, // FMINNM_ZPZI_UNDEF_H
|
|
0U, // FMINNM_ZPZI_UNDEF_S
|
|
0U, // FMINNM_ZPZI_ZERO_D
|
|
0U, // FMINNM_ZPZI_ZERO_H
|
|
0U, // FMINNM_ZPZI_ZERO_S
|
|
0U, // FMINNM_ZPZZ_UNDEF_D
|
|
0U, // FMINNM_ZPZZ_UNDEF_H
|
|
0U, // FMINNM_ZPZZ_UNDEF_S
|
|
0U, // FMINNM_ZPZZ_ZERO_D
|
|
0U, // FMINNM_ZPZZ_ZERO_H
|
|
0U, // FMINNM_ZPZZ_ZERO_S
|
|
0U, // FMIN_ZPZI_UNDEF_D
|
|
0U, // FMIN_ZPZI_UNDEF_H
|
|
0U, // FMIN_ZPZI_UNDEF_S
|
|
0U, // FMIN_ZPZI_ZERO_D
|
|
0U, // FMIN_ZPZI_ZERO_H
|
|
0U, // FMIN_ZPZI_ZERO_S
|
|
0U, // FMIN_ZPZZ_UNDEF_D
|
|
0U, // FMIN_ZPZZ_UNDEF_H
|
|
0U, // FMIN_ZPZZ_UNDEF_S
|
|
0U, // FMIN_ZPZZ_ZERO_D
|
|
0U, // FMIN_ZPZZ_ZERO_H
|
|
0U, // FMIN_ZPZZ_ZERO_S
|
|
0U, // FMLA_ZPZZZ_UNDEF_D
|
|
0U, // FMLA_ZPZZZ_UNDEF_H
|
|
0U, // FMLA_ZPZZZ_UNDEF_S
|
|
0U, // FMLS_ZPZZZ_UNDEF_D
|
|
0U, // FMLS_ZPZZZ_UNDEF_H
|
|
0U, // FMLS_ZPZZZ_UNDEF_S
|
|
0U, // FMOVD0
|
|
0U, // FMOVH0
|
|
0U, // FMOVS0
|
|
0U, // FMULX_ZPZZ_ZERO_D
|
|
0U, // FMULX_ZPZZ_ZERO_H
|
|
0U, // FMULX_ZPZZ_ZERO_S
|
|
0U, // FMUL_ZPZI_UNDEF_D
|
|
0U, // FMUL_ZPZI_UNDEF_H
|
|
0U, // FMUL_ZPZI_UNDEF_S
|
|
0U, // FMUL_ZPZI_ZERO_D
|
|
0U, // FMUL_ZPZI_ZERO_H
|
|
0U, // FMUL_ZPZI_ZERO_S
|
|
0U, // FMUL_ZPZZ_UNDEF_D
|
|
0U, // FMUL_ZPZZ_UNDEF_H
|
|
0U, // FMUL_ZPZZ_UNDEF_S
|
|
0U, // FMUL_ZPZZ_ZERO_D
|
|
0U, // FMUL_ZPZZ_ZERO_H
|
|
0U, // FMUL_ZPZZ_ZERO_S
|
|
0U, // FNEG_ZPmZ_UNDEF_D
|
|
0U, // FNEG_ZPmZ_UNDEF_H
|
|
0U, // FNEG_ZPmZ_UNDEF_S
|
|
0U, // FNMLA_ZPZZZ_UNDEF_D
|
|
0U, // FNMLA_ZPZZZ_UNDEF_H
|
|
0U, // FNMLA_ZPZZZ_UNDEF_S
|
|
0U, // FNMLS_ZPZZZ_UNDEF_D
|
|
0U, // FNMLS_ZPZZZ_UNDEF_H
|
|
0U, // FNMLS_ZPZZZ_UNDEF_S
|
|
0U, // FRECPX_ZPmZ_UNDEF_D
|
|
0U, // FRECPX_ZPmZ_UNDEF_H
|
|
0U, // FRECPX_ZPmZ_UNDEF_S
|
|
0U, // FRINTA_ZPmZ_UNDEF_D
|
|
0U, // FRINTA_ZPmZ_UNDEF_H
|
|
0U, // FRINTA_ZPmZ_UNDEF_S
|
|
0U, // FRINTI_ZPmZ_UNDEF_D
|
|
0U, // FRINTI_ZPmZ_UNDEF_H
|
|
0U, // FRINTI_ZPmZ_UNDEF_S
|
|
0U, // FRINTM_ZPmZ_UNDEF_D
|
|
0U, // FRINTM_ZPmZ_UNDEF_H
|
|
0U, // FRINTM_ZPmZ_UNDEF_S
|
|
0U, // FRINTN_ZPmZ_UNDEF_D
|
|
0U, // FRINTN_ZPmZ_UNDEF_H
|
|
0U, // FRINTN_ZPmZ_UNDEF_S
|
|
0U, // FRINTP_ZPmZ_UNDEF_D
|
|
0U, // FRINTP_ZPmZ_UNDEF_H
|
|
0U, // FRINTP_ZPmZ_UNDEF_S
|
|
0U, // FRINTX_ZPmZ_UNDEF_D
|
|
0U, // FRINTX_ZPmZ_UNDEF_H
|
|
0U, // FRINTX_ZPmZ_UNDEF_S
|
|
0U, // FRINTZ_ZPmZ_UNDEF_D
|
|
0U, // FRINTZ_ZPmZ_UNDEF_H
|
|
0U, // FRINTZ_ZPmZ_UNDEF_S
|
|
0U, // FSQRT_ZPmZ_UNDEF_D
|
|
0U, // FSQRT_ZPmZ_UNDEF_H
|
|
0U, // FSQRT_ZPmZ_UNDEF_S
|
|
0U, // FSUBR_ZPZI_UNDEF_D
|
|
0U, // FSUBR_ZPZI_UNDEF_H
|
|
0U, // FSUBR_ZPZI_UNDEF_S
|
|
0U, // FSUBR_ZPZI_ZERO_D
|
|
0U, // FSUBR_ZPZI_ZERO_H
|
|
0U, // FSUBR_ZPZI_ZERO_S
|
|
0U, // FSUBR_ZPZZ_ZERO_D
|
|
0U, // FSUBR_ZPZZ_ZERO_H
|
|
0U, // FSUBR_ZPZZ_ZERO_S
|
|
0U, // FSUB_ZPZI_UNDEF_D
|
|
0U, // FSUB_ZPZI_UNDEF_H
|
|
0U, // FSUB_ZPZI_UNDEF_S
|
|
0U, // FSUB_ZPZI_ZERO_D
|
|
0U, // FSUB_ZPZI_ZERO_H
|
|
0U, // FSUB_ZPZI_ZERO_S
|
|
0U, // FSUB_ZPZZ_UNDEF_D
|
|
0U, // FSUB_ZPZZ_UNDEF_H
|
|
0U, // FSUB_ZPZZ_UNDEF_S
|
|
0U, // FSUB_ZPZZ_ZERO_D
|
|
0U, // FSUB_ZPZZ_ZERO_H
|
|
0U, // FSUB_ZPZZ_ZERO_S
|
|
0U, // GLD1B_D
|
|
0U, // GLD1B_D_IMM
|
|
0U, // GLD1B_D_SXTW
|
|
0U, // GLD1B_D_UXTW
|
|
0U, // GLD1B_S_IMM
|
|
0U, // GLD1B_S_SXTW
|
|
0U, // GLD1B_S_UXTW
|
|
0U, // GLD1D
|
|
0U, // GLD1D_IMM
|
|
0U, // GLD1D_SCALED
|
|
0U, // GLD1D_SXTW
|
|
0U, // GLD1D_SXTW_SCALED
|
|
0U, // GLD1D_UXTW
|
|
0U, // GLD1D_UXTW_SCALED
|
|
0U, // GLD1H_D
|
|
0U, // GLD1H_D_IMM
|
|
0U, // GLD1H_D_SCALED
|
|
0U, // GLD1H_D_SXTW
|
|
0U, // GLD1H_D_SXTW_SCALED
|
|
0U, // GLD1H_D_UXTW
|
|
0U, // GLD1H_D_UXTW_SCALED
|
|
0U, // GLD1H_S_IMM
|
|
0U, // GLD1H_S_SXTW
|
|
0U, // GLD1H_S_SXTW_SCALED
|
|
0U, // GLD1H_S_UXTW
|
|
0U, // GLD1H_S_UXTW_SCALED
|
|
0U, // GLD1SB_D
|
|
0U, // GLD1SB_D_IMM
|
|
0U, // GLD1SB_D_SXTW
|
|
0U, // GLD1SB_D_UXTW
|
|
0U, // GLD1SB_S_IMM
|
|
0U, // GLD1SB_S_SXTW
|
|
0U, // GLD1SB_S_UXTW
|
|
0U, // GLD1SH_D
|
|
0U, // GLD1SH_D_IMM
|
|
0U, // GLD1SH_D_SCALED
|
|
0U, // GLD1SH_D_SXTW
|
|
0U, // GLD1SH_D_SXTW_SCALED
|
|
0U, // GLD1SH_D_UXTW
|
|
0U, // GLD1SH_D_UXTW_SCALED
|
|
0U, // GLD1SH_S_IMM
|
|
0U, // GLD1SH_S_SXTW
|
|
0U, // GLD1SH_S_SXTW_SCALED
|
|
0U, // GLD1SH_S_UXTW
|
|
0U, // GLD1SH_S_UXTW_SCALED
|
|
0U, // GLD1SW_D
|
|
0U, // GLD1SW_D_IMM
|
|
0U, // GLD1SW_D_SCALED
|
|
0U, // GLD1SW_D_SXTW
|
|
0U, // GLD1SW_D_SXTW_SCALED
|
|
0U, // GLD1SW_D_UXTW
|
|
0U, // GLD1SW_D_UXTW_SCALED
|
|
0U, // GLD1W_D
|
|
0U, // GLD1W_D_IMM
|
|
0U, // GLD1W_D_SCALED
|
|
0U, // GLD1W_D_SXTW
|
|
0U, // GLD1W_D_SXTW_SCALED
|
|
0U, // GLD1W_D_UXTW
|
|
0U, // GLD1W_D_UXTW_SCALED
|
|
0U, // GLD1W_IMM
|
|
0U, // GLD1W_SXTW
|
|
0U, // GLD1W_SXTW_SCALED
|
|
0U, // GLD1W_UXTW
|
|
0U, // GLD1W_UXTW_SCALED
|
|
0U, // GLDFF1B_D
|
|
0U, // GLDFF1B_D_IMM
|
|
0U, // GLDFF1B_D_SXTW
|
|
0U, // GLDFF1B_D_UXTW
|
|
0U, // GLDFF1B_S_IMM
|
|
0U, // GLDFF1B_S_SXTW
|
|
0U, // GLDFF1B_S_UXTW
|
|
0U, // GLDFF1D
|
|
0U, // GLDFF1D_IMM
|
|
0U, // GLDFF1D_SCALED
|
|
0U, // GLDFF1D_SXTW
|
|
0U, // GLDFF1D_SXTW_SCALED
|
|
0U, // GLDFF1D_UXTW
|
|
0U, // GLDFF1D_UXTW_SCALED
|
|
0U, // GLDFF1H_D
|
|
0U, // GLDFF1H_D_IMM
|
|
0U, // GLDFF1H_D_SCALED
|
|
0U, // GLDFF1H_D_SXTW
|
|
0U, // GLDFF1H_D_SXTW_SCALED
|
|
0U, // GLDFF1H_D_UXTW
|
|
0U, // GLDFF1H_D_UXTW_SCALED
|
|
0U, // GLDFF1H_S_IMM
|
|
0U, // GLDFF1H_S_SXTW
|
|
0U, // GLDFF1H_S_SXTW_SCALED
|
|
0U, // GLDFF1H_S_UXTW
|
|
0U, // GLDFF1H_S_UXTW_SCALED
|
|
0U, // GLDFF1SB_D
|
|
0U, // GLDFF1SB_D_IMM
|
|
0U, // GLDFF1SB_D_SXTW
|
|
0U, // GLDFF1SB_D_UXTW
|
|
0U, // GLDFF1SB_S_IMM
|
|
0U, // GLDFF1SB_S_SXTW
|
|
0U, // GLDFF1SB_S_UXTW
|
|
0U, // GLDFF1SH_D
|
|
0U, // GLDFF1SH_D_IMM
|
|
0U, // GLDFF1SH_D_SCALED
|
|
0U, // GLDFF1SH_D_SXTW
|
|
0U, // GLDFF1SH_D_SXTW_SCALED
|
|
0U, // GLDFF1SH_D_UXTW
|
|
0U, // GLDFF1SH_D_UXTW_SCALED
|
|
0U, // GLDFF1SH_S_IMM
|
|
0U, // GLDFF1SH_S_SXTW
|
|
0U, // GLDFF1SH_S_SXTW_SCALED
|
|
0U, // GLDFF1SH_S_UXTW
|
|
0U, // GLDFF1SH_S_UXTW_SCALED
|
|
0U, // GLDFF1SW_D
|
|
0U, // GLDFF1SW_D_IMM
|
|
0U, // GLDFF1SW_D_SCALED
|
|
0U, // GLDFF1SW_D_SXTW
|
|
0U, // GLDFF1SW_D_SXTW_SCALED
|
|
0U, // GLDFF1SW_D_UXTW
|
|
0U, // GLDFF1SW_D_UXTW_SCALED
|
|
0U, // GLDFF1W_D
|
|
0U, // GLDFF1W_D_IMM
|
|
0U, // GLDFF1W_D_SCALED
|
|
0U, // GLDFF1W_D_SXTW
|
|
0U, // GLDFF1W_D_SXTW_SCALED
|
|
0U, // GLDFF1W_D_UXTW
|
|
0U, // GLDFF1W_D_UXTW_SCALED
|
|
0U, // GLDFF1W_IMM
|
|
0U, // GLDFF1W_SXTW
|
|
0U, // GLDFF1W_SXTW_SCALED
|
|
0U, // GLDFF1W_UXTW
|
|
0U, // GLDFF1W_UXTW_SCALED
|
|
0U, // G_ADD_LOW
|
|
0U, // G_DUP
|
|
0U, // G_DUPLANE16
|
|
0U, // G_DUPLANE32
|
|
0U, // G_DUPLANE64
|
|
0U, // G_DUPLANE8
|
|
0U, // G_EXT
|
|
0U, // G_FCMEQ
|
|
0U, // G_FCMEQZ
|
|
0U, // G_FCMGE
|
|
0U, // G_FCMGEZ
|
|
0U, // G_FCMGT
|
|
0U, // G_FCMGTZ
|
|
0U, // G_FCMLEZ
|
|
0U, // G_FCMLTZ
|
|
0U, // G_REV16
|
|
0U, // G_REV32
|
|
0U, // G_REV64
|
|
0U, // G_SITOF
|
|
0U, // G_TRN1
|
|
0U, // G_TRN2
|
|
0U, // G_UITOF
|
|
0U, // G_UZP1
|
|
0U, // G_UZP2
|
|
0U, // G_VASHR
|
|
0U, // G_VLSHR
|
|
0U, // G_ZIP1
|
|
0U, // G_ZIP2
|
|
0U, // HOM_Epilog
|
|
0U, // HOM_Prolog
|
|
0U, // HWASAN_CHECK_MEMACCESS
|
|
0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
|
|
0U, // IRGstack
|
|
0U, // JumpTableDest16
|
|
0U, // JumpTableDest32
|
|
0U, // JumpTableDest8
|
|
0U, // LD1B_D_IMM
|
|
0U, // LD1B_H_IMM
|
|
0U, // LD1B_IMM
|
|
0U, // LD1B_S_IMM
|
|
0U, // LD1D_IMM
|
|
0U, // LD1H_D_IMM
|
|
0U, // LD1H_IMM
|
|
0U, // LD1H_S_IMM
|
|
0U, // LD1SB_D_IMM
|
|
0U, // LD1SB_H_IMM
|
|
0U, // LD1SB_S_IMM
|
|
0U, // LD1SH_D_IMM
|
|
0U, // LD1SH_S_IMM
|
|
0U, // LD1SW_D_IMM
|
|
0U, // LD1W_D_IMM
|
|
0U, // LD1W_IMM
|
|
0U, // LDFF1B
|
|
0U, // LDFF1B_D
|
|
0U, // LDFF1B_H
|
|
0U, // LDFF1B_S
|
|
0U, // LDFF1D
|
|
0U, // LDFF1H
|
|
0U, // LDFF1H_D
|
|
0U, // LDFF1H_S
|
|
0U, // LDFF1SB_D
|
|
0U, // LDFF1SB_H
|
|
0U, // LDFF1SB_S
|
|
0U, // LDFF1SH_D
|
|
0U, // LDFF1SH_S
|
|
0U, // LDFF1SW_D
|
|
0U, // LDFF1W
|
|
0U, // LDFF1W_D
|
|
0U, // LDNF1B_D_IMM
|
|
0U, // LDNF1B_H_IMM
|
|
0U, // LDNF1B_IMM
|
|
0U, // LDNF1B_S_IMM
|
|
0U, // LDNF1D_IMM
|
|
0U, // LDNF1H_D_IMM
|
|
0U, // LDNF1H_IMM
|
|
0U, // LDNF1H_S_IMM
|
|
0U, // LDNF1SB_D_IMM
|
|
0U, // LDNF1SB_H_IMM
|
|
0U, // LDNF1SB_S_IMM
|
|
0U, // LDNF1SH_D_IMM
|
|
0U, // LDNF1SH_S_IMM
|
|
0U, // LDNF1SW_D_IMM
|
|
0U, // LDNF1W_D_IMM
|
|
0U, // LDNF1W_IMM
|
|
0U, // LDR_ZZXI
|
|
0U, // LDR_ZZZXI
|
|
0U, // LDR_ZZZZXI
|
|
0U, // LOADgot
|
|
0U, // LSL_ZPZI_UNDEF_B
|
|
0U, // LSL_ZPZI_UNDEF_D
|
|
0U, // LSL_ZPZI_UNDEF_H
|
|
0U, // LSL_ZPZI_UNDEF_S
|
|
0U, // LSL_ZPZZ_UNDEF_B
|
|
0U, // LSL_ZPZZ_UNDEF_D
|
|
0U, // LSL_ZPZZ_UNDEF_H
|
|
0U, // LSL_ZPZZ_UNDEF_S
|
|
0U, // LSL_ZPZZ_ZERO_B
|
|
0U, // LSL_ZPZZ_ZERO_D
|
|
0U, // LSL_ZPZZ_ZERO_H
|
|
0U, // LSL_ZPZZ_ZERO_S
|
|
0U, // LSR_ZPZI_UNDEF_B
|
|
0U, // LSR_ZPZI_UNDEF_D
|
|
0U, // LSR_ZPZI_UNDEF_H
|
|
0U, // LSR_ZPZI_UNDEF_S
|
|
0U, // LSR_ZPZZ_UNDEF_B
|
|
0U, // LSR_ZPZZ_UNDEF_D
|
|
0U, // LSR_ZPZZ_UNDEF_H
|
|
0U, // LSR_ZPZZ_UNDEF_S
|
|
0U, // LSR_ZPZZ_ZERO_B
|
|
0U, // LSR_ZPZZ_ZERO_D
|
|
0U, // LSR_ZPZZ_ZERO_H
|
|
0U, // LSR_ZPZZ_ZERO_S
|
|
0U, // MOPSMemoryCopyPseudo
|
|
0U, // MOPSMemoryMovePseudo
|
|
0U, // MOPSMemorySetPseudo
|
|
0U, // MOPSMemorySetTaggingPseudo
|
|
0U, // MOVMCSym
|
|
0U, // MOVaddr
|
|
0U, // MOVaddrBA
|
|
0U, // MOVaddrCP
|
|
0U, // MOVaddrEXT
|
|
0U, // MOVaddrJT
|
|
0U, // MOVaddrTLS
|
|
0U, // MOVbaseTLS
|
|
0U, // MOVi32imm
|
|
0U, // MOVi64imm
|
|
0U, // MUL_ZPZZ_UNDEF_B
|
|
0U, // MUL_ZPZZ_UNDEF_D
|
|
0U, // MUL_ZPZZ_UNDEF_H
|
|
0U, // MUL_ZPZZ_UNDEF_S
|
|
0U, // NEG_ZPmZ_UNDEF_B
|
|
0U, // NEG_ZPmZ_UNDEF_D
|
|
0U, // NEG_ZPmZ_UNDEF_H
|
|
0U, // NEG_ZPmZ_UNDEF_S
|
|
0U, // NOT_ZPmZ_UNDEF_B
|
|
0U, // NOT_ZPmZ_UNDEF_D
|
|
0U, // NOT_ZPmZ_UNDEF_H
|
|
0U, // NOT_ZPmZ_UNDEF_S
|
|
0U, // ORNWrr
|
|
0U, // ORNXrr
|
|
0U, // ORRWrr
|
|
0U, // ORRXrr
|
|
0U, // RDFFR_P
|
|
0U, // RDFFR_PPz
|
|
0U, // RET_ReallyLR
|
|
0U, // SABD_ZPZZ_UNDEF_B
|
|
0U, // SABD_ZPZZ_UNDEF_D
|
|
0U, // SABD_ZPZZ_UNDEF_H
|
|
0U, // SABD_ZPZZ_UNDEF_S
|
|
0U, // SCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // SCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // SCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // SDIV_ZPZZ_UNDEF_D
|
|
0U, // SDIV_ZPZZ_UNDEF_S
|
|
0U, // SEH_AddFP
|
|
0U, // SEH_EpilogEnd
|
|
0U, // SEH_EpilogStart
|
|
0U, // SEH_Nop
|
|
0U, // SEH_PrologEnd
|
|
0U, // SEH_SaveFPLR
|
|
0U, // SEH_SaveFPLR_X
|
|
0U, // SEH_SaveFReg
|
|
0U, // SEH_SaveFRegP
|
|
0U, // SEH_SaveFRegP_X
|
|
0U, // SEH_SaveFReg_X
|
|
0U, // SEH_SaveReg
|
|
0U, // SEH_SaveRegP
|
|
0U, // SEH_SaveRegP_X
|
|
0U, // SEH_SaveReg_X
|
|
0U, // SEH_SetFP
|
|
0U, // SEH_StackAlloc
|
|
0U, // SMAX_ZPZZ_UNDEF_B
|
|
0U, // SMAX_ZPZZ_UNDEF_D
|
|
0U, // SMAX_ZPZZ_UNDEF_H
|
|
0U, // SMAX_ZPZZ_UNDEF_S
|
|
0U, // SMIN_ZPZZ_UNDEF_B
|
|
0U, // SMIN_ZPZZ_UNDEF_D
|
|
0U, // SMIN_ZPZZ_UNDEF_H
|
|
0U, // SMIN_ZPZZ_UNDEF_S
|
|
0U, // SMULH_ZPZZ_UNDEF_B
|
|
0U, // SMULH_ZPZZ_UNDEF_D
|
|
0U, // SMULH_ZPZZ_UNDEF_H
|
|
0U, // SMULH_ZPZZ_UNDEF_S
|
|
0U, // SPACE
|
|
0U, // SQABS_ZPmZ_UNDEF_B
|
|
0U, // SQABS_ZPmZ_UNDEF_D
|
|
0U, // SQABS_ZPmZ_UNDEF_H
|
|
0U, // SQABS_ZPmZ_UNDEF_S
|
|
0U, // SQNEG_ZPmZ_UNDEF_B
|
|
0U, // SQNEG_ZPmZ_UNDEF_D
|
|
0U, // SQNEG_ZPmZ_UNDEF_H
|
|
0U, // SQNEG_ZPmZ_UNDEF_S
|
|
0U, // SQRSHL_ZPZZ_UNDEF_B
|
|
0U, // SQRSHL_ZPZZ_UNDEF_D
|
|
0U, // SQRSHL_ZPZZ_UNDEF_H
|
|
0U, // SQRSHL_ZPZZ_UNDEF_S
|
|
0U, // SQSHLU_ZPZI_ZERO_B
|
|
0U, // SQSHLU_ZPZI_ZERO_D
|
|
0U, // SQSHLU_ZPZI_ZERO_H
|
|
0U, // SQSHLU_ZPZI_ZERO_S
|
|
0U, // SQSHL_ZPZI_ZERO_B
|
|
0U, // SQSHL_ZPZI_ZERO_D
|
|
0U, // SQSHL_ZPZI_ZERO_H
|
|
0U, // SQSHL_ZPZI_ZERO_S
|
|
0U, // SQSHL_ZPZZ_UNDEF_B
|
|
0U, // SQSHL_ZPZZ_UNDEF_D
|
|
0U, // SQSHL_ZPZZ_UNDEF_H
|
|
0U, // SQSHL_ZPZZ_UNDEF_S
|
|
0U, // SRSHL_ZPZZ_UNDEF_B
|
|
0U, // SRSHL_ZPZZ_UNDEF_D
|
|
0U, // SRSHL_ZPZZ_UNDEF_H
|
|
0U, // SRSHL_ZPZZ_UNDEF_S
|
|
0U, // SRSHR_ZPZI_ZERO_B
|
|
0U, // SRSHR_ZPZI_ZERO_D
|
|
0U, // SRSHR_ZPZI_ZERO_H
|
|
0U, // SRSHR_ZPZI_ZERO_S
|
|
0U, // STGloop
|
|
0U, // STGloop_wback
|
|
0U, // STR_ZZXI
|
|
0U, // STR_ZZZXI
|
|
0U, // STR_ZZZZXI
|
|
0U, // STZGloop
|
|
0U, // STZGloop_wback
|
|
0U, // SUBR_ZPZZ_ZERO_B
|
|
0U, // SUBR_ZPZZ_ZERO_D
|
|
0U, // SUBR_ZPZZ_ZERO_H
|
|
0U, // SUBR_ZPZZ_ZERO_S
|
|
0U, // SUBSWrr
|
|
0U, // SUBSXrr
|
|
0U, // SUBWrr
|
|
0U, // SUBXrr
|
|
0U, // SUB_ZPZZ_UNDEF_B
|
|
0U, // SUB_ZPZZ_UNDEF_D
|
|
0U, // SUB_ZPZZ_UNDEF_H
|
|
0U, // SUB_ZPZZ_UNDEF_S
|
|
0U, // SUB_ZPZZ_ZERO_B
|
|
0U, // SUB_ZPZZ_ZERO_D
|
|
0U, // SUB_ZPZZ_ZERO_H
|
|
0U, // SUB_ZPZZ_ZERO_S
|
|
0U, // SXTB_ZPmZ_UNDEF_D
|
|
0U, // SXTB_ZPmZ_UNDEF_H
|
|
0U, // SXTB_ZPmZ_UNDEF_S
|
|
0U, // SXTH_ZPmZ_UNDEF_D
|
|
0U, // SXTH_ZPmZ_UNDEF_S
|
|
0U, // SXTW_ZPmZ_UNDEF_D
|
|
0U, // SpeculationBarrierISBDSBEndBB
|
|
0U, // SpeculationBarrierSBEndBB
|
|
0U, // SpeculationSafeValueW
|
|
0U, // SpeculationSafeValueX
|
|
0U, // StoreSwiftAsyncContext
|
|
0U, // TAGPstack
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNriALL
|
|
0U, // TCRETURNriBTI
|
|
0U, // TLSDESCCALL
|
|
0U, // TLSDESC_CALLSEQ
|
|
0U, // UABD_ZPZZ_UNDEF_B
|
|
0U, // UABD_ZPZZ_UNDEF_D
|
|
0U, // UABD_ZPZZ_UNDEF_H
|
|
0U, // UABD_ZPZZ_UNDEF_S
|
|
0U, // UCVTF_ZPmZ_DtoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_DtoS_UNDEF
|
|
0U, // UCVTF_ZPmZ_HtoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoD_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoH_UNDEF
|
|
0U, // UCVTF_ZPmZ_StoS_UNDEF
|
|
0U, // UDIV_ZPZZ_UNDEF_D
|
|
0U, // UDIV_ZPZZ_UNDEF_S
|
|
0U, // UMAX_ZPZZ_UNDEF_B
|
|
0U, // UMAX_ZPZZ_UNDEF_D
|
|
0U, // UMAX_ZPZZ_UNDEF_H
|
|
0U, // UMAX_ZPZZ_UNDEF_S
|
|
0U, // UMIN_ZPZZ_UNDEF_B
|
|
0U, // UMIN_ZPZZ_UNDEF_D
|
|
0U, // UMIN_ZPZZ_UNDEF_H
|
|
0U, // UMIN_ZPZZ_UNDEF_S
|
|
0U, // UMULH_ZPZZ_UNDEF_B
|
|
0U, // UMULH_ZPZZ_UNDEF_D
|
|
0U, // UMULH_ZPZZ_UNDEF_H
|
|
0U, // UMULH_ZPZZ_UNDEF_S
|
|
0U, // UQRSHL_ZPZZ_UNDEF_B
|
|
0U, // UQRSHL_ZPZZ_UNDEF_D
|
|
0U, // UQRSHL_ZPZZ_UNDEF_H
|
|
0U, // UQRSHL_ZPZZ_UNDEF_S
|
|
0U, // UQSHL_ZPZI_ZERO_B
|
|
0U, // UQSHL_ZPZI_ZERO_D
|
|
0U, // UQSHL_ZPZI_ZERO_H
|
|
0U, // UQSHL_ZPZI_ZERO_S
|
|
0U, // UQSHL_ZPZZ_UNDEF_B
|
|
0U, // UQSHL_ZPZZ_UNDEF_D
|
|
0U, // UQSHL_ZPZZ_UNDEF_H
|
|
0U, // UQSHL_ZPZZ_UNDEF_S
|
|
0U, // URECPE_ZPmZ_UNDEF_S
|
|
0U, // URSHL_ZPZZ_UNDEF_B
|
|
0U, // URSHL_ZPZZ_UNDEF_D
|
|
0U, // URSHL_ZPZZ_UNDEF_H
|
|
0U, // URSHL_ZPZZ_UNDEF_S
|
|
0U, // URSHR_ZPZI_ZERO_B
|
|
0U, // URSHR_ZPZI_ZERO_D
|
|
0U, // URSHR_ZPZI_ZERO_H
|
|
0U, // URSHR_ZPZI_ZERO_S
|
|
0U, // URSQRTE_ZPmZ_UNDEF_S
|
|
0U, // UXTB_ZPmZ_UNDEF_D
|
|
0U, // UXTB_ZPmZ_UNDEF_H
|
|
0U, // UXTB_ZPmZ_UNDEF_S
|
|
0U, // UXTH_ZPmZ_UNDEF_D
|
|
0U, // UXTH_ZPmZ_UNDEF_S
|
|
0U, // UXTW_ZPmZ_UNDEF_D
|
|
0U, // ABS_ZPmZ_B
|
|
8U, // ABS_ZPmZ_D
|
|
0U, // ABS_ZPmZ_H
|
|
16U, // ABS_ZPmZ_S
|
|
24U, // ABSv16i8
|
|
32U, // ABSv1i64
|
|
40U, // ABSv2i32
|
|
48U, // ABSv2i64
|
|
56U, // ABSv4i16
|
|
64U, // ABSv4i32
|
|
72U, // ABSv8i16
|
|
80U, // ABSv8i8
|
|
1112U, // ADCLB_ZZZ_D
|
|
2136U, // ADCLB_ZZZ_S
|
|
1112U, // ADCLT_ZZZ_D
|
|
2136U, // ADCLT_ZZZ_S
|
|
3160U, // ADCSWr
|
|
3160U, // ADCSXr
|
|
3160U, // ADCWr
|
|
3160U, // ADCXr
|
|
135256U, // ADDG
|
|
0U, // ADDHA_MPPZ_D
|
|
0U, // ADDHA_MPPZ_S
|
|
5208U, // ADDHNB_ZZZ_B
|
|
96U, // ADDHNB_ZZZ_H
|
|
6232U, // ADDHNB_ZZZ_S
|
|
7256U, // ADDHNT_ZZZ_B
|
|
16U, // ADDHNT_ZZZ_H
|
|
1112U, // ADDHNT_ZZZ_S
|
|
270440U, // ADDHNv2i64_v2i32
|
|
271464U, // ADDHNv2i64_v4i32
|
|
401520U, // ADDHNv4i32_v4i16
|
|
402544U, // ADDHNv4i32_v8i16
|
|
533624U, // ADDHNv8i16_v16i8
|
|
532600U, // ADDHNv8i16_v8i8
|
|
3160U, // ADDPL_XXI
|
|
8530048U, // ADDP_ZPmZ_B
|
|
16914560U, // ADDP_ZPmZ_D
|
|
25832584U, // ADDP_ZPmZ_H
|
|
33697920U, // ADDP_ZPmZ_S
|
|
794768U, // ADDPv16i8
|
|
925848U, // ADDPv2i32
|
|
270440U, // ADDPv2i64
|
|
48U, // ADDPv2i64p
|
|
1056928U, // ADDPv4i16
|
|
401520U, // ADDPv4i32
|
|
532600U, // ADDPv8i16
|
|
1188008U, // ADDPv8i8
|
|
13400U, // ADDSWri
|
|
14424U, // ADDSWrs
|
|
15448U, // ADDSWrx
|
|
13400U, // ADDSXri
|
|
14424U, // ADDSXrs
|
|
15448U, // ADDSXrx
|
|
1313880U, // ADDSXrx64
|
|
0U, // ADDVA_MPPZ_D
|
|
0U, // ADDVA_MPPZ_S
|
|
3160U, // ADDVL_XXI
|
|
24U, // ADDVv16i8v
|
|
56U, // ADDVv4i16v
|
|
64U, // ADDVv4i32v
|
|
72U, // ADDVv8i16v
|
|
80U, // ADDVv8i8v
|
|
13400U, // ADDWri
|
|
14424U, // ADDWrs
|
|
15448U, // ADDWrx
|
|
13400U, // ADDXri
|
|
14424U, // ADDXrs
|
|
15448U, // ADDXrx
|
|
1313880U, // ADDXrx64
|
|
16472U, // ADD_ZI_B
|
|
17496U, // ADD_ZI_D
|
|
176U, // ADD_ZI_H
|
|
18520U, // ADD_ZI_S
|
|
8530048U, // ADD_ZPmZ_B
|
|
16914560U, // ADD_ZPmZ_D
|
|
25832584U, // ADD_ZPmZ_H
|
|
33697920U, // ADD_ZPmZ_S
|
|
10328U, // ADD_ZZZ_B
|
|
6232U, // ADD_ZZZ_D
|
|
136U, // ADD_ZZZ_H
|
|
12376U, // ADD_ZZZ_S
|
|
794768U, // ADDv16i8
|
|
3160U, // ADDv1i64
|
|
925848U, // ADDv2i32
|
|
270440U, // ADDv2i64
|
|
1056928U, // ADDv4i16
|
|
401520U, // ADDv4i32
|
|
532600U, // ADDv8i16
|
|
1188008U, // ADDv8i8
|
|
32U, // ADR
|
|
1U, // ADRP
|
|
19544U, // ADR_LSL_ZZZ_D_0
|
|
20568U, // ADR_LSL_ZZZ_D_1
|
|
21592U, // ADR_LSL_ZZZ_D_2
|
|
22616U, // ADR_LSL_ZZZ_D_3
|
|
23640U, // ADR_LSL_ZZZ_S_0
|
|
24664U, // ADR_LSL_ZZZ_S_1
|
|
25688U, // ADR_LSL_ZZZ_S_2
|
|
26712U, // ADR_LSL_ZZZ_S_3
|
|
27736U, // ADR_SXTW_ZZZ_D_0
|
|
28760U, // ADR_SXTW_ZZZ_D_1
|
|
29784U, // ADR_SXTW_ZZZ_D_2
|
|
30808U, // ADR_SXTW_ZZZ_D_3
|
|
31832U, // ADR_UXTW_ZZZ_D_0
|
|
32856U, // ADR_UXTW_ZZZ_D_1
|
|
33880U, // ADR_UXTW_ZZZ_D_2
|
|
34904U, // ADR_UXTW_ZZZ_D_3
|
|
10328U, // AESD_ZZZ_B
|
|
24U, // AESDrr
|
|
10328U, // AESE_ZZZ_B
|
|
24U, // AESErr
|
|
32U, // AESIMC_ZZ_B
|
|
24U, // AESIMCrr
|
|
32U, // AESMC_ZZ_B
|
|
24U, // AESMCrr
|
|
35928U, // ANDSWri
|
|
14424U, // ANDSWrs
|
|
36952U, // ANDSXri
|
|
14424U, // ANDSXrs
|
|
8530104U, // ANDS_PPzPP
|
|
0U, // ANDV_VPZ_B
|
|
0U, // ANDV_VPZ_D
|
|
0U, // ANDV_VPZ_H
|
|
0U, // ANDV_VPZ_S
|
|
35928U, // ANDWri
|
|
14424U, // ANDWrs
|
|
36952U, // ANDXri
|
|
14424U, // ANDXrs
|
|
8530104U, // AND_PPzPP
|
|
36952U, // AND_ZI
|
|
8530048U, // AND_ZPmZ_B
|
|
16914560U, // AND_ZPmZ_D
|
|
25832584U, // AND_ZPmZ_H
|
|
33697920U, // AND_ZPmZ_S
|
|
6232U, // AND_ZZZ
|
|
794768U, // ANDv16i8
|
|
1188008U, // ANDv8i8
|
|
141440U, // ASRD_ZPmI_B
|
|
137344U, // ASRD_ZPmI_D
|
|
1453192U, // ASRD_ZPmI_H
|
|
143488U, // ASRD_ZPmI_S
|
|
8530048U, // ASRR_ZPmZ_B
|
|
16914560U, // ASRR_ZPmZ_D
|
|
25832584U, // ASRR_ZPmZ_H
|
|
33697920U, // ASRR_ZPmZ_S
|
|
3160U, // ASRVWr
|
|
3160U, // ASRVXr
|
|
16918656U, // ASR_WIDE_ZPmZ_B
|
|
1584264U, // ASR_WIDE_ZPmZ_H
|
|
16920704U, // ASR_WIDE_ZPmZ_S
|
|
6232U, // ASR_WIDE_ZZZ_B
|
|
192U, // ASR_WIDE_ZZZ_H
|
|
6232U, // ASR_WIDE_ZZZ_S
|
|
141440U, // ASR_ZPmI_B
|
|
137344U, // ASR_ZPmI_D
|
|
1453192U, // ASR_ZPmI_H
|
|
143488U, // ASR_ZPmI_S
|
|
8530048U, // ASR_ZPmZ_B
|
|
16914560U, // ASR_ZPmZ_D
|
|
25832584U, // ASR_ZPmZ_H
|
|
33697920U, // ASR_ZPmZ_S
|
|
3160U, // ASR_ZZI_B
|
|
3160U, // ASR_ZZI_D
|
|
200U, // ASR_ZZI_H
|
|
3160U, // ASR_ZZI_S
|
|
33U, // AUTDA
|
|
33U, // AUTDB
|
|
0U, // AUTDZA
|
|
0U, // AUTDZB
|
|
33U, // AUTIA
|
|
0U, // AUTIA1716
|
|
0U, // AUTIASP
|
|
0U, // AUTIAZ
|
|
33U, // AUTIB
|
|
0U, // AUTIB1716
|
|
0U, // AUTIBSP
|
|
0U, // AUTIBZ
|
|
0U, // AUTIZA
|
|
0U, // AUTIZB
|
|
0U, // AXFLAG
|
|
0U, // B
|
|
580526224U, // BCAX
|
|
16914520U, // BCAX_ZZZZ
|
|
0U, // BCcc
|
|
10328U, // BDEP_ZZZ_B
|
|
6232U, // BDEP_ZZZ_D
|
|
136U, // BDEP_ZZZ_H
|
|
12376U, // BDEP_ZZZ_S
|
|
10328U, // BEXT_ZZZ_B
|
|
6232U, // BEXT_ZZZ_D
|
|
136U, // BEXT_ZZZ_H
|
|
12376U, // BEXT_ZZZ_S
|
|
1844384U, // BF16DOTlanev4bf16
|
|
1844344U, // BF16DOTlanev8bf16
|
|
32U, // BFCVT
|
|
64U, // BFCVTN
|
|
64U, // BFCVTN2
|
|
1U, // BFCVTNT_ZPmZ
|
|
1U, // BFCVT_ZPmZ
|
|
27139160U, // BFDOT_ZZI
|
|
7256U, // BFDOT_ZZZ
|
|
1057952U, // BFDOTv4bf16
|
|
533624U, // BFDOTv8bf16
|
|
533624U, // BFMLALB
|
|
52438136U, // BFMLALBIdx
|
|
533624U, // BFMLALT
|
|
52438136U, // BFMLALTIdx
|
|
533624U, // BFMMLA
|
|
27139160U, // BFMMLA_B_ZZI
|
|
7256U, // BFMMLA_B_ZZZ
|
|
27139160U, // BFMMLA_T_ZZI
|
|
7256U, // BFMMLA_T_ZZZ
|
|
7256U, // BFMMLA_ZZZ
|
|
58889305U, // BFMWri
|
|
58889305U, // BFMXri
|
|
10328U, // BGRP_ZZZ_B
|
|
6232U, // BGRP_ZZZ_D
|
|
136U, // BGRP_ZZZ_H
|
|
12376U, // BGRP_ZZZ_S
|
|
14424U, // BICSWrs
|
|
14424U, // BICSXrs
|
|
8530104U, // BICS_PPzPP
|
|
14424U, // BICWrs
|
|
14424U, // BICXrs
|
|
8530104U, // BIC_PPzPP
|
|
8530048U, // BIC_ZPmZ_B
|
|
16914560U, // BIC_ZPmZ_D
|
|
25832584U, // BIC_ZPmZ_H
|
|
33697920U, // BIC_ZPmZ_S
|
|
6232U, // BIC_ZZZ
|
|
794768U, // BICv16i8
|
|
1U, // BICv2i32
|
|
1U, // BICv4i16
|
|
1U, // BICv4i32
|
|
1U, // BICv8i16
|
|
1188008U, // BICv8i8
|
|
795792U, // BIFv16i8
|
|
1189032U, // BIFv8i8
|
|
795792U, // BITv16i8
|
|
1189032U, // BITv8i8
|
|
0U, // BL
|
|
0U, // BLR
|
|
32U, // BLRAA
|
|
0U, // BLRAAZ
|
|
32U, // BLRAB
|
|
0U, // BLRABZ
|
|
0U, // BR
|
|
32U, // BRAA
|
|
0U, // BRAAZ
|
|
32U, // BRAB
|
|
0U, // BRABZ
|
|
0U, // BRB_IALL
|
|
0U, // BRB_INJ
|
|
0U, // BRK
|
|
10424U, // BRKAS_PPzP
|
|
0U, // BRKA_PPmP
|
|
10424U, // BRKA_PPzP
|
|
10424U, // BRKBS_PPzP
|
|
0U, // BRKB_PPmP
|
|
10424U, // BRKB_PPzP
|
|
8530104U, // BRKNS_PPzP
|
|
8530104U, // BRKN_PPzP
|
|
8530104U, // BRKPAS_PPzPP
|
|
8530104U, // BRKPA_PPzPP
|
|
8530104U, // BRKPBS_PPzPP
|
|
8530104U, // BRKPB_PPzPP
|
|
16914520U, // BSL1N_ZZZZ
|
|
16914520U, // BSL2N_ZZZZ
|
|
16914520U, // BSL_ZZZZ
|
|
795792U, // BSLv16i8
|
|
1189032U, // BSLv8i8
|
|
0U, // Bcc
|
|
67250264U, // CADD_ZZI_B
|
|
67246168U, // CADD_ZZI_D
|
|
2239624U, // CADD_ZZI_H
|
|
67252312U, // CADD_ZZI_S
|
|
2397393U, // CASAB
|
|
2397393U, // CASAH
|
|
2397393U, // CASALB
|
|
2397393U, // CASALH
|
|
2397393U, // CASALW
|
|
2397393U, // CASALX
|
|
2397393U, // CASAW
|
|
2397393U, // CASAX
|
|
2397393U, // CASB
|
|
2397393U, // CASH
|
|
2397393U, // CASLB
|
|
2397393U, // CASLH
|
|
2397393U, // CASLW
|
|
2397393U, // CASLX
|
|
0U, // CASPALW
|
|
0U, // CASPALX
|
|
0U, // CASPAW
|
|
0U, // CASPAX
|
|
0U, // CASPLW
|
|
0U, // CASPLX
|
|
0U, // CASPW
|
|
0U, // CASPX
|
|
2397393U, // CASW
|
|
2397393U, // CASX
|
|
1U, // CBNZW
|
|
1U, // CBNZX
|
|
1U, // CBZW
|
|
1U, // CBZX
|
|
75631704U, // CCMNWi
|
|
75631704U, // CCMNWr
|
|
75631704U, // CCMNXi
|
|
75631704U, // CCMNXr
|
|
75631704U, // CCMPWi
|
|
75631704U, // CCMPWr
|
|
75631704U, // CCMPXi
|
|
75631704U, // CCMPXr
|
|
1159601240U, // CDOT_ZZZI_D
|
|
92444673U, // CDOT_ZZZI_S
|
|
100801624U, // CDOT_ZZZ_D
|
|
2501633U, // CDOT_ZZZ_S
|
|
0U, // CFINV
|
|
8522840U, // CLASTA_RPZ_B
|
|
16911448U, // CLASTA_RPZ_D
|
|
109186136U, // CLASTA_RPZ_H
|
|
33688664U, // CLASTA_RPZ_S
|
|
8522840U, // CLASTA_VPZ_B
|
|
16911448U, // CLASTA_VPZ_D
|
|
109186136U, // CLASTA_VPZ_H
|
|
33688664U, // CLASTA_VPZ_S
|
|
8530008U, // CLASTA_ZPZ_B
|
|
16914520U, // CLASTA_ZPZ_D
|
|
25832584U, // CLASTA_ZPZ_H
|
|
33697880U, // CLASTA_ZPZ_S
|
|
8522840U, // CLASTB_RPZ_B
|
|
16911448U, // CLASTB_RPZ_D
|
|
109186136U, // CLASTB_RPZ_H
|
|
33688664U, // CLASTB_RPZ_S
|
|
8522840U, // CLASTB_VPZ_B
|
|
16911448U, // CLASTB_VPZ_D
|
|
109186136U, // CLASTB_VPZ_H
|
|
33688664U, // CLASTB_VPZ_S
|
|
8530008U, // CLASTB_ZPZ_B
|
|
16914520U, // CLASTB_ZPZ_D
|
|
25832584U, // CLASTB_ZPZ_H
|
|
33697880U, // CLASTB_ZPZ_S
|
|
0U, // CLREX
|
|
32U, // CLSWr
|
|
32U, // CLSXr
|
|
0U, // CLS_ZPmZ_B
|
|
8U, // CLS_ZPmZ_D
|
|
0U, // CLS_ZPmZ_H
|
|
16U, // CLS_ZPmZ_S
|
|
24U, // CLSv16i8
|
|
40U, // CLSv2i32
|
|
56U, // CLSv4i16
|
|
64U, // CLSv4i32
|
|
72U, // CLSv8i16
|
|
80U, // CLSv8i8
|
|
32U, // CLZWr
|
|
32U, // CLZXr
|
|
0U, // CLZ_ZPmZ_B
|
|
8U, // CLZ_ZPmZ_D
|
|
0U, // CLZ_ZPmZ_H
|
|
16U, // CLZ_ZPmZ_S
|
|
24U, // CLZv16i8
|
|
40U, // CLZv2i32
|
|
56U, // CLZv4i16
|
|
64U, // CLZv4i32
|
|
72U, // CLZv8i16
|
|
80U, // CLZv8i8
|
|
794768U, // CMEQv16i8
|
|
216U, // CMEQv16i8rz
|
|
3160U, // CMEQv1i64
|
|
224U, // CMEQv1i64rz
|
|
925848U, // CMEQv2i32
|
|
232U, // CMEQv2i32rz
|
|
270440U, // CMEQv2i64
|
|
240U, // CMEQv2i64rz
|
|
1056928U, // CMEQv4i16
|
|
248U, // CMEQv4i16rz
|
|
401520U, // CMEQv4i32
|
|
256U, // CMEQv4i32rz
|
|
532600U, // CMEQv8i16
|
|
264U, // CMEQv8i16rz
|
|
1188008U, // CMEQv8i8
|
|
272U, // CMEQv8i8rz
|
|
794768U, // CMGEv16i8
|
|
216U, // CMGEv16i8rz
|
|
3160U, // CMGEv1i64
|
|
224U, // CMGEv1i64rz
|
|
925848U, // CMGEv2i32
|
|
232U, // CMGEv2i32rz
|
|
270440U, // CMGEv2i64
|
|
240U, // CMGEv2i64rz
|
|
1056928U, // CMGEv4i16
|
|
248U, // CMGEv4i16rz
|
|
401520U, // CMGEv4i32
|
|
256U, // CMGEv4i32rz
|
|
532600U, // CMGEv8i16
|
|
264U, // CMGEv8i16rz
|
|
1188008U, // CMGEv8i8
|
|
272U, // CMGEv8i8rz
|
|
794768U, // CMGTv16i8
|
|
216U, // CMGTv16i8rz
|
|
3160U, // CMGTv1i64
|
|
224U, // CMGTv1i64rz
|
|
925848U, // CMGTv2i32
|
|
232U, // CMGTv2i32rz
|
|
270440U, // CMGTv2i64
|
|
240U, // CMGTv2i64rz
|
|
1056928U, // CMGTv4i16
|
|
248U, // CMGTv4i16rz
|
|
401520U, // CMGTv4i32
|
|
256U, // CMGTv4i32rz
|
|
532600U, // CMGTv8i16
|
|
264U, // CMGTv8i16rz
|
|
1188008U, // CMGTv8i8
|
|
272U, // CMGTv8i8rz
|
|
794768U, // CMHIv16i8
|
|
3160U, // CMHIv1i64
|
|
925848U, // CMHIv2i32
|
|
270440U, // CMHIv2i64
|
|
1056928U, // CMHIv4i16
|
|
401520U, // CMHIv4i32
|
|
532600U, // CMHIv8i16
|
|
1188008U, // CMHIv8i8
|
|
794768U, // CMHSv16i8
|
|
3160U, // CMHSv1i64
|
|
925848U, // CMHSv2i32
|
|
270440U, // CMHSv2i64
|
|
1056928U, // CMHSv4i16
|
|
401520U, // CMHSv4i32
|
|
532600U, // CMHSv8i16
|
|
1188008U, // CMHSv8i8
|
|
92444952U, // CMLA_ZZZI_H
|
|
1159596120U, // CMLA_ZZZI_S
|
|
2501633U, // CMLA_ZZZ_B
|
|
100795480U, // CMLA_ZZZ_D
|
|
2501912U, // CMLA_ZZZ_H
|
|
100796504U, // CMLA_ZZZ_S
|
|
216U, // CMLEv16i8rz
|
|
224U, // CMLEv1i64rz
|
|
232U, // CMLEv2i32rz
|
|
240U, // CMLEv2i64rz
|
|
248U, // CMLEv4i16rz
|
|
256U, // CMLEv4i32rz
|
|
264U, // CMLEv8i16rz
|
|
272U, // CMLEv8i8rz
|
|
216U, // CMLTv16i8rz
|
|
224U, // CMLTv1i64rz
|
|
232U, // CMLTv2i32rz
|
|
240U, // CMLTv2i64rz
|
|
248U, // CMLTv4i16rz
|
|
256U, // CMLTv4i32rz
|
|
264U, // CMLTv8i16rz
|
|
272U, // CMLTv8i8rz
|
|
141496U, // CMPEQ_PPzZI_B
|
|
137400U, // CMPEQ_PPzZI_D
|
|
1453193U, // CMPEQ_PPzZI_H
|
|
143544U, // CMPEQ_PPzZI_S
|
|
8530104U, // CMPEQ_PPzZZ_B
|
|
16914616U, // CMPEQ_PPzZZ_D
|
|
25832585U, // CMPEQ_PPzZZ_H
|
|
33697976U, // CMPEQ_PPzZZ_S
|
|
16918712U, // CMPEQ_WIDE_PPzZZ_B
|
|
1584265U, // CMPEQ_WIDE_PPzZZ_H
|
|
16920760U, // CMPEQ_WIDE_PPzZZ_S
|
|
141496U, // CMPGE_PPzZI_B
|
|
137400U, // CMPGE_PPzZI_D
|
|
1453193U, // CMPGE_PPzZI_H
|
|
143544U, // CMPGE_PPzZI_S
|
|
8530104U, // CMPGE_PPzZZ_B
|
|
16914616U, // CMPGE_PPzZZ_D
|
|
25832585U, // CMPGE_PPzZZ_H
|
|
33697976U, // CMPGE_PPzZZ_S
|
|
16918712U, // CMPGE_WIDE_PPzZZ_B
|
|
1584265U, // CMPGE_WIDE_PPzZZ_H
|
|
16920760U, // CMPGE_WIDE_PPzZZ_S
|
|
141496U, // CMPGT_PPzZI_B
|
|
137400U, // CMPGT_PPzZI_D
|
|
1453193U, // CMPGT_PPzZI_H
|
|
143544U, // CMPGT_PPzZI_S
|
|
8530104U, // CMPGT_PPzZZ_B
|
|
16914616U, // CMPGT_PPzZZ_D
|
|
25832585U, // CMPGT_PPzZZ_H
|
|
33697976U, // CMPGT_PPzZZ_S
|
|
16918712U, // CMPGT_WIDE_PPzZZ_B
|
|
1584265U, // CMPGT_WIDE_PPzZZ_H
|
|
16920760U, // CMPGT_WIDE_PPzZZ_S
|
|
117582008U, // CMPHI_PPzZI_B
|
|
117577912U, // CMPHI_PPzZI_D
|
|
2632841U, // CMPHI_PPzZI_H
|
|
117584056U, // CMPHI_PPzZI_S
|
|
8530104U, // CMPHI_PPzZZ_B
|
|
16914616U, // CMPHI_PPzZZ_D
|
|
25832585U, // CMPHI_PPzZZ_H
|
|
33697976U, // CMPHI_PPzZZ_S
|
|
16918712U, // CMPHI_WIDE_PPzZZ_B
|
|
1584265U, // CMPHI_WIDE_PPzZZ_H
|
|
16920760U, // CMPHI_WIDE_PPzZZ_S
|
|
117582008U, // CMPHS_PPzZI_B
|
|
117577912U, // CMPHS_PPzZI_D
|
|
2632841U, // CMPHS_PPzZI_H
|
|
117584056U, // CMPHS_PPzZI_S
|
|
8530104U, // CMPHS_PPzZZ_B
|
|
16914616U, // CMPHS_PPzZZ_D
|
|
25832585U, // CMPHS_PPzZZ_H
|
|
33697976U, // CMPHS_PPzZZ_S
|
|
16918712U, // CMPHS_WIDE_PPzZZ_B
|
|
1584265U, // CMPHS_WIDE_PPzZZ_H
|
|
16920760U, // CMPHS_WIDE_PPzZZ_S
|
|
141496U, // CMPLE_PPzZI_B
|
|
137400U, // CMPLE_PPzZI_D
|
|
1453193U, // CMPLE_PPzZI_H
|
|
143544U, // CMPLE_PPzZI_S
|
|
16918712U, // CMPLE_WIDE_PPzZZ_B
|
|
1584265U, // CMPLE_WIDE_PPzZZ_H
|
|
16920760U, // CMPLE_WIDE_PPzZZ_S
|
|
117582008U, // CMPLO_PPzZI_B
|
|
117577912U, // CMPLO_PPzZI_D
|
|
2632841U, // CMPLO_PPzZI_H
|
|
117584056U, // CMPLO_PPzZI_S
|
|
16918712U, // CMPLO_WIDE_PPzZZ_B
|
|
1584265U, // CMPLO_WIDE_PPzZZ_H
|
|
16920760U, // CMPLO_WIDE_PPzZZ_S
|
|
117582008U, // CMPLS_PPzZI_B
|
|
117577912U, // CMPLS_PPzZI_D
|
|
2632841U, // CMPLS_PPzZI_H
|
|
117584056U, // CMPLS_PPzZI_S
|
|
16918712U, // CMPLS_WIDE_PPzZZ_B
|
|
1584265U, // CMPLS_WIDE_PPzZZ_H
|
|
16920760U, // CMPLS_WIDE_PPzZZ_S
|
|
141496U, // CMPLT_PPzZI_B
|
|
137400U, // CMPLT_PPzZI_D
|
|
1453193U, // CMPLT_PPzZI_H
|
|
143544U, // CMPLT_PPzZI_S
|
|
16918712U, // CMPLT_WIDE_PPzZZ_B
|
|
1584265U, // CMPLT_WIDE_PPzZZ_H
|
|
16920760U, // CMPLT_WIDE_PPzZZ_S
|
|
141496U, // CMPNE_PPzZI_B
|
|
137400U, // CMPNE_PPzZI_D
|
|
1453193U, // CMPNE_PPzZI_H
|
|
143544U, // CMPNE_PPzZI_S
|
|
8530104U, // CMPNE_PPzZZ_B
|
|
16914616U, // CMPNE_PPzZZ_D
|
|
25832585U, // CMPNE_PPzZZ_H
|
|
33697976U, // CMPNE_PPzZZ_S
|
|
16918712U, // CMPNE_WIDE_PPzZZ_B
|
|
1584265U, // CMPNE_WIDE_PPzZZ_H
|
|
16920760U, // CMPNE_WIDE_PPzZZ_S
|
|
794768U, // CMTSTv16i8
|
|
3160U, // CMTSTv1i64
|
|
925848U, // CMTSTv2i32
|
|
270440U, // CMTSTv2i64
|
|
1056928U, // CMTSTv4i16
|
|
401520U, // CMTSTv4i32
|
|
532600U, // CMTSTv8i16
|
|
1188008U, // CMTSTv8i8
|
|
0U, // CNOT_ZPmZ_B
|
|
8U, // CNOT_ZPmZ_D
|
|
0U, // CNOT_ZPmZ_H
|
|
16U, // CNOT_ZPmZ_S
|
|
289U, // CNTB_XPiI
|
|
289U, // CNTD_XPiI
|
|
289U, // CNTH_XPiI
|
|
10328U, // CNTP_XPP_B
|
|
6232U, // CNTP_XPP_D
|
|
5208U, // CNTP_XPP_H
|
|
12376U, // CNTP_XPP_S
|
|
289U, // CNTW_XPiI
|
|
0U, // CNT_ZPmZ_B
|
|
8U, // CNT_ZPmZ_D
|
|
0U, // CNT_ZPmZ_H
|
|
16U, // CNT_ZPmZ_S
|
|
24U, // CNTv16i8
|
|
80U, // CNTv8i8
|
|
6232U, // COMPACT_ZPZ_D
|
|
12376U, // COMPACT_ZPZ_S
|
|
0U, // CPYE
|
|
0U, // CPYEN
|
|
0U, // CPYERN
|
|
0U, // CPYERT
|
|
0U, // CPYERTN
|
|
0U, // CPYERTRN
|
|
0U, // CPYERTWN
|
|
0U, // CPYET
|
|
0U, // CPYETN
|
|
0U, // CPYETRN
|
|
0U, // CPYETWN
|
|
0U, // CPYEWN
|
|
0U, // CPYEWT
|
|
0U, // CPYEWTN
|
|
0U, // CPYEWTRN
|
|
0U, // CPYEWTWN
|
|
0U, // CPYFE
|
|
0U, // CPYFEN
|
|
0U, // CPYFERN
|
|
0U, // CPYFERT
|
|
0U, // CPYFERTN
|
|
0U, // CPYFERTRN
|
|
0U, // CPYFERTWN
|
|
0U, // CPYFET
|
|
0U, // CPYFETN
|
|
0U, // CPYFETRN
|
|
0U, // CPYFETWN
|
|
0U, // CPYFEWN
|
|
0U, // CPYFEWT
|
|
0U, // CPYFEWTN
|
|
0U, // CPYFEWTRN
|
|
0U, // CPYFEWTWN
|
|
0U, // CPYFM
|
|
0U, // CPYFMN
|
|
0U, // CPYFMRN
|
|
0U, // CPYFMRT
|
|
0U, // CPYFMRTN
|
|
0U, // CPYFMRTRN
|
|
0U, // CPYFMRTWN
|
|
0U, // CPYFMT
|
|
0U, // CPYFMTN
|
|
0U, // CPYFMTRN
|
|
0U, // CPYFMTWN
|
|
0U, // CPYFMWN
|
|
0U, // CPYFMWT
|
|
0U, // CPYFMWTN
|
|
0U, // CPYFMWTRN
|
|
0U, // CPYFMWTWN
|
|
0U, // CPYFP
|
|
0U, // CPYFPN
|
|
0U, // CPYFPRN
|
|
0U, // CPYFPRT
|
|
0U, // CPYFPRTN
|
|
0U, // CPYFPRTRN
|
|
0U, // CPYFPRTWN
|
|
0U, // CPYFPT
|
|
0U, // CPYFPTN
|
|
0U, // CPYFPTRN
|
|
0U, // CPYFPTWN
|
|
0U, // CPYFPWN
|
|
0U, // CPYFPWT
|
|
0U, // CPYFPWTN
|
|
0U, // CPYFPWTRN
|
|
0U, // CPYFPWTWN
|
|
0U, // CPYM
|
|
0U, // CPYMN
|
|
0U, // CPYMRN
|
|
0U, // CPYMRT
|
|
0U, // CPYMRTN
|
|
0U, // CPYMRTRN
|
|
0U, // CPYMRTWN
|
|
0U, // CPYMT
|
|
0U, // CPYMTN
|
|
0U, // CPYMTRN
|
|
0U, // CPYMTWN
|
|
0U, // CPYMWN
|
|
0U, // CPYMWT
|
|
0U, // CPYMWTN
|
|
0U, // CPYMWTRN
|
|
0U, // CPYMWTWN
|
|
0U, // CPYP
|
|
0U, // CPYPN
|
|
0U, // CPYPRN
|
|
0U, // CPYPRT
|
|
0U, // CPYPRTN
|
|
0U, // CPYPRTRN
|
|
0U, // CPYPRTWN
|
|
0U, // CPYPT
|
|
0U, // CPYPTN
|
|
0U, // CPYPTRN
|
|
0U, // CPYPTWN
|
|
0U, // CPYPWN
|
|
0U, // CPYPWT
|
|
0U, // CPYPWTN
|
|
0U, // CPYPWTRN
|
|
0U, // CPYPWTWN
|
|
296U, // CPY_ZPmI_B
|
|
304U, // CPY_ZPmI_D
|
|
1U, // CPY_ZPmI_H
|
|
312U, // CPY_ZPmI_S
|
|
320U, // CPY_ZPmR_B
|
|
320U, // CPY_ZPmR_D
|
|
1U, // CPY_ZPmR_H
|
|
320U, // CPY_ZPmR_S
|
|
320U, // CPY_ZPmV_B
|
|
320U, // CPY_ZPmV_D
|
|
1U, // CPY_ZPmV_H
|
|
320U, // CPY_ZPmV_S
|
|
40120U, // CPY_ZPzI_B
|
|
41144U, // CPY_ZPzI_D
|
|
329U, // CPY_ZPzI_H
|
|
42168U, // CPY_ZPzI_S
|
|
3160U, // CRC32Brr
|
|
3160U, // CRC32CBrr
|
|
3160U, // CRC32CHrr
|
|
3160U, // CRC32CWrr
|
|
3160U, // CRC32CXrr
|
|
3160U, // CRC32Hrr
|
|
3160U, // CRC32Wrr
|
|
3160U, // CRC32Xrr
|
|
75631704U, // CSELWr
|
|
75631704U, // CSELXr
|
|
75631704U, // CSINCWr
|
|
75631704U, // CSINCXr
|
|
75631704U, // CSINVWr
|
|
75631704U, // CSINVXr
|
|
75631704U, // CSNEGWr
|
|
75631704U, // CSNEGXr
|
|
32U, // CTERMEQ_WW
|
|
32U, // CTERMEQ_XX
|
|
32U, // CTERMNE_WW
|
|
32U, // CTERMNE_XX
|
|
0U, // DCPS1
|
|
0U, // DCPS2
|
|
0U, // DCPS3
|
|
1U, // DECB_XPiI
|
|
1U, // DECD_XPiI
|
|
1U, // DECD_ZPiI
|
|
1U, // DECH_XPiI
|
|
0U, // DECH_ZPiI
|
|
32U, // DECP_XP_B
|
|
32U, // DECP_XP_D
|
|
32U, // DECP_XP_H
|
|
32U, // DECP_XP_S
|
|
32U, // DECP_ZP_D
|
|
0U, // DECP_ZP_H
|
|
32U, // DECP_ZP_S
|
|
1U, // DECW_XPiI
|
|
1U, // DECW_ZPiI
|
|
0U, // DMB
|
|
0U, // DRPS
|
|
0U, // DSB
|
|
0U, // DSBnXS
|
|
1U, // DUPM_ZI
|
|
1U, // DUP_ZI_B
|
|
1U, // DUP_ZI_D
|
|
0U, // DUP_ZI_H
|
|
1U, // DUP_ZI_S
|
|
32U, // DUP_ZR_B
|
|
32U, // DUP_ZR_D
|
|
0U, // DUP_ZR_H
|
|
32U, // DUP_ZR_S
|
|
336U, // DUP_ZZI_B
|
|
336U, // DUP_ZZI_D
|
|
1U, // DUP_ZZI_H
|
|
1U, // DUP_ZZI_Q
|
|
336U, // DUP_ZZI_S
|
|
43352U, // DUPi16
|
|
43360U, // DUPi32
|
|
43368U, // DUPi64
|
|
43376U, // DUPi8
|
|
32U, // DUPv16i8gpr
|
|
43376U, // DUPv16i8lane
|
|
32U, // DUPv2i32gpr
|
|
43360U, // DUPv2i32lane
|
|
32U, // DUPv2i64gpr
|
|
43368U, // DUPv2i64lane
|
|
32U, // DUPv4i16gpr
|
|
43352U, // DUPv4i16lane
|
|
32U, // DUPv4i32gpr
|
|
43360U, // DUPv4i32lane
|
|
32U, // DUPv8i16gpr
|
|
43352U, // DUPv8i16lane
|
|
32U, // DUPv8i8gpr
|
|
43376U, // DUPv8i8lane
|
|
14424U, // EONWrs
|
|
14424U, // EONXrs
|
|
580526224U, // EOR3
|
|
16914520U, // EOR3_ZZZZ
|
|
1U, // EORBT_ZZZ_B
|
|
1112U, // EORBT_ZZZ_D
|
|
280U, // EORBT_ZZZ_H
|
|
2136U, // EORBT_ZZZ_S
|
|
8530104U, // EORS_PPzPP
|
|
1U, // EORTB_ZZZ_B
|
|
1112U, // EORTB_ZZZ_D
|
|
280U, // EORTB_ZZZ_H
|
|
2136U, // EORTB_ZZZ_S
|
|
0U, // EORV_VPZ_B
|
|
0U, // EORV_VPZ_D
|
|
0U, // EORV_VPZ_H
|
|
0U, // EORV_VPZ_S
|
|
35928U, // EORWri
|
|
14424U, // EORWrs
|
|
36952U, // EORXri
|
|
14424U, // EORXrs
|
|
8530104U, // EOR_PPzPP
|
|
36952U, // EOR_ZI
|
|
8530048U, // EOR_ZPmZ_B
|
|
16914560U, // EOR_ZPmZ_D
|
|
25832584U, // EOR_ZPmZ_H
|
|
33697920U, // EOR_ZPmZ_S
|
|
6232U, // EOR_ZZZ
|
|
794768U, // EORv16i8
|
|
1188008U, // EORv8i8
|
|
0U, // ERET
|
|
0U, // ERETAA
|
|
0U, // ERETAB
|
|
44160U, // EXTRACT_ZPMXI_H_B
|
|
44160U, // EXTRACT_ZPMXI_H_D
|
|
376U, // EXTRACT_ZPMXI_H_H
|
|
376U, // EXTRACT_ZPMXI_H_Q
|
|
44160U, // EXTRACT_ZPMXI_H_S
|
|
45184U, // EXTRACT_ZPMXI_V_B
|
|
45184U, // EXTRACT_ZPMXI_V_D
|
|
384U, // EXTRACT_ZPMXI_V_H
|
|
384U, // EXTRACT_ZPMXI_V_Q
|
|
45184U, // EXTRACT_ZPMXI_V_S
|
|
134232U, // EXTRWrri
|
|
134232U, // EXTRXrri
|
|
117581912U, // EXT_ZZI
|
|
394U, // EXT_ZZI_B
|
|
1712272U, // EXTv16i8
|
|
2760872U, // EXTv8i8
|
|
3160U, // FABD16
|
|
3160U, // FABD32
|
|
3160U, // FABD64
|
|
16914560U, // FABD_ZPmZ_D
|
|
25832584U, // FABD_ZPmZ_H
|
|
33697920U, // FABD_ZPmZ_S
|
|
925848U, // FABDv2f32
|
|
270440U, // FABDv2f64
|
|
1056928U, // FABDv4f16
|
|
401520U, // FABDv4f32
|
|
532600U, // FABDv8f16
|
|
32U, // FABSDr
|
|
32U, // FABSHr
|
|
32U, // FABSSr
|
|
8U, // FABS_ZPmZ_D
|
|
0U, // FABS_ZPmZ_H
|
|
16U, // FABS_ZPmZ_S
|
|
40U, // FABSv2f32
|
|
48U, // FABSv2f64
|
|
56U, // FABSv4f16
|
|
64U, // FABSv4f32
|
|
72U, // FABSv8f16
|
|
3160U, // FACGE16
|
|
3160U, // FACGE32
|
|
3160U, // FACGE64
|
|
16914616U, // FACGE_PPzZZ_D
|
|
25832585U, // FACGE_PPzZZ_H
|
|
33697976U, // FACGE_PPzZZ_S
|
|
925848U, // FACGEv2f32
|
|
270440U, // FACGEv2f64
|
|
1056928U, // FACGEv4f16
|
|
401520U, // FACGEv4f32
|
|
532600U, // FACGEv8f16
|
|
3160U, // FACGT16
|
|
3160U, // FACGT32
|
|
3160U, // FACGT64
|
|
16914616U, // FACGT_PPzZZ_D
|
|
25832585U, // FACGT_PPzZZ_H
|
|
33697976U, // FACGT_PPzZZ_S
|
|
925848U, // FACGTv2f32
|
|
270440U, // FACGTv2f64
|
|
1056928U, // FACGTv4f16
|
|
401520U, // FACGTv4f32
|
|
532600U, // FACGTv8f16
|
|
0U, // FADDA_VPZ_D
|
|
280U, // FADDA_VPZ_H
|
|
0U, // FADDA_VPZ_S
|
|
3160U, // FADDDrr
|
|
3160U, // FADDHrr
|
|
16914560U, // FADDP_ZPmZZ_D
|
|
25832584U, // FADDP_ZPmZZ_H
|
|
33697920U, // FADDP_ZPmZZ_S
|
|
925848U, // FADDPv2f32
|
|
270440U, // FADDPv2f64
|
|
400U, // FADDPv2i16p
|
|
40U, // FADDPv2i32p
|
|
48U, // FADDPv2i64p
|
|
1056928U, // FADDPv4f16
|
|
401520U, // FADDPv4f32
|
|
532600U, // FADDPv8f16
|
|
3160U, // FADDSrr
|
|
0U, // FADDV_VPZ_D
|
|
0U, // FADDV_VPZ_H
|
|
0U, // FADDV_VPZ_S
|
|
125966464U, // FADD_ZPmI_D
|
|
2894984U, // FADD_ZPmI_H
|
|
125972608U, // FADD_ZPmI_S
|
|
16914560U, // FADD_ZPmZ_D
|
|
25832584U, // FADD_ZPmZ_H
|
|
33697920U, // FADD_ZPmZ_S
|
|
6232U, // FADD_ZZZ_D
|
|
136U, // FADD_ZZZ_H
|
|
12376U, // FADD_ZZZ_S
|
|
925848U, // FADDv2f32
|
|
270440U, // FADDv2f64
|
|
1056928U, // FADDv4f16
|
|
401520U, // FADDv4f32
|
|
532600U, // FADDv8f16
|
|
1627527296U, // FCADD_ZPmZ_D
|
|
2232036488U, // FCADD_ZPmZ_H
|
|
1644310656U, // FCADD_ZPmZ_S
|
|
70131864U, // FCADDv2f32
|
|
70262888U, // FCADDv2f64
|
|
70394016U, // FCADDv4f16
|
|
70525040U, // FCADDv4f32
|
|
70656120U, // FCADDv8f16
|
|
75631704U, // FCCMPDrr
|
|
75631704U, // FCCMPEDrr
|
|
75631704U, // FCCMPEHrr
|
|
75631704U, // FCCMPESrr
|
|
75631704U, // FCCMPHrr
|
|
75631704U, // FCCMPSrr
|
|
3160U, // FCMEQ16
|
|
3160U, // FCMEQ32
|
|
3160U, // FCMEQ64
|
|
3676344U, // FCMEQ_PPzZ0_D
|
|
46217U, // FCMEQ_PPzZ0_H
|
|
3682488U, // FCMEQ_PPzZ0_S
|
|
16914616U, // FCMEQ_PPzZZ_D
|
|
25832585U, // FCMEQ_PPzZZ_H
|
|
33697976U, // FCMEQ_PPzZZ_S
|
|
408U, // FCMEQv1i16rz
|
|
408U, // FCMEQv1i32rz
|
|
408U, // FCMEQv1i64rz
|
|
925848U, // FCMEQv2f32
|
|
270440U, // FCMEQv2f64
|
|
416U, // FCMEQv2i32rz
|
|
424U, // FCMEQv2i64rz
|
|
1056928U, // FCMEQv4f16
|
|
401520U, // FCMEQv4f32
|
|
432U, // FCMEQv4i16rz
|
|
440U, // FCMEQv4i32rz
|
|
532600U, // FCMEQv8f16
|
|
448U, // FCMEQv8i16rz
|
|
3160U, // FCMGE16
|
|
3160U, // FCMGE32
|
|
3160U, // FCMGE64
|
|
3676344U, // FCMGE_PPzZ0_D
|
|
46217U, // FCMGE_PPzZ0_H
|
|
3682488U, // FCMGE_PPzZ0_S
|
|
16914616U, // FCMGE_PPzZZ_D
|
|
25832585U, // FCMGE_PPzZZ_H
|
|
33697976U, // FCMGE_PPzZZ_S
|
|
408U, // FCMGEv1i16rz
|
|
408U, // FCMGEv1i32rz
|
|
408U, // FCMGEv1i64rz
|
|
925848U, // FCMGEv2f32
|
|
270440U, // FCMGEv2f64
|
|
416U, // FCMGEv2i32rz
|
|
424U, // FCMGEv2i64rz
|
|
1056928U, // FCMGEv4f16
|
|
401520U, // FCMGEv4f32
|
|
432U, // FCMGEv4i16rz
|
|
440U, // FCMGEv4i32rz
|
|
532600U, // FCMGEv8f16
|
|
448U, // FCMGEv8i16rz
|
|
3160U, // FCMGT16
|
|
3160U, // FCMGT32
|
|
3160U, // FCMGT64
|
|
3676344U, // FCMGT_PPzZ0_D
|
|
46217U, // FCMGT_PPzZ0_H
|
|
3682488U, // FCMGT_PPzZ0_S
|
|
16914616U, // FCMGT_PPzZZ_D
|
|
25832585U, // FCMGT_PPzZZ_H
|
|
33697976U, // FCMGT_PPzZZ_S
|
|
408U, // FCMGTv1i16rz
|
|
408U, // FCMGTv1i32rz
|
|
408U, // FCMGTv1i64rz
|
|
925848U, // FCMGTv2f32
|
|
270440U, // FCMGTv2f64
|
|
416U, // FCMGTv2i32rz
|
|
424U, // FCMGTv2i64rz
|
|
1056928U, // FCMGTv4f16
|
|
401520U, // FCMGTv4f32
|
|
432U, // FCMGTv4i16rz
|
|
440U, // FCMGTv4i32rz
|
|
532600U, // FCMGTv8f16
|
|
448U, // FCMGTv8i16rz
|
|
1744962688U, // FCMLA_ZPmZZ_D
|
|
1161440536U, // FCMLA_ZPmZZ_H
|
|
1753352320U, // FCMLA_ZPmZZ_S
|
|
92444952U, // FCMLA_ZZZI_H
|
|
1159596120U, // FCMLA_ZZZI_S
|
|
103687320U, // FCMLAv2f32
|
|
103818344U, // FCMLAv2f64
|
|
103949472U, // FCMLAv4f16
|
|
1663050912U, // FCMLAv4f16_indexed
|
|
104080496U, // FCMLAv4f32
|
|
1664885872U, // FCMLAv4f32_indexed
|
|
104211576U, // FCMLAv8f16
|
|
1663050872U, // FCMLAv8f16_indexed
|
|
3676344U, // FCMLE_PPzZ0_D
|
|
46217U, // FCMLE_PPzZ0_H
|
|
3682488U, // FCMLE_PPzZ0_S
|
|
408U, // FCMLEv1i16rz
|
|
408U, // FCMLEv1i32rz
|
|
408U, // FCMLEv1i64rz
|
|
416U, // FCMLEv2i32rz
|
|
424U, // FCMLEv2i64rz
|
|
432U, // FCMLEv4i16rz
|
|
440U, // FCMLEv4i32rz
|
|
448U, // FCMLEv8i16rz
|
|
3676344U, // FCMLT_PPzZ0_D
|
|
46217U, // FCMLT_PPzZ0_H
|
|
3682488U, // FCMLT_PPzZ0_S
|
|
408U, // FCMLTv1i16rz
|
|
408U, // FCMLTv1i32rz
|
|
408U, // FCMLTv1i64rz
|
|
416U, // FCMLTv2i32rz
|
|
424U, // FCMLTv2i64rz
|
|
432U, // FCMLTv4i16rz
|
|
440U, // FCMLTv4i32rz
|
|
448U, // FCMLTv8i16rz
|
|
3676344U, // FCMNE_PPzZ0_D
|
|
46217U, // FCMNE_PPzZ0_H
|
|
3682488U, // FCMNE_PPzZ0_S
|
|
16914616U, // FCMNE_PPzZZ_D
|
|
25832585U, // FCMNE_PPzZZ_H
|
|
33697976U, // FCMNE_PPzZZ_S
|
|
0U, // FCMPDri
|
|
32U, // FCMPDrr
|
|
0U, // FCMPEDri
|
|
32U, // FCMPEDrr
|
|
0U, // FCMPEHri
|
|
32U, // FCMPEHrr
|
|
0U, // FCMPESri
|
|
32U, // FCMPESrr
|
|
0U, // FCMPHri
|
|
32U, // FCMPHrr
|
|
0U, // FCMPSri
|
|
32U, // FCMPSrr
|
|
16914616U, // FCMUO_PPzZZ_D
|
|
25832585U, // FCMUO_PPzZZ_H
|
|
33697976U, // FCMUO_PPzZZ_S
|
|
456U, // FCPY_ZPmI_D
|
|
2U, // FCPY_ZPmI_H
|
|
456U, // FCPY_ZPmI_S
|
|
75631704U, // FCSELDrrr
|
|
75631704U, // FCSELHrrr
|
|
75631704U, // FCSELSrrr
|
|
32U, // FCVTASUWDr
|
|
32U, // FCVTASUWHr
|
|
32U, // FCVTASUWSr
|
|
32U, // FCVTASUXDr
|
|
32U, // FCVTASUXHr
|
|
32U, // FCVTASUXSr
|
|
32U, // FCVTASv1f16
|
|
32U, // FCVTASv1i32
|
|
32U, // FCVTASv1i64
|
|
40U, // FCVTASv2f32
|
|
48U, // FCVTASv2f64
|
|
56U, // FCVTASv4f16
|
|
64U, // FCVTASv4f32
|
|
72U, // FCVTASv8f16
|
|
32U, // FCVTAUUWDr
|
|
32U, // FCVTAUUWHr
|
|
32U, // FCVTAUUWSr
|
|
32U, // FCVTAUUXDr
|
|
32U, // FCVTAUUXHr
|
|
32U, // FCVTAUUXSr
|
|
32U, // FCVTAUv1f16
|
|
32U, // FCVTAUv1i32
|
|
32U, // FCVTAUv1i64
|
|
40U, // FCVTAUv2f32
|
|
48U, // FCVTAUv2f64
|
|
56U, // FCVTAUv4f16
|
|
64U, // FCVTAUv4f32
|
|
72U, // FCVTAUv8f16
|
|
32U, // FCVTDHr
|
|
32U, // FCVTDSr
|
|
32U, // FCVTHDr
|
|
32U, // FCVTHSr
|
|
280U, // FCVTLT_ZPmZ_HtoS
|
|
16U, // FCVTLT_ZPmZ_StoD
|
|
40U, // FCVTLv2i32
|
|
56U, // FCVTLv4i16
|
|
64U, // FCVTLv4i32
|
|
72U, // FCVTLv8i16
|
|
32U, // FCVTMSUWDr
|
|
32U, // FCVTMSUWHr
|
|
32U, // FCVTMSUWSr
|
|
32U, // FCVTMSUXDr
|
|
32U, // FCVTMSUXHr
|
|
32U, // FCVTMSUXSr
|
|
32U, // FCVTMSv1f16
|
|
32U, // FCVTMSv1i32
|
|
32U, // FCVTMSv1i64
|
|
40U, // FCVTMSv2f32
|
|
48U, // FCVTMSv2f64
|
|
56U, // FCVTMSv4f16
|
|
64U, // FCVTMSv4f32
|
|
72U, // FCVTMSv8f16
|
|
32U, // FCVTMUUWDr
|
|
32U, // FCVTMUUWHr
|
|
32U, // FCVTMUUWSr
|
|
32U, // FCVTMUUXDr
|
|
32U, // FCVTMUUXHr
|
|
32U, // FCVTMUUXSr
|
|
32U, // FCVTMUv1f16
|
|
32U, // FCVTMUv1i32
|
|
32U, // FCVTMUv1i64
|
|
40U, // FCVTMUv2f32
|
|
48U, // FCVTMUv2f64
|
|
56U, // FCVTMUv4f16
|
|
64U, // FCVTMUv4f32
|
|
72U, // FCVTMUv8f16
|
|
32U, // FCVTNSUWDr
|
|
32U, // FCVTNSUWHr
|
|
32U, // FCVTNSUWSr
|
|
32U, // FCVTNSUXDr
|
|
32U, // FCVTNSUXHr
|
|
32U, // FCVTNSUXSr
|
|
32U, // FCVTNSv1f16
|
|
32U, // FCVTNSv1i32
|
|
32U, // FCVTNSv1i64
|
|
40U, // FCVTNSv2f32
|
|
48U, // FCVTNSv2f64
|
|
56U, // FCVTNSv4f16
|
|
64U, // FCVTNSv4f32
|
|
72U, // FCVTNSv8f16
|
|
8U, // FCVTNT_ZPmZ_DtoS
|
|
1U, // FCVTNT_ZPmZ_StoH
|
|
32U, // FCVTNUUWDr
|
|
32U, // FCVTNUUWHr
|
|
32U, // FCVTNUUWSr
|
|
32U, // FCVTNUUXDr
|
|
32U, // FCVTNUUXHr
|
|
32U, // FCVTNUUXSr
|
|
32U, // FCVTNUv1f16
|
|
32U, // FCVTNUv1i32
|
|
32U, // FCVTNUv1i64
|
|
40U, // FCVTNUv2f32
|
|
48U, // FCVTNUv2f64
|
|
56U, // FCVTNUv4f16
|
|
64U, // FCVTNUv4f32
|
|
72U, // FCVTNUv8f16
|
|
48U, // FCVTNv2i32
|
|
64U, // FCVTNv4i16
|
|
48U, // FCVTNv4i32
|
|
64U, // FCVTNv8i16
|
|
32U, // FCVTPSUWDr
|
|
32U, // FCVTPSUWHr
|
|
32U, // FCVTPSUWSr
|
|
32U, // FCVTPSUXDr
|
|
32U, // FCVTPSUXHr
|
|
32U, // FCVTPSUXSr
|
|
32U, // FCVTPSv1f16
|
|
32U, // FCVTPSv1i32
|
|
32U, // FCVTPSv1i64
|
|
40U, // FCVTPSv2f32
|
|
48U, // FCVTPSv2f64
|
|
56U, // FCVTPSv4f16
|
|
64U, // FCVTPSv4f32
|
|
72U, // FCVTPSv8f16
|
|
32U, // FCVTPUUWDr
|
|
32U, // FCVTPUUWHr
|
|
32U, // FCVTPUUWSr
|
|
32U, // FCVTPUUXDr
|
|
32U, // FCVTPUUXHr
|
|
32U, // FCVTPUUXSr
|
|
32U, // FCVTPUv1f16
|
|
32U, // FCVTPUv1i32
|
|
32U, // FCVTPUv1i64
|
|
40U, // FCVTPUv2f32
|
|
48U, // FCVTPUv2f64
|
|
56U, // FCVTPUv4f16
|
|
64U, // FCVTPUv4f32
|
|
72U, // FCVTPUv8f16
|
|
32U, // FCVTSDr
|
|
32U, // FCVTSHr
|
|
8U, // FCVTXNT_ZPmZ_DtoS
|
|
32U, // FCVTXNv1i64
|
|
48U, // FCVTXNv2f32
|
|
48U, // FCVTXNv4f32
|
|
8U, // FCVTX_ZPmZ_DtoS
|
|
3160U, // FCVTZSSWDri
|
|
3160U, // FCVTZSSWHri
|
|
3160U, // FCVTZSSWSri
|
|
3160U, // FCVTZSSXDri
|
|
3160U, // FCVTZSSXHri
|
|
3160U, // FCVTZSSXSri
|
|
32U, // FCVTZSUWDr
|
|
32U, // FCVTZSUWHr
|
|
32U, // FCVTZSUWSr
|
|
32U, // FCVTZSUXDr
|
|
32U, // FCVTZSUXHr
|
|
32U, // FCVTZSUXSr
|
|
8U, // FCVTZS_ZPmZ_DtoD
|
|
8U, // FCVTZS_ZPmZ_DtoS
|
|
280U, // FCVTZS_ZPmZ_HtoD
|
|
0U, // FCVTZS_ZPmZ_HtoH
|
|
280U, // FCVTZS_ZPmZ_HtoS
|
|
16U, // FCVTZS_ZPmZ_StoD
|
|
16U, // FCVTZS_ZPmZ_StoS
|
|
3160U, // FCVTZSd
|
|
3160U, // FCVTZSh
|
|
3160U, // FCVTZSs
|
|
32U, // FCVTZSv1f16
|
|
32U, // FCVTZSv1i32
|
|
32U, // FCVTZSv1i64
|
|
40U, // FCVTZSv2f32
|
|
48U, // FCVTZSv2f64
|
|
3224U, // FCVTZSv2i32_shift
|
|
3176U, // FCVTZSv2i64_shift
|
|
56U, // FCVTZSv4f16
|
|
64U, // FCVTZSv4f32
|
|
3232U, // FCVTZSv4i16_shift
|
|
3184U, // FCVTZSv4i32_shift
|
|
72U, // FCVTZSv8f16
|
|
3192U, // FCVTZSv8i16_shift
|
|
3160U, // FCVTZUSWDri
|
|
3160U, // FCVTZUSWHri
|
|
3160U, // FCVTZUSWSri
|
|
3160U, // FCVTZUSXDri
|
|
3160U, // FCVTZUSXHri
|
|
3160U, // FCVTZUSXSri
|
|
32U, // FCVTZUUWDr
|
|
32U, // FCVTZUUWHr
|
|
32U, // FCVTZUUWSr
|
|
32U, // FCVTZUUXDr
|
|
32U, // FCVTZUUXHr
|
|
32U, // FCVTZUUXSr
|
|
8U, // FCVTZU_ZPmZ_DtoD
|
|
8U, // FCVTZU_ZPmZ_DtoS
|
|
280U, // FCVTZU_ZPmZ_HtoD
|
|
0U, // FCVTZU_ZPmZ_HtoH
|
|
280U, // FCVTZU_ZPmZ_HtoS
|
|
16U, // FCVTZU_ZPmZ_StoD
|
|
16U, // FCVTZU_ZPmZ_StoS
|
|
3160U, // FCVTZUd
|
|
3160U, // FCVTZUh
|
|
3160U, // FCVTZUs
|
|
32U, // FCVTZUv1f16
|
|
32U, // FCVTZUv1i32
|
|
32U, // FCVTZUv1i64
|
|
40U, // FCVTZUv2f32
|
|
48U, // FCVTZUv2f64
|
|
3224U, // FCVTZUv2i32_shift
|
|
3176U, // FCVTZUv2i64_shift
|
|
56U, // FCVTZUv4f16
|
|
64U, // FCVTZUv4f32
|
|
3232U, // FCVTZUv4i16_shift
|
|
3184U, // FCVTZUv4i32_shift
|
|
72U, // FCVTZUv8f16
|
|
3192U, // FCVTZUv8i16_shift
|
|
2U, // FCVT_ZPmZ_DtoH
|
|
8U, // FCVT_ZPmZ_DtoS
|
|
280U, // FCVT_ZPmZ_HtoD
|
|
280U, // FCVT_ZPmZ_HtoS
|
|
16U, // FCVT_ZPmZ_StoD
|
|
1U, // FCVT_ZPmZ_StoH
|
|
3160U, // FDIVDrr
|
|
3160U, // FDIVHrr
|
|
16914560U, // FDIVR_ZPmZ_D
|
|
25832584U, // FDIVR_ZPmZ_H
|
|
33697920U, // FDIVR_ZPmZ_S
|
|
3160U, // FDIVSrr
|
|
16914560U, // FDIV_ZPmZ_D
|
|
25832584U, // FDIV_ZPmZ_H
|
|
33697920U, // FDIV_ZPmZ_S
|
|
925848U, // FDIVv2f32
|
|
270440U, // FDIVv2f64
|
|
1056928U, // FDIVv4f16
|
|
401520U, // FDIVv4f32
|
|
532600U, // FDIVv8f16
|
|
2U, // FDUP_ZI_D
|
|
0U, // FDUP_ZI_H
|
|
2U, // FDUP_ZI_S
|
|
32U, // FEXPA_ZZ_D
|
|
0U, // FEXPA_ZZ_H
|
|
32U, // FEXPA_ZZ_S
|
|
32U, // FJCVTZS
|
|
8U, // FLOGB_ZPmZ_D
|
|
0U, // FLOGB_ZPmZ_H
|
|
16U, // FLOGB_ZPmZ_S
|
|
134232U, // FMADDDrrr
|
|
134232U, // FMADDHrrr
|
|
134232U, // FMADDSrrr
|
|
134349952U, // FMAD_ZPmZZ_D
|
|
28978456U, // FMAD_ZPmZZ_H
|
|
142739584U, // FMAD_ZPmZZ_S
|
|
3160U, // FMAXDrr
|
|
3160U, // FMAXHrr
|
|
3160U, // FMAXNMDrr
|
|
3160U, // FMAXNMHrr
|
|
16914560U, // FMAXNMP_ZPmZZ_D
|
|
25832584U, // FMAXNMP_ZPmZZ_H
|
|
33697920U, // FMAXNMP_ZPmZZ_S
|
|
925848U, // FMAXNMPv2f32
|
|
270440U, // FMAXNMPv2f64
|
|
400U, // FMAXNMPv2i16p
|
|
40U, // FMAXNMPv2i32p
|
|
48U, // FMAXNMPv2i64p
|
|
1056928U, // FMAXNMPv4f16
|
|
401520U, // FMAXNMPv4f32
|
|
532600U, // FMAXNMPv8f16
|
|
3160U, // FMAXNMSrr
|
|
0U, // FMAXNMV_VPZ_D
|
|
0U, // FMAXNMV_VPZ_H
|
|
0U, // FMAXNMV_VPZ_S
|
|
56U, // FMAXNMVv4i16v
|
|
64U, // FMAXNMVv4i32v
|
|
72U, // FMAXNMVv8i16v
|
|
151132288U, // FMAXNM_ZPmI_D
|
|
4074632U, // FMAXNM_ZPmI_H
|
|
151138432U, // FMAXNM_ZPmI_S
|
|
16914560U, // FMAXNM_ZPmZ_D
|
|
25832584U, // FMAXNM_ZPmZ_H
|
|
33697920U, // FMAXNM_ZPmZ_S
|
|
925848U, // FMAXNMv2f32
|
|
270440U, // FMAXNMv2f64
|
|
1056928U, // FMAXNMv4f16
|
|
401520U, // FMAXNMv4f32
|
|
532600U, // FMAXNMv8f16
|
|
16914560U, // FMAXP_ZPmZZ_D
|
|
25832584U, // FMAXP_ZPmZZ_H
|
|
33697920U, // FMAXP_ZPmZZ_S
|
|
925848U, // FMAXPv2f32
|
|
270440U, // FMAXPv2f64
|
|
400U, // FMAXPv2i16p
|
|
40U, // FMAXPv2i32p
|
|
48U, // FMAXPv2i64p
|
|
1056928U, // FMAXPv4f16
|
|
401520U, // FMAXPv4f32
|
|
532600U, // FMAXPv8f16
|
|
3160U, // FMAXSrr
|
|
0U, // FMAXV_VPZ_D
|
|
0U, // FMAXV_VPZ_H
|
|
0U, // FMAXV_VPZ_S
|
|
56U, // FMAXVv4i16v
|
|
64U, // FMAXVv4i32v
|
|
72U, // FMAXVv8i16v
|
|
151132288U, // FMAX_ZPmI_D
|
|
4074632U, // FMAX_ZPmI_H
|
|
151138432U, // FMAX_ZPmI_S
|
|
16914560U, // FMAX_ZPmZ_D
|
|
25832584U, // FMAX_ZPmZ_H
|
|
33697920U, // FMAX_ZPmZ_S
|
|
925848U, // FMAXv2f32
|
|
270440U, // FMAXv2f64
|
|
1056928U, // FMAXv4f16
|
|
401520U, // FMAXv4f32
|
|
532600U, // FMAXv8f16
|
|
3160U, // FMINDrr
|
|
3160U, // FMINHrr
|
|
3160U, // FMINNMDrr
|
|
3160U, // FMINNMHrr
|
|
16914560U, // FMINNMP_ZPmZZ_D
|
|
25832584U, // FMINNMP_ZPmZZ_H
|
|
33697920U, // FMINNMP_ZPmZZ_S
|
|
925848U, // FMINNMPv2f32
|
|
270440U, // FMINNMPv2f64
|
|
400U, // FMINNMPv2i16p
|
|
40U, // FMINNMPv2i32p
|
|
48U, // FMINNMPv2i64p
|
|
1056928U, // FMINNMPv4f16
|
|
401520U, // FMINNMPv4f32
|
|
532600U, // FMINNMPv8f16
|
|
3160U, // FMINNMSrr
|
|
0U, // FMINNMV_VPZ_D
|
|
0U, // FMINNMV_VPZ_H
|
|
0U, // FMINNMV_VPZ_S
|
|
56U, // FMINNMVv4i16v
|
|
64U, // FMINNMVv4i32v
|
|
72U, // FMINNMVv8i16v
|
|
151132288U, // FMINNM_ZPmI_D
|
|
4074632U, // FMINNM_ZPmI_H
|
|
151138432U, // FMINNM_ZPmI_S
|
|
16914560U, // FMINNM_ZPmZ_D
|
|
25832584U, // FMINNM_ZPmZ_H
|
|
33697920U, // FMINNM_ZPmZ_S
|
|
925848U, // FMINNMv2f32
|
|
270440U, // FMINNMv2f64
|
|
1056928U, // FMINNMv4f16
|
|
401520U, // FMINNMv4f32
|
|
532600U, // FMINNMv8f16
|
|
16914560U, // FMINP_ZPmZZ_D
|
|
25832584U, // FMINP_ZPmZZ_H
|
|
33697920U, // FMINP_ZPmZZ_S
|
|
925848U, // FMINPv2f32
|
|
270440U, // FMINPv2f64
|
|
400U, // FMINPv2i16p
|
|
40U, // FMINPv2i32p
|
|
48U, // FMINPv2i64p
|
|
1056928U, // FMINPv4f16
|
|
401520U, // FMINPv4f32
|
|
532600U, // FMINPv8f16
|
|
3160U, // FMINSrr
|
|
0U, // FMINV_VPZ_D
|
|
0U, // FMINV_VPZ_H
|
|
0U, // FMINV_VPZ_S
|
|
56U, // FMINVv4i16v
|
|
64U, // FMINVv4i32v
|
|
72U, // FMINVv8i16v
|
|
151132288U, // FMIN_ZPmI_D
|
|
4074632U, // FMIN_ZPmI_H
|
|
151138432U, // FMIN_ZPmI_S
|
|
16914560U, // FMIN_ZPmZ_D
|
|
25832584U, // FMIN_ZPmZ_H
|
|
33697920U, // FMIN_ZPmZ_S
|
|
925848U, // FMINv2f32
|
|
270440U, // FMINv2f64
|
|
1056928U, // FMINv4f16
|
|
401520U, // FMINv4f32
|
|
532600U, // FMINv8f16
|
|
47568U, // FMLAL2lanev4f16
|
|
52438176U, // FMLAL2lanev8f16
|
|
48592U, // FMLAL2v4f16
|
|
1057952U, // FMLAL2v8f16
|
|
27139160U, // FMLALB_ZZZI_SHH
|
|
7256U, // FMLALB_ZZZ_SHH
|
|
27139160U, // FMLALT_ZZZI_SHH
|
|
7256U, // FMLALT_ZZZ_SHH
|
|
47568U, // FMLALlanev4f16
|
|
52438176U, // FMLALlanev8f16
|
|
48592U, // FMLALv4f16
|
|
1057952U, // FMLALv8f16
|
|
134349952U, // FMLA_ZPmZZ_D
|
|
28978456U, // FMLA_ZPmZZ_H
|
|
142739584U, // FMLA_ZPmZZ_S
|
|
27133016U, // FMLA_ZZZI_D
|
|
39192U, // FMLA_ZZZI_H
|
|
27134040U, // FMLA_ZZZI_S
|
|
52438105U, // FMLAv1i16_indexed
|
|
54273113U, // FMLAv1i32_indexed
|
|
54535257U, // FMLAv1i64_indexed
|
|
926872U, // FMLAv2f32
|
|
271464U, // FMLAv2f64
|
|
54273176U, // FMLAv2i32_indexed
|
|
54535272U, // FMLAv2i64_indexed
|
|
1057952U, // FMLAv4f16
|
|
402544U, // FMLAv4f32
|
|
52438176U, // FMLAv4i16_indexed
|
|
54273136U, // FMLAv4i32_indexed
|
|
533624U, // FMLAv8f16
|
|
52438136U, // FMLAv8i16_indexed
|
|
47568U, // FMLSL2lanev4f16
|
|
52438176U, // FMLSL2lanev8f16
|
|
48592U, // FMLSL2v4f16
|
|
1057952U, // FMLSL2v8f16
|
|
27139160U, // FMLSLB_ZZZI_SHH
|
|
7256U, // FMLSLB_ZZZ_SHH
|
|
27139160U, // FMLSLT_ZZZI_SHH
|
|
7256U, // FMLSLT_ZZZ_SHH
|
|
47568U, // FMLSLlanev4f16
|
|
52438176U, // FMLSLlanev8f16
|
|
48592U, // FMLSLv4f16
|
|
1057952U, // FMLSLv8f16
|
|
134349952U, // FMLS_ZPmZZ_D
|
|
28978456U, // FMLS_ZPmZZ_H
|
|
142739584U, // FMLS_ZPmZZ_S
|
|
27133016U, // FMLS_ZZZI_D
|
|
39192U, // FMLS_ZZZI_H
|
|
27134040U, // FMLS_ZZZI_S
|
|
52438105U, // FMLSv1i16_indexed
|
|
54273113U, // FMLSv1i32_indexed
|
|
54535257U, // FMLSv1i64_indexed
|
|
926872U, // FMLSv2f32
|
|
271464U, // FMLSv2f64
|
|
54273176U, // FMLSv2i32_indexed
|
|
54535272U, // FMLSv2i64_indexed
|
|
1057952U, // FMLSv4f16
|
|
402544U, // FMLSv4f32
|
|
52438176U, // FMLSv4i16_indexed
|
|
54273136U, // FMLSv4i32_indexed
|
|
533624U, // FMLSv8f16
|
|
52438136U, // FMLSv8i16_indexed
|
|
1112U, // FMMLA_ZZZ_D
|
|
2136U, // FMMLA_ZZZ_S
|
|
472U, // FMOPA_MPPZZ_D
|
|
480U, // FMOPA_MPPZZ_S
|
|
472U, // FMOPS_MPPZZ_D
|
|
480U, // FMOPS_MPPZZ_S
|
|
43368U, // FMOVDXHighr
|
|
32U, // FMOVDXr
|
|
2U, // FMOVDi
|
|
32U, // FMOVDr
|
|
32U, // FMOVHWr
|
|
32U, // FMOVHXr
|
|
2U, // FMOVHi
|
|
32U, // FMOVHr
|
|
32U, // FMOVSWr
|
|
2U, // FMOVSi
|
|
32U, // FMOVSr
|
|
32U, // FMOVWHr
|
|
32U, // FMOVWSr
|
|
32U, // FMOVXDHighr
|
|
32U, // FMOVXDr
|
|
32U, // FMOVXHr
|
|
2U, // FMOVv2f32_ns
|
|
2U, // FMOVv2f64_ns
|
|
2U, // FMOVv4f16_ns
|
|
2U, // FMOVv4f32_ns
|
|
2U, // FMOVv8f16_ns
|
|
134349952U, // FMSB_ZPmZZ_D
|
|
28978456U, // FMSB_ZPmZZ_H
|
|
142739584U, // FMSB_ZPmZZ_S
|
|
134232U, // FMSUBDrrr
|
|
134232U, // FMSUBHrrr
|
|
134232U, // FMSUBSrrr
|
|
3160U, // FMULDrr
|
|
3160U, // FMULHrr
|
|
3160U, // FMULSrr
|
|
3160U, // FMULX16
|
|
3160U, // FMULX32
|
|
3160U, // FMULX64
|
|
16914560U, // FMULX_ZPmZ_D
|
|
25832584U, // FMULX_ZPmZ_H
|
|
33697920U, // FMULX_ZPmZ_S
|
|
161488984U, // FMULXv1i16_indexed
|
|
163323992U, // FMULXv1i32_indexed
|
|
163586136U, // FMULXv1i64_indexed
|
|
925848U, // FMULXv2f32
|
|
270440U, // FMULXv2f64
|
|
163324056U, // FMULXv2i32_indexed
|
|
163586152U, // FMULXv2i64_indexed
|
|
1056928U, // FMULXv4f16
|
|
401520U, // FMULXv4f32
|
|
161489056U, // FMULXv4i16_indexed
|
|
163324016U, // FMULXv4i32_indexed
|
|
532600U, // FMULXv8f16
|
|
161489016U, // FMULXv8i16_indexed
|
|
167909504U, // FMUL_ZPmI_D
|
|
4336776U, // FMUL_ZPmI_H
|
|
167915648U, // FMUL_ZPmI_S
|
|
16914560U, // FMUL_ZPmZ_D
|
|
25832584U, // FMUL_ZPmZ_H
|
|
33697920U, // FMUL_ZPmZ_S
|
|
4462680U, // FMUL_ZZZI_D
|
|
49288U, // FMUL_ZZZI_H
|
|
4468824U, // FMUL_ZZZI_S
|
|
6232U, // FMUL_ZZZ_D
|
|
136U, // FMUL_ZZZ_H
|
|
12376U, // FMUL_ZZZ_S
|
|
161488984U, // FMULv1i16_indexed
|
|
163323992U, // FMULv1i32_indexed
|
|
163586136U, // FMULv1i64_indexed
|
|
925848U, // FMULv2f32
|
|
270440U, // FMULv2f64
|
|
163324056U, // FMULv2i32_indexed
|
|
163586152U, // FMULv2i64_indexed
|
|
1056928U, // FMULv4f16
|
|
401520U, // FMULv4f32
|
|
161489056U, // FMULv4i16_indexed
|
|
163324016U, // FMULv4i32_indexed
|
|
532600U, // FMULv8f16
|
|
161489016U, // FMULv8i16_indexed
|
|
32U, // FNEGDr
|
|
32U, // FNEGHr
|
|
32U, // FNEGSr
|
|
8U, // FNEG_ZPmZ_D
|
|
0U, // FNEG_ZPmZ_H
|
|
16U, // FNEG_ZPmZ_S
|
|
40U, // FNEGv2f32
|
|
48U, // FNEGv2f64
|
|
56U, // FNEGv4f16
|
|
64U, // FNEGv4f32
|
|
72U, // FNEGv8f16
|
|
134232U, // FNMADDDrrr
|
|
134232U, // FNMADDHrrr
|
|
134232U, // FNMADDSrrr
|
|
134349952U, // FNMAD_ZPmZZ_D
|
|
28978456U, // FNMAD_ZPmZZ_H
|
|
142739584U, // FNMAD_ZPmZZ_S
|
|
134349952U, // FNMLA_ZPmZZ_D
|
|
28978456U, // FNMLA_ZPmZZ_H
|
|
142739584U, // FNMLA_ZPmZZ_S
|
|
134349952U, // FNMLS_ZPmZZ_D
|
|
28978456U, // FNMLS_ZPmZZ_H
|
|
142739584U, // FNMLS_ZPmZZ_S
|
|
134349952U, // FNMSB_ZPmZZ_D
|
|
28978456U, // FNMSB_ZPmZZ_H
|
|
142739584U, // FNMSB_ZPmZZ_S
|
|
134232U, // FNMSUBDrrr
|
|
134232U, // FNMSUBHrrr
|
|
134232U, // FNMSUBSrrr
|
|
3160U, // FNMULDrr
|
|
3160U, // FNMULHrr
|
|
3160U, // FNMULSrr
|
|
32U, // FRECPE_ZZ_D
|
|
0U, // FRECPE_ZZ_H
|
|
32U, // FRECPE_ZZ_S
|
|
32U, // FRECPEv1f16
|
|
32U, // FRECPEv1i32
|
|
32U, // FRECPEv1i64
|
|
40U, // FRECPEv2f32
|
|
48U, // FRECPEv2f64
|
|
56U, // FRECPEv4f16
|
|
64U, // FRECPEv4f32
|
|
72U, // FRECPEv8f16
|
|
3160U, // FRECPS16
|
|
3160U, // FRECPS32
|
|
3160U, // FRECPS64
|
|
6232U, // FRECPS_ZZZ_D
|
|
136U, // FRECPS_ZZZ_H
|
|
12376U, // FRECPS_ZZZ_S
|
|
925848U, // FRECPSv2f32
|
|
270440U, // FRECPSv2f64
|
|
1056928U, // FRECPSv4f16
|
|
401520U, // FRECPSv4f32
|
|
532600U, // FRECPSv8f16
|
|
8U, // FRECPX_ZPmZ_D
|
|
0U, // FRECPX_ZPmZ_H
|
|
16U, // FRECPX_ZPmZ_S
|
|
32U, // FRECPXv1f16
|
|
32U, // FRECPXv1i32
|
|
32U, // FRECPXv1i64
|
|
32U, // FRINT32XDr
|
|
32U, // FRINT32XSr
|
|
40U, // FRINT32Xv2f32
|
|
48U, // FRINT32Xv2f64
|
|
64U, // FRINT32Xv4f32
|
|
32U, // FRINT32ZDr
|
|
32U, // FRINT32ZSr
|
|
40U, // FRINT32Zv2f32
|
|
48U, // FRINT32Zv2f64
|
|
64U, // FRINT32Zv4f32
|
|
32U, // FRINT64XDr
|
|
32U, // FRINT64XSr
|
|
40U, // FRINT64Xv2f32
|
|
48U, // FRINT64Xv2f64
|
|
64U, // FRINT64Xv4f32
|
|
32U, // FRINT64ZDr
|
|
32U, // FRINT64ZSr
|
|
40U, // FRINT64Zv2f32
|
|
48U, // FRINT64Zv2f64
|
|
64U, // FRINT64Zv4f32
|
|
32U, // FRINTADr
|
|
32U, // FRINTAHr
|
|
32U, // FRINTASr
|
|
8U, // FRINTA_ZPmZ_D
|
|
0U, // FRINTA_ZPmZ_H
|
|
16U, // FRINTA_ZPmZ_S
|
|
40U, // FRINTAv2f32
|
|
48U, // FRINTAv2f64
|
|
56U, // FRINTAv4f16
|
|
64U, // FRINTAv4f32
|
|
72U, // FRINTAv8f16
|
|
32U, // FRINTIDr
|
|
32U, // FRINTIHr
|
|
32U, // FRINTISr
|
|
8U, // FRINTI_ZPmZ_D
|
|
0U, // FRINTI_ZPmZ_H
|
|
16U, // FRINTI_ZPmZ_S
|
|
40U, // FRINTIv2f32
|
|
48U, // FRINTIv2f64
|
|
56U, // FRINTIv4f16
|
|
64U, // FRINTIv4f32
|
|
72U, // FRINTIv8f16
|
|
32U, // FRINTMDr
|
|
32U, // FRINTMHr
|
|
32U, // FRINTMSr
|
|
8U, // FRINTM_ZPmZ_D
|
|
0U, // FRINTM_ZPmZ_H
|
|
16U, // FRINTM_ZPmZ_S
|
|
40U, // FRINTMv2f32
|
|
48U, // FRINTMv2f64
|
|
56U, // FRINTMv4f16
|
|
64U, // FRINTMv4f32
|
|
72U, // FRINTMv8f16
|
|
32U, // FRINTNDr
|
|
32U, // FRINTNHr
|
|
32U, // FRINTNSr
|
|
8U, // FRINTN_ZPmZ_D
|
|
0U, // FRINTN_ZPmZ_H
|
|
16U, // FRINTN_ZPmZ_S
|
|
40U, // FRINTNv2f32
|
|
48U, // FRINTNv2f64
|
|
56U, // FRINTNv4f16
|
|
64U, // FRINTNv4f32
|
|
72U, // FRINTNv8f16
|
|
32U, // FRINTPDr
|
|
32U, // FRINTPHr
|
|
32U, // FRINTPSr
|
|
8U, // FRINTP_ZPmZ_D
|
|
0U, // FRINTP_ZPmZ_H
|
|
16U, // FRINTP_ZPmZ_S
|
|
40U, // FRINTPv2f32
|
|
48U, // FRINTPv2f64
|
|
56U, // FRINTPv4f16
|
|
64U, // FRINTPv4f32
|
|
72U, // FRINTPv8f16
|
|
32U, // FRINTXDr
|
|
32U, // FRINTXHr
|
|
32U, // FRINTXSr
|
|
8U, // FRINTX_ZPmZ_D
|
|
0U, // FRINTX_ZPmZ_H
|
|
16U, // FRINTX_ZPmZ_S
|
|
40U, // FRINTXv2f32
|
|
48U, // FRINTXv2f64
|
|
56U, // FRINTXv4f16
|
|
64U, // FRINTXv4f32
|
|
72U, // FRINTXv8f16
|
|
32U, // FRINTZDr
|
|
32U, // FRINTZHr
|
|
32U, // FRINTZSr
|
|
8U, // FRINTZ_ZPmZ_D
|
|
0U, // FRINTZ_ZPmZ_H
|
|
16U, // FRINTZ_ZPmZ_S
|
|
40U, // FRINTZv2f32
|
|
48U, // FRINTZv2f64
|
|
56U, // FRINTZv4f16
|
|
64U, // FRINTZv4f32
|
|
72U, // FRINTZv8f16
|
|
32U, // FRSQRTE_ZZ_D
|
|
0U, // FRSQRTE_ZZ_H
|
|
32U, // FRSQRTE_ZZ_S
|
|
32U, // FRSQRTEv1f16
|
|
32U, // FRSQRTEv1i32
|
|
32U, // FRSQRTEv1i64
|
|
40U, // FRSQRTEv2f32
|
|
48U, // FRSQRTEv2f64
|
|
56U, // FRSQRTEv4f16
|
|
64U, // FRSQRTEv4f32
|
|
72U, // FRSQRTEv8f16
|
|
3160U, // FRSQRTS16
|
|
3160U, // FRSQRTS32
|
|
3160U, // FRSQRTS64
|
|
6232U, // FRSQRTS_ZZZ_D
|
|
136U, // FRSQRTS_ZZZ_H
|
|
12376U, // FRSQRTS_ZZZ_S
|
|
925848U, // FRSQRTSv2f32
|
|
270440U, // FRSQRTSv2f64
|
|
1056928U, // FRSQRTSv4f16
|
|
401520U, // FRSQRTSv4f32
|
|
532600U, // FRSQRTSv8f16
|
|
16914560U, // FSCALE_ZPmZ_D
|
|
25832584U, // FSCALE_ZPmZ_H
|
|
33697920U, // FSCALE_ZPmZ_S
|
|
32U, // FSQRTDr
|
|
32U, // FSQRTHr
|
|
32U, // FSQRTSr
|
|
8U, // FSQRT_ZPmZ_D
|
|
0U, // FSQRT_ZPmZ_H
|
|
16U, // FSQRT_ZPmZ_S
|
|
40U, // FSQRTv2f32
|
|
48U, // FSQRTv2f64
|
|
56U, // FSQRTv4f16
|
|
64U, // FSQRTv4f32
|
|
72U, // FSQRTv8f16
|
|
3160U, // FSUBDrr
|
|
3160U, // FSUBHrr
|
|
125966464U, // FSUBR_ZPmI_D
|
|
2894984U, // FSUBR_ZPmI_H
|
|
125972608U, // FSUBR_ZPmI_S
|
|
16914560U, // FSUBR_ZPmZ_D
|
|
25832584U, // FSUBR_ZPmZ_H
|
|
33697920U, // FSUBR_ZPmZ_S
|
|
3160U, // FSUBSrr
|
|
125966464U, // FSUB_ZPmI_D
|
|
2894984U, // FSUB_ZPmI_H
|
|
125972608U, // FSUB_ZPmI_S
|
|
16914560U, // FSUB_ZPmZ_D
|
|
25832584U, // FSUB_ZPmZ_H
|
|
33697920U, // FSUB_ZPmZ_S
|
|
6232U, // FSUB_ZZZ_D
|
|
136U, // FSUB_ZZZ_H
|
|
12376U, // FSUB_ZZZ_S
|
|
925848U, // FSUBv2f32
|
|
270440U, // FSUBv2f64
|
|
1056928U, // FSUBv4f16
|
|
401520U, // FSUBv4f32
|
|
532600U, // FSUBv8f16
|
|
137304U, // FTMAD_ZZI_D
|
|
1453192U, // FTMAD_ZZI_H
|
|
143448U, // FTMAD_ZZI_S
|
|
6232U, // FTSMUL_ZZZ_D
|
|
136U, // FTSMUL_ZZZ_H
|
|
12376U, // FTSMUL_ZZZ_S
|
|
6232U, // FTSSEL_ZZZ_D
|
|
136U, // FTSSEL_ZZZ_H
|
|
12376U, // FTSSEL_ZZZ_S
|
|
2397272U, // GLD1B_D_IMM_REAL
|
|
50265U, // GLD1B_D_REAL
|
|
51289U, // GLD1B_D_SXTW_REAL
|
|
52313U, // GLD1B_D_UXTW_REAL
|
|
2397272U, // GLD1B_S_IMM_REAL
|
|
53337U, // GLD1B_S_SXTW_REAL
|
|
54361U, // GLD1B_S_UXTW_REAL
|
|
2414680U, // GLD1D_IMM_REAL
|
|
50265U, // GLD1D_REAL
|
|
56409U, // GLD1D_SCALED_REAL
|
|
51289U, // GLD1D_SXTW_REAL
|
|
57433U, // GLD1D_SXTW_SCALED_REAL
|
|
52313U, // GLD1D_UXTW_REAL
|
|
58457U, // GLD1D_UXTW_SCALED_REAL
|
|
2418776U, // GLD1H_D_IMM_REAL
|
|
50265U, // GLD1H_D_REAL
|
|
60505U, // GLD1H_D_SCALED_REAL
|
|
51289U, // GLD1H_D_SXTW_REAL
|
|
61529U, // GLD1H_D_SXTW_SCALED_REAL
|
|
52313U, // GLD1H_D_UXTW_REAL
|
|
62553U, // GLD1H_D_UXTW_SCALED_REAL
|
|
2418776U, // GLD1H_S_IMM_REAL
|
|
53337U, // GLD1H_S_SXTW_REAL
|
|
63577U, // GLD1H_S_SXTW_SCALED_REAL
|
|
54361U, // GLD1H_S_UXTW_REAL
|
|
64601U, // GLD1H_S_UXTW_SCALED_REAL
|
|
2397272U, // GLD1SB_D_IMM_REAL
|
|
50265U, // GLD1SB_D_REAL
|
|
51289U, // GLD1SB_D_SXTW_REAL
|
|
52313U, // GLD1SB_D_UXTW_REAL
|
|
2397272U, // GLD1SB_S_IMM_REAL
|
|
53337U, // GLD1SB_S_SXTW_REAL
|
|
54361U, // GLD1SB_S_UXTW_REAL
|
|
2418776U, // GLD1SH_D_IMM_REAL
|
|
50265U, // GLD1SH_D_REAL
|
|
60505U, // GLD1SH_D_SCALED_REAL
|
|
51289U, // GLD1SH_D_SXTW_REAL
|
|
61529U, // GLD1SH_D_SXTW_SCALED_REAL
|
|
52313U, // GLD1SH_D_UXTW_REAL
|
|
62553U, // GLD1SH_D_UXTW_SCALED_REAL
|
|
2418776U, // GLD1SH_S_IMM_REAL
|
|
53337U, // GLD1SH_S_SXTW_REAL
|
|
63577U, // GLD1SH_S_SXTW_SCALED_REAL
|
|
54361U, // GLD1SH_S_UXTW_REAL
|
|
64601U, // GLD1SH_S_UXTW_SCALED_REAL
|
|
2424920U, // GLD1SW_D_IMM_REAL
|
|
50265U, // GLD1SW_D_REAL
|
|
66649U, // GLD1SW_D_SCALED_REAL
|
|
51289U, // GLD1SW_D_SXTW_REAL
|
|
67673U, // GLD1SW_D_SXTW_SCALED_REAL
|
|
52313U, // GLD1SW_D_UXTW_REAL
|
|
68697U, // GLD1SW_D_UXTW_SCALED_REAL
|
|
2424920U, // GLD1W_D_IMM_REAL
|
|
50265U, // GLD1W_D_REAL
|
|
66649U, // GLD1W_D_SCALED_REAL
|
|
51289U, // GLD1W_D_SXTW_REAL
|
|
67673U, // GLD1W_D_SXTW_SCALED_REAL
|
|
52313U, // GLD1W_D_UXTW_REAL
|
|
68697U, // GLD1W_D_UXTW_SCALED_REAL
|
|
2424920U, // GLD1W_IMM_REAL
|
|
53337U, // GLD1W_SXTW_REAL
|
|
69721U, // GLD1W_SXTW_SCALED_REAL
|
|
54361U, // GLD1W_UXTW_REAL
|
|
70745U, // GLD1W_UXTW_SCALED_REAL
|
|
2397272U, // GLDFF1B_D_IMM_REAL
|
|
50265U, // GLDFF1B_D_REAL
|
|
51289U, // GLDFF1B_D_SXTW_REAL
|
|
52313U, // GLDFF1B_D_UXTW_REAL
|
|
2397272U, // GLDFF1B_S_IMM_REAL
|
|
53337U, // GLDFF1B_S_SXTW_REAL
|
|
54361U, // GLDFF1B_S_UXTW_REAL
|
|
2414680U, // GLDFF1D_IMM_REAL
|
|
50265U, // GLDFF1D_REAL
|
|
56409U, // GLDFF1D_SCALED_REAL
|
|
51289U, // GLDFF1D_SXTW_REAL
|
|
57433U, // GLDFF1D_SXTW_SCALED_REAL
|
|
52313U, // GLDFF1D_UXTW_REAL
|
|
58457U, // GLDFF1D_UXTW_SCALED_REAL
|
|
2418776U, // GLDFF1H_D_IMM_REAL
|
|
50265U, // GLDFF1H_D_REAL
|
|
60505U, // GLDFF1H_D_SCALED_REAL
|
|
51289U, // GLDFF1H_D_SXTW_REAL
|
|
61529U, // GLDFF1H_D_SXTW_SCALED_REAL
|
|
52313U, // GLDFF1H_D_UXTW_REAL
|
|
62553U, // GLDFF1H_D_UXTW_SCALED_REAL
|
|
2418776U, // GLDFF1H_S_IMM_REAL
|
|
53337U, // GLDFF1H_S_SXTW_REAL
|
|
63577U, // GLDFF1H_S_SXTW_SCALED_REAL
|
|
54361U, // GLDFF1H_S_UXTW_REAL
|
|
64601U, // GLDFF1H_S_UXTW_SCALED_REAL
|
|
2397272U, // GLDFF1SB_D_IMM_REAL
|
|
50265U, // GLDFF1SB_D_REAL
|
|
51289U, // GLDFF1SB_D_SXTW_REAL
|
|
52313U, // GLDFF1SB_D_UXTW_REAL
|
|
2397272U, // GLDFF1SB_S_IMM_REAL
|
|
53337U, // GLDFF1SB_S_SXTW_REAL
|
|
54361U, // GLDFF1SB_S_UXTW_REAL
|
|
2418776U, // GLDFF1SH_D_IMM_REAL
|
|
50265U, // GLDFF1SH_D_REAL
|
|
60505U, // GLDFF1SH_D_SCALED_REAL
|
|
51289U, // GLDFF1SH_D_SXTW_REAL
|
|
61529U, // GLDFF1SH_D_SXTW_SCALED_REAL
|
|
52313U, // GLDFF1SH_D_UXTW_REAL
|
|
62553U, // GLDFF1SH_D_UXTW_SCALED_REAL
|
|
2418776U, // GLDFF1SH_S_IMM_REAL
|
|
53337U, // GLDFF1SH_S_SXTW_REAL
|
|
63577U, // GLDFF1SH_S_SXTW_SCALED_REAL
|
|
54361U, // GLDFF1SH_S_UXTW_REAL
|
|
64601U, // GLDFF1SH_S_UXTW_SCALED_REAL
|
|
2424920U, // GLDFF1SW_D_IMM_REAL
|
|
50265U, // GLDFF1SW_D_REAL
|
|
66649U, // GLDFF1SW_D_SCALED_REAL
|
|
51289U, // GLDFF1SW_D_SXTW_REAL
|
|
67673U, // GLDFF1SW_D_SXTW_SCALED_REAL
|
|
52313U, // GLDFF1SW_D_UXTW_REAL
|
|
68697U, // GLDFF1SW_D_UXTW_SCALED_REAL
|
|
2424920U, // GLDFF1W_D_IMM_REAL
|
|
50265U, // GLDFF1W_D_REAL
|
|
66649U, // GLDFF1W_D_SCALED_REAL
|
|
51289U, // GLDFF1W_D_SXTW_REAL
|
|
67673U, // GLDFF1W_D_SXTW_SCALED_REAL
|
|
52313U, // GLDFF1W_D_UXTW_REAL
|
|
68697U, // GLDFF1W_D_UXTW_SCALED_REAL
|
|
2424920U, // GLDFF1W_IMM_REAL
|
|
53337U, // GLDFF1W_SXTW_REAL
|
|
69721U, // GLDFF1W_SXTW_SCALED_REAL
|
|
54361U, // GLDFF1W_UXTW_REAL
|
|
70745U, // GLDFF1W_UXTW_SCALED_REAL
|
|
3160U, // GMI
|
|
0U, // HINT
|
|
16914616U, // HISTCNT_ZPzZZ_D
|
|
33697976U, // HISTCNT_ZPzZZ_S
|
|
10328U, // HISTSEG_ZZZ
|
|
0U, // HLT
|
|
0U, // HVC
|
|
1U, // INCB_XPiI
|
|
1U, // INCD_XPiI
|
|
1U, // INCD_ZPiI
|
|
1U, // INCH_XPiI
|
|
0U, // INCH_ZPiI
|
|
32U, // INCP_XP_B
|
|
32U, // INCP_XP_D
|
|
32U, // INCP_XP_H
|
|
32U, // INCP_XP_S
|
|
32U, // INCP_ZP_D
|
|
0U, // INCP_ZP_H
|
|
32U, // INCP_ZP_S
|
|
1U, // INCW_XPiI
|
|
1U, // INCW_ZPiI
|
|
490U, // INDEX_II_B
|
|
3160U, // INDEX_II_D
|
|
2U, // INDEX_II_H
|
|
3160U, // INDEX_II_S
|
|
202U, // INDEX_IR_B
|
|
3160U, // INDEX_IR_D
|
|
33U, // INDEX_IR_H
|
|
3160U, // INDEX_IR_S
|
|
71768U, // INDEX_RI_B
|
|
3160U, // INDEX_RI_D
|
|
496U, // INDEX_RI_H
|
|
3160U, // INDEX_RI_S
|
|
3160U, // INDEX_RR_B
|
|
3160U, // INDEX_RR_D
|
|
200U, // INDEX_RR_H
|
|
3160U, // INDEX_RR_S
|
|
506U, // INSERT_MXIPZ_H_B
|
|
474U, // INSERT_MXIPZ_H_D
|
|
514U, // INSERT_MXIPZ_H_H
|
|
522U, // INSERT_MXIPZ_H_Q
|
|
482U, // INSERT_MXIPZ_H_S
|
|
506U, // INSERT_MXIPZ_V_B
|
|
474U, // INSERT_MXIPZ_V_D
|
|
514U, // INSERT_MXIPZ_V_H
|
|
522U, // INSERT_MXIPZ_V_Q
|
|
482U, // INSERT_MXIPZ_V_S
|
|
33U, // INSR_ZR_B
|
|
33U, // INSR_ZR_D
|
|
0U, // INSR_ZR_H
|
|
33U, // INSR_ZR_S
|
|
2U, // INSR_ZV_B
|
|
2U, // INSR_ZV_D
|
|
0U, // INSR_ZV_H
|
|
2U, // INSR_ZV_S
|
|
1U, // INSvi16gpr
|
|
39258U, // INSvi16lane
|
|
1U, // INSvi32gpr
|
|
39266U, // INSvi32lane
|
|
1U, // INSvi64gpr
|
|
39274U, // INSvi64lane
|
|
1U, // INSvi8gpr
|
|
39282U, // INSvi8lane
|
|
3160U, // IRG
|
|
0U, // ISB
|
|
10328U, // LASTA_RPZ_B
|
|
6232U, // LASTA_RPZ_D
|
|
5208U, // LASTA_RPZ_H
|
|
12376U, // LASTA_RPZ_S
|
|
10328U, // LASTA_VPZ_B
|
|
6232U, // LASTA_VPZ_D
|
|
5208U, // LASTA_VPZ_H
|
|
12376U, // LASTA_VPZ_S
|
|
10328U, // LASTB_RPZ_B
|
|
6232U, // LASTB_RPZ_D
|
|
5208U, // LASTB_RPZ_H
|
|
12376U, // LASTB_RPZ_S
|
|
10328U, // LASTB_VPZ_B
|
|
6232U, // LASTB_VPZ_D
|
|
5208U, // LASTB_VPZ_H
|
|
12376U, // LASTB_VPZ_S
|
|
72793U, // LD1B
|
|
72793U, // LD1B_D
|
|
4625497U, // LD1B_D_IMM_REAL
|
|
72793U, // LD1B_H
|
|
4625497U, // LD1B_H_IMM_REAL
|
|
4625497U, // LD1B_IMM_REAL
|
|
72793U, // LD1B_S
|
|
4625497U, // LD1B_S_IMM_REAL
|
|
73817U, // LD1D
|
|
4625497U, // LD1D_IMM_REAL
|
|
0U, // LD1Fourv16b
|
|
0U, // LD1Fourv16b_POST
|
|
0U, // LD1Fourv1d
|
|
0U, // LD1Fourv1d_POST
|
|
0U, // LD1Fourv2d
|
|
0U, // LD1Fourv2d_POST
|
|
0U, // LD1Fourv2s
|
|
0U, // LD1Fourv2s_POST
|
|
0U, // LD1Fourv4h
|
|
0U, // LD1Fourv4h_POST
|
|
0U, // LD1Fourv4s
|
|
0U, // LD1Fourv4s_POST
|
|
0U, // LD1Fourv8b
|
|
0U, // LD1Fourv8b_POST
|
|
0U, // LD1Fourv8h
|
|
0U, // LD1Fourv8h_POST
|
|
74841U, // LD1H
|
|
74841U, // LD1H_D
|
|
4625497U, // LD1H_D_IMM_REAL
|
|
4625497U, // LD1H_IMM_REAL
|
|
74841U, // LD1H_S
|
|
4625497U, // LD1H_S_IMM_REAL
|
|
0U, // LD1Onev16b
|
|
0U, // LD1Onev16b_POST
|
|
0U, // LD1Onev1d
|
|
0U, // LD1Onev1d_POST
|
|
0U, // LD1Onev2d
|
|
0U, // LD1Onev2d_POST
|
|
0U, // LD1Onev2s
|
|
0U, // LD1Onev2s_POST
|
|
0U, // LD1Onev4h
|
|
0U, // LD1Onev4h_POST
|
|
0U, // LD1Onev4s
|
|
0U, // LD1Onev4s_POST
|
|
0U, // LD1Onev8b
|
|
0U, // LD1Onev8b_POST
|
|
0U, // LD1Onev8h
|
|
0U, // LD1Onev8h_POST
|
|
2397273U, // LD1RB_D_IMM
|
|
2397273U, // LD1RB_H_IMM
|
|
2397273U, // LD1RB_IMM
|
|
2397273U, // LD1RB_S_IMM
|
|
2414681U, // LD1RD_IMM
|
|
2418777U, // LD1RH_D_IMM
|
|
2418777U, // LD1RH_IMM
|
|
2418777U, // LD1RH_S_IMM
|
|
72793U, // LD1RO_B
|
|
75865U, // LD1RO_B_IMM
|
|
73817U, // LD1RO_D
|
|
75865U, // LD1RO_D_IMM
|
|
74841U, // LD1RO_H
|
|
75865U, // LD1RO_H_IMM
|
|
76889U, // LD1RO_W
|
|
75865U, // LD1RO_W_IMM
|
|
72793U, // LD1RQ_B
|
|
2437209U, // LD1RQ_B_IMM
|
|
73817U, // LD1RQ_D
|
|
2437209U, // LD1RQ_D_IMM
|
|
74841U, // LD1RQ_H
|
|
2437209U, // LD1RQ_H_IMM
|
|
76889U, // LD1RQ_W
|
|
2437209U, // LD1RQ_W_IMM
|
|
2397273U, // LD1RSB_D_IMM
|
|
2397273U, // LD1RSB_H_IMM
|
|
2397273U, // LD1RSB_S_IMM
|
|
2418777U, // LD1RSH_D_IMM
|
|
2418777U, // LD1RSH_S_IMM
|
|
2424921U, // LD1RSW_IMM
|
|
2424921U, // LD1RW_D_IMM
|
|
2424921U, // LD1RW_IMM
|
|
0U, // LD1Rv16b
|
|
0U, // LD1Rv16b_POST
|
|
0U, // LD1Rv1d
|
|
0U, // LD1Rv1d_POST
|
|
0U, // LD1Rv2d
|
|
0U, // LD1Rv2d_POST
|
|
0U, // LD1Rv2s
|
|
0U, // LD1Rv2s_POST
|
|
0U, // LD1Rv4h
|
|
0U, // LD1Rv4h_POST
|
|
0U, // LD1Rv4s
|
|
0U, // LD1Rv4s_POST
|
|
0U, // LD1Rv8b
|
|
0U, // LD1Rv8b_POST
|
|
0U, // LD1Rv8h
|
|
0U, // LD1Rv8h_POST
|
|
72793U, // LD1SB_D
|
|
4625497U, // LD1SB_D_IMM_REAL
|
|
72793U, // LD1SB_H
|
|
4625497U, // LD1SB_H_IMM_REAL
|
|
72793U, // LD1SB_S
|
|
4625497U, // LD1SB_S_IMM_REAL
|
|
74841U, // LD1SH_D
|
|
4625497U, // LD1SH_D_IMM_REAL
|
|
74841U, // LD1SH_S
|
|
4625497U, // LD1SH_S_IMM_REAL
|
|
76889U, // LD1SW_D
|
|
4625497U, // LD1SW_D_IMM_REAL
|
|
0U, // LD1Threev16b
|
|
0U, // LD1Threev16b_POST
|
|
0U, // LD1Threev1d
|
|
0U, // LD1Threev1d_POST
|
|
0U, // LD1Threev2d
|
|
0U, // LD1Threev2d_POST
|
|
0U, // LD1Threev2s
|
|
0U, // LD1Threev2s_POST
|
|
0U, // LD1Threev4h
|
|
0U, // LD1Threev4h_POST
|
|
0U, // LD1Threev4s
|
|
0U, // LD1Threev4s_POST
|
|
0U, // LD1Threev8b
|
|
0U, // LD1Threev8b_POST
|
|
0U, // LD1Threev8h
|
|
0U, // LD1Threev8h_POST
|
|
0U, // LD1Twov16b
|
|
0U, // LD1Twov16b_POST
|
|
0U, // LD1Twov1d
|
|
0U, // LD1Twov1d_POST
|
|
0U, // LD1Twov2d
|
|
0U, // LD1Twov2d_POST
|
|
0U, // LD1Twov2s
|
|
0U, // LD1Twov2s_POST
|
|
0U, // LD1Twov4h
|
|
0U, // LD1Twov4h_POST
|
|
0U, // LD1Twov4s
|
|
0U, // LD1Twov4s_POST
|
|
0U, // LD1Twov8b
|
|
0U, // LD1Twov8b_POST
|
|
0U, // LD1Twov8h
|
|
0U, // LD1Twov8h_POST
|
|
76889U, // LD1W
|
|
76889U, // LD1W_D
|
|
4625497U, // LD1W_D_IMM_REAL
|
|
4625497U, // LD1W_IMM_REAL
|
|
530U, // LD1_MXIPXX_H_B
|
|
538U, // LD1_MXIPXX_H_D
|
|
546U, // LD1_MXIPXX_H_H
|
|
554U, // LD1_MXIPXX_H_Q
|
|
562U, // LD1_MXIPXX_H_S
|
|
530U, // LD1_MXIPXX_V_B
|
|
538U, // LD1_MXIPXX_V_D
|
|
546U, // LD1_MXIPXX_V_H
|
|
554U, // LD1_MXIPXX_V_Q
|
|
562U, // LD1_MXIPXX_V_S
|
|
0U, // LD1i16
|
|
0U, // LD1i16_POST
|
|
0U, // LD1i32
|
|
0U, // LD1i32_POST
|
|
0U, // LD1i64
|
|
0U, // LD1i64_POST
|
|
0U, // LD1i8
|
|
0U, // LD1i8_POST
|
|
72793U, // LD2B
|
|
4647001U, // LD2B_IMM
|
|
73817U, // LD2D
|
|
4647001U, // LD2D_IMM
|
|
74841U, // LD2H
|
|
4647001U, // LD2H_IMM
|
|
0U, // LD2Rv16b
|
|
0U, // LD2Rv16b_POST
|
|
0U, // LD2Rv1d
|
|
0U, // LD2Rv1d_POST
|
|
0U, // LD2Rv2d
|
|
0U, // LD2Rv2d_POST
|
|
0U, // LD2Rv2s
|
|
0U, // LD2Rv2s_POST
|
|
0U, // LD2Rv4h
|
|
0U, // LD2Rv4h_POST
|
|
0U, // LD2Rv4s
|
|
0U, // LD2Rv4s_POST
|
|
0U, // LD2Rv8b
|
|
0U, // LD2Rv8b_POST
|
|
0U, // LD2Rv8h
|
|
0U, // LD2Rv8h_POST
|
|
0U, // LD2Twov16b
|
|
0U, // LD2Twov16b_POST
|
|
0U, // LD2Twov2d
|
|
0U, // LD2Twov2d_POST
|
|
0U, // LD2Twov2s
|
|
0U, // LD2Twov2s_POST
|
|
0U, // LD2Twov4h
|
|
0U, // LD2Twov4h_POST
|
|
0U, // LD2Twov4s
|
|
0U, // LD2Twov4s_POST
|
|
0U, // LD2Twov8b
|
|
0U, // LD2Twov8b_POST
|
|
0U, // LD2Twov8h
|
|
0U, // LD2Twov8h_POST
|
|
76889U, // LD2W
|
|
4647001U, // LD2W_IMM
|
|
0U, // LD2i16
|
|
0U, // LD2i16_POST
|
|
0U, // LD2i32
|
|
0U, // LD2i32_POST
|
|
0U, // LD2i64
|
|
0U, // LD2i64_POST
|
|
0U, // LD2i8
|
|
0U, // LD2i8_POST
|
|
72793U, // LD3B
|
|
78937U, // LD3B_IMM
|
|
73817U, // LD3D
|
|
78937U, // LD3D_IMM
|
|
74841U, // LD3H
|
|
78937U, // LD3H_IMM
|
|
0U, // LD3Rv16b
|
|
0U, // LD3Rv16b_POST
|
|
0U, // LD3Rv1d
|
|
0U, // LD3Rv1d_POST
|
|
0U, // LD3Rv2d
|
|
0U, // LD3Rv2d_POST
|
|
0U, // LD3Rv2s
|
|
0U, // LD3Rv2s_POST
|
|
0U, // LD3Rv4h
|
|
0U, // LD3Rv4h_POST
|
|
0U, // LD3Rv4s
|
|
0U, // LD3Rv4s_POST
|
|
0U, // LD3Rv8b
|
|
0U, // LD3Rv8b_POST
|
|
0U, // LD3Rv8h
|
|
0U, // LD3Rv8h_POST
|
|
0U, // LD3Threev16b
|
|
0U, // LD3Threev16b_POST
|
|
0U, // LD3Threev2d
|
|
0U, // LD3Threev2d_POST
|
|
0U, // LD3Threev2s
|
|
0U, // LD3Threev2s_POST
|
|
0U, // LD3Threev4h
|
|
0U, // LD3Threev4h_POST
|
|
0U, // LD3Threev4s
|
|
0U, // LD3Threev4s_POST
|
|
0U, // LD3Threev8b
|
|
0U, // LD3Threev8b_POST
|
|
0U, // LD3Threev8h
|
|
0U, // LD3Threev8h_POST
|
|
76889U, // LD3W
|
|
78937U, // LD3W_IMM
|
|
0U, // LD3i16
|
|
0U, // LD3i16_POST
|
|
0U, // LD3i32
|
|
0U, // LD3i32_POST
|
|
0U, // LD3i64
|
|
0U, // LD3i64_POST
|
|
0U, // LD3i8
|
|
0U, // LD3i8_POST
|
|
72793U, // LD4B
|
|
4653145U, // LD4B_IMM
|
|
73817U, // LD4D
|
|
4653145U, // LD4D_IMM
|
|
0U, // LD4Fourv16b
|
|
0U, // LD4Fourv16b_POST
|
|
0U, // LD4Fourv2d
|
|
0U, // LD4Fourv2d_POST
|
|
0U, // LD4Fourv2s
|
|
0U, // LD4Fourv2s_POST
|
|
0U, // LD4Fourv4h
|
|
0U, // LD4Fourv4h_POST
|
|
0U, // LD4Fourv4s
|
|
0U, // LD4Fourv4s_POST
|
|
0U, // LD4Fourv8b
|
|
0U, // LD4Fourv8b_POST
|
|
0U, // LD4Fourv8h
|
|
0U, // LD4Fourv8h_POST
|
|
74841U, // LD4H
|
|
4653145U, // LD4H_IMM
|
|
0U, // LD4Rv16b
|
|
0U, // LD4Rv16b_POST
|
|
0U, // LD4Rv1d
|
|
0U, // LD4Rv1d_POST
|
|
0U, // LD4Rv2d
|
|
0U, // LD4Rv2d_POST
|
|
0U, // LD4Rv2s
|
|
0U, // LD4Rv2s_POST
|
|
0U, // LD4Rv4h
|
|
0U, // LD4Rv4h_POST
|
|
0U, // LD4Rv4s
|
|
0U, // LD4Rv4s_POST
|
|
0U, // LD4Rv8b
|
|
0U, // LD4Rv8b_POST
|
|
0U, // LD4Rv8h
|
|
0U, // LD4Rv8h_POST
|
|
76889U, // LD4W
|
|
4653145U, // LD4W_IMM
|
|
0U, // LD4i16
|
|
0U, // LD4i16_POST
|
|
0U, // LD4i32
|
|
0U, // LD4i32_POST
|
|
0U, // LD4i64
|
|
0U, // LD4i64_POST
|
|
0U, // LD4i8
|
|
0U, // LD4i8_POST
|
|
0U, // LD64B
|
|
2U, // LDADDAB
|
|
2U, // LDADDAH
|
|
2U, // LDADDALB
|
|
2U, // LDADDALH
|
|
2U, // LDADDALW
|
|
2U, // LDADDALX
|
|
2U, // LDADDAW
|
|
2U, // LDADDAX
|
|
2U, // LDADDB
|
|
2U, // LDADDH
|
|
2U, // LDADDLB
|
|
2U, // LDADDLH
|
|
2U, // LDADDLW
|
|
2U, // LDADDLX
|
|
2U, // LDADDW
|
|
2U, // LDADDX
|
|
568U, // LDAPRB
|
|
568U, // LDAPRH
|
|
568U, // LDAPRW
|
|
568U, // LDAPRX
|
|
2362456U, // LDAPURBi
|
|
2362456U, // LDAPURHi
|
|
2362456U, // LDAPURSBWi
|
|
2362456U, // LDAPURSBXi
|
|
2362456U, // LDAPURSHWi
|
|
2362456U, // LDAPURSHXi
|
|
2362456U, // LDAPURSWi
|
|
2362456U, // LDAPURXi
|
|
2362456U, // LDAPURi
|
|
568U, // LDARB
|
|
568U, // LDARH
|
|
568U, // LDARW
|
|
568U, // LDARX
|
|
2362576U, // LDAXPW
|
|
2362576U, // LDAXPX
|
|
568U, // LDAXRB
|
|
568U, // LDAXRH
|
|
568U, // LDAXRW
|
|
568U, // LDAXRX
|
|
2U, // LDCLRAB
|
|
2U, // LDCLRAH
|
|
2U, // LDCLRALB
|
|
2U, // LDCLRALH
|
|
2U, // LDCLRALW
|
|
2U, // LDCLRALX
|
|
2U, // LDCLRAW
|
|
2U, // LDCLRAX
|
|
2U, // LDCLRB
|
|
2U, // LDCLRH
|
|
2U, // LDCLRLB
|
|
2U, // LDCLRLH
|
|
2U, // LDCLRLW
|
|
2U, // LDCLRLX
|
|
2U, // LDCLRW
|
|
2U, // LDCLRX
|
|
2U, // LDEORAB
|
|
2U, // LDEORAH
|
|
2U, // LDEORALB
|
|
2U, // LDEORALH
|
|
2U, // LDEORALW
|
|
2U, // LDEORALX
|
|
2U, // LDEORAW
|
|
2U, // LDEORAX
|
|
2U, // LDEORB
|
|
2U, // LDEORH
|
|
2U, // LDEORLB
|
|
2U, // LDEORLH
|
|
2U, // LDEORLW
|
|
2U, // LDEORLX
|
|
2U, // LDEORW
|
|
2U, // LDEORX
|
|
72793U, // LDFF1B_D_REAL
|
|
72793U, // LDFF1B_H_REAL
|
|
72793U, // LDFF1B_REAL
|
|
72793U, // LDFF1B_S_REAL
|
|
73817U, // LDFF1D_REAL
|
|
74841U, // LDFF1H_D_REAL
|
|
74841U, // LDFF1H_REAL
|
|
74841U, // LDFF1H_S_REAL
|
|
72793U, // LDFF1SB_D_REAL
|
|
72793U, // LDFF1SB_H_REAL
|
|
72793U, // LDFF1SB_S_REAL
|
|
74841U, // LDFF1SH_D_REAL
|
|
74841U, // LDFF1SH_S_REAL
|
|
76889U, // LDFF1SW_D_REAL
|
|
76889U, // LDFF1W_D_REAL
|
|
76889U, // LDFF1W_REAL
|
|
2437209U, // LDG
|
|
568U, // LDGM
|
|
568U, // LDLARB
|
|
568U, // LDLARH
|
|
568U, // LDLARW
|
|
568U, // LDLARX
|
|
4625497U, // LDNF1B_D_IMM_REAL
|
|
4625497U, // LDNF1B_H_IMM_REAL
|
|
4625497U, // LDNF1B_IMM_REAL
|
|
4625497U, // LDNF1B_S_IMM_REAL
|
|
4625497U, // LDNF1D_IMM_REAL
|
|
4625497U, // LDNF1H_D_IMM_REAL
|
|
4625497U, // LDNF1H_IMM_REAL
|
|
4625497U, // LDNF1H_S_IMM_REAL
|
|
4625497U, // LDNF1SB_D_IMM_REAL
|
|
4625497U, // LDNF1SB_H_IMM_REAL
|
|
4625497U, // LDNF1SB_S_IMM_REAL
|
|
4625497U, // LDNF1SH_D_IMM_REAL
|
|
4625497U, // LDNF1SH_S_IMM_REAL
|
|
4625497U, // LDNF1SW_D_IMM_REAL
|
|
4625497U, // LDNF1W_D_IMM_REAL
|
|
4625497U, // LDNF1W_IMM_REAL
|
|
176295120U, // LDNPDi
|
|
184683728U, // LDNPQi
|
|
193072336U, // LDNPSi
|
|
193072336U, // LDNPWi
|
|
176295120U, // LDNPXi
|
|
4625497U, // LDNT1B_ZRI
|
|
72793U, // LDNT1B_ZRR
|
|
2397272U, // LDNT1B_ZZR_D_REAL
|
|
2397272U, // LDNT1B_ZZR_S_REAL
|
|
4625497U, // LDNT1D_ZRI
|
|
73817U, // LDNT1D_ZRR
|
|
2397272U, // LDNT1D_ZZR_D_REAL
|
|
4625497U, // LDNT1H_ZRI
|
|
74841U, // LDNT1H_ZRR
|
|
2397272U, // LDNT1H_ZZR_D_REAL
|
|
2397272U, // LDNT1H_ZZR_S_REAL
|
|
2397272U, // LDNT1SB_ZZR_D_REAL
|
|
2397272U, // LDNT1SB_ZZR_S_REAL
|
|
2397272U, // LDNT1SH_ZZR_D_REAL
|
|
2397272U, // LDNT1SH_ZZR_S_REAL
|
|
2397272U, // LDNT1SW_ZZR_D_REAL
|
|
4625497U, // LDNT1W_ZRI
|
|
76889U, // LDNT1W_ZRR
|
|
2397272U, // LDNT1W_ZZR_D_REAL
|
|
2397272U, // LDNT1W_ZZR_S_REAL
|
|
176295120U, // LDPDi
|
|
206083281U, // LDPDpost
|
|
2885850321U, // LDPDpre
|
|
184683728U, // LDPQi
|
|
214471889U, // LDPQpost
|
|
2894238929U, // LDPQpre
|
|
193072336U, // LDPSWi
|
|
222860497U, // LDPSWpost
|
|
2902627537U, // LDPSWpre
|
|
193072336U, // LDPSi
|
|
222860497U, // LDPSpost
|
|
2902627537U, // LDPSpre
|
|
193072336U, // LDPWi
|
|
222860497U, // LDPWpost
|
|
2902627537U, // LDPWpre
|
|
176295120U, // LDPXi
|
|
206083281U, // LDPXpost
|
|
2885850321U, // LDPXpre
|
|
79960U, // LDRAAindexed
|
|
4905049U, // LDRAAwriteback
|
|
79960U, // LDRABindexed
|
|
4905049U, // LDRABwriteback
|
|
38465U, // LDRBBpost
|
|
4887641U, // LDRBBpre
|
|
226626648U, // LDRBBroW
|
|
235015256U, // LDRBBroX
|
|
80984U, // LDRBBui
|
|
38465U, // LDRBpost
|
|
4887641U, // LDRBpre
|
|
226626648U, // LDRBroW
|
|
235015256U, // LDRBroX
|
|
80984U, // LDRBui
|
|
1U, // LDRDl
|
|
38465U, // LDRDpost
|
|
4887641U, // LDRDpre
|
|
243403864U, // LDRDroW
|
|
251792472U, // LDRDroX
|
|
82008U, // LDRDui
|
|
38465U, // LDRHHpost
|
|
4887641U, // LDRHHpre
|
|
260181080U, // LDRHHroW
|
|
268569688U, // LDRHHroX
|
|
83032U, // LDRHHui
|
|
38465U, // LDRHpost
|
|
4887641U, // LDRHpre
|
|
260181080U, // LDRHroW
|
|
268569688U, // LDRHroX
|
|
83032U, // LDRHui
|
|
1U, // LDRQl
|
|
38465U, // LDRQpost
|
|
4887641U, // LDRQpre
|
|
276958296U, // LDRQroW
|
|
285346904U, // LDRQroX
|
|
84056U, // LDRQui
|
|
38465U, // LDRSBWpost
|
|
4887641U, // LDRSBWpre
|
|
226626648U, // LDRSBWroW
|
|
235015256U, // LDRSBWroX
|
|
80984U, // LDRSBWui
|
|
38465U, // LDRSBXpost
|
|
4887641U, // LDRSBXpre
|
|
226626648U, // LDRSBXroW
|
|
235015256U, // LDRSBXroX
|
|
80984U, // LDRSBXui
|
|
38465U, // LDRSHWpost
|
|
4887641U, // LDRSHWpre
|
|
260181080U, // LDRSHWroW
|
|
268569688U, // LDRSHWroX
|
|
83032U, // LDRSHWui
|
|
38465U, // LDRSHXpost
|
|
4887641U, // LDRSHXpre
|
|
260181080U, // LDRSHXroW
|
|
268569688U, // LDRSHXroX
|
|
83032U, // LDRSHXui
|
|
1U, // LDRSWl
|
|
38465U, // LDRSWpost
|
|
4887641U, // LDRSWpre
|
|
293735512U, // LDRSWroW
|
|
302124120U, // LDRSWroX
|
|
85080U, // LDRSWui
|
|
1U, // LDRSl
|
|
38465U, // LDRSpost
|
|
4887641U, // LDRSpre
|
|
293735512U, // LDRSroW
|
|
302124120U, // LDRSroX
|
|
85080U, // LDRSui
|
|
1U, // LDRWl
|
|
38465U, // LDRWpost
|
|
4887641U, // LDRWpre
|
|
293735512U, // LDRWroW
|
|
302124120U, // LDRWroX
|
|
85080U, // LDRWui
|
|
1U, // LDRXl
|
|
38465U, // LDRXpost
|
|
4887641U, // LDRXpre
|
|
243403864U, // LDRXroW
|
|
251792472U, // LDRXroX
|
|
82008U, // LDRXui
|
|
4590680U, // LDR_PXI
|
|
0U, // LDR_ZA
|
|
4590680U, // LDR_ZXI
|
|
2U, // LDSETAB
|
|
2U, // LDSETAH
|
|
2U, // LDSETALB
|
|
2U, // LDSETALH
|
|
2U, // LDSETALW
|
|
2U, // LDSETALX
|
|
2U, // LDSETAW
|
|
2U, // LDSETAX
|
|
2U, // LDSETB
|
|
2U, // LDSETH
|
|
2U, // LDSETLB
|
|
2U, // LDSETLH
|
|
2U, // LDSETLW
|
|
2U, // LDSETLX
|
|
2U, // LDSETW
|
|
2U, // LDSETX
|
|
2U, // LDSMAXAB
|
|
2U, // LDSMAXAH
|
|
2U, // LDSMAXALB
|
|
2U, // LDSMAXALH
|
|
2U, // LDSMAXALW
|
|
2U, // LDSMAXALX
|
|
2U, // LDSMAXAW
|
|
2U, // LDSMAXAX
|
|
2U, // LDSMAXB
|
|
2U, // LDSMAXH
|
|
2U, // LDSMAXLB
|
|
2U, // LDSMAXLH
|
|
2U, // LDSMAXLW
|
|
2U, // LDSMAXLX
|
|
2U, // LDSMAXW
|
|
2U, // LDSMAXX
|
|
2U, // LDSMINAB
|
|
2U, // LDSMINAH
|
|
2U, // LDSMINALB
|
|
2U, // LDSMINALH
|
|
2U, // LDSMINALW
|
|
2U, // LDSMINALX
|
|
2U, // LDSMINAW
|
|
2U, // LDSMINAX
|
|
2U, // LDSMINB
|
|
2U, // LDSMINH
|
|
2U, // LDSMINLB
|
|
2U, // LDSMINLH
|
|
2U, // LDSMINLW
|
|
2U, // LDSMINLX
|
|
2U, // LDSMINW
|
|
2U, // LDSMINX
|
|
2362456U, // LDTRBi
|
|
2362456U, // LDTRHi
|
|
2362456U, // LDTRSBWi
|
|
2362456U, // LDTRSBXi
|
|
2362456U, // LDTRSHWi
|
|
2362456U, // LDTRSHXi
|
|
2362456U, // LDTRSWi
|
|
2362456U, // LDTRWi
|
|
2362456U, // LDTRXi
|
|
2U, // LDUMAXAB
|
|
2U, // LDUMAXAH
|
|
2U, // LDUMAXALB
|
|
2U, // LDUMAXALH
|
|
2U, // LDUMAXALW
|
|
2U, // LDUMAXALX
|
|
2U, // LDUMAXAW
|
|
2U, // LDUMAXAX
|
|
2U, // LDUMAXB
|
|
2U, // LDUMAXH
|
|
2U, // LDUMAXLB
|
|
2U, // LDUMAXLH
|
|
2U, // LDUMAXLW
|
|
2U, // LDUMAXLX
|
|
2U, // LDUMAXW
|
|
2U, // LDUMAXX
|
|
2U, // LDUMINAB
|
|
2U, // LDUMINAH
|
|
2U, // LDUMINALB
|
|
2U, // LDUMINALH
|
|
2U, // LDUMINALW
|
|
2U, // LDUMINALX
|
|
2U, // LDUMINAW
|
|
2U, // LDUMINAX
|
|
2U, // LDUMINB
|
|
2U, // LDUMINH
|
|
2U, // LDUMINLB
|
|
2U, // LDUMINLH
|
|
2U, // LDUMINLW
|
|
2U, // LDUMINLX
|
|
2U, // LDUMINW
|
|
2U, // LDUMINX
|
|
2362456U, // LDURBBi
|
|
2362456U, // LDURBi
|
|
2362456U, // LDURDi
|
|
2362456U, // LDURHHi
|
|
2362456U, // LDURHi
|
|
2362456U, // LDURQi
|
|
2362456U, // LDURSBWi
|
|
2362456U, // LDURSBXi
|
|
2362456U, // LDURSHWi
|
|
2362456U, // LDURSHXi
|
|
2362456U, // LDURSWi
|
|
2362456U, // LDURSi
|
|
2362456U, // LDURWi
|
|
2362456U, // LDURXi
|
|
2362576U, // LDXPW
|
|
2362576U, // LDXPX
|
|
568U, // LDXRB
|
|
568U, // LDXRH
|
|
568U, // LDXRW
|
|
568U, // LDXRX
|
|
8530048U, // LSLR_ZPmZ_B
|
|
16914560U, // LSLR_ZPmZ_D
|
|
25832584U, // LSLR_ZPmZ_H
|
|
33697920U, // LSLR_ZPmZ_S
|
|
3160U, // LSLVWr
|
|
3160U, // LSLVXr
|
|
16918656U, // LSL_WIDE_ZPmZ_B
|
|
1584264U, // LSL_WIDE_ZPmZ_H
|
|
16920704U, // LSL_WIDE_ZPmZ_S
|
|
6232U, // LSL_WIDE_ZZZ_B
|
|
192U, // LSL_WIDE_ZZZ_H
|
|
6232U, // LSL_WIDE_ZZZ_S
|
|
141440U, // LSL_ZPmI_B
|
|
137344U, // LSL_ZPmI_D
|
|
1453192U, // LSL_ZPmI_H
|
|
143488U, // LSL_ZPmI_S
|
|
8530048U, // LSL_ZPmZ_B
|
|
16914560U, // LSL_ZPmZ_D
|
|
25832584U, // LSL_ZPmZ_H
|
|
33697920U, // LSL_ZPmZ_S
|
|
3160U, // LSL_ZZI_B
|
|
3160U, // LSL_ZZI_D
|
|
200U, // LSL_ZZI_H
|
|
3160U, // LSL_ZZI_S
|
|
8530048U, // LSRR_ZPmZ_B
|
|
16914560U, // LSRR_ZPmZ_D
|
|
25832584U, // LSRR_ZPmZ_H
|
|
33697920U, // LSRR_ZPmZ_S
|
|
3160U, // LSRVWr
|
|
3160U, // LSRVXr
|
|
16918656U, // LSR_WIDE_ZPmZ_B
|
|
1584264U, // LSR_WIDE_ZPmZ_H
|
|
16920704U, // LSR_WIDE_ZPmZ_S
|
|
6232U, // LSR_WIDE_ZZZ_B
|
|
192U, // LSR_WIDE_ZZZ_H
|
|
6232U, // LSR_WIDE_ZZZ_S
|
|
141440U, // LSR_ZPmI_B
|
|
137344U, // LSR_ZPmI_D
|
|
1453192U, // LSR_ZPmI_H
|
|
143488U, // LSR_ZPmI_S
|
|
8530048U, // LSR_ZPmZ_B
|
|
16914560U, // LSR_ZPmZ_D
|
|
25832584U, // LSR_ZPmZ_H
|
|
33697920U, // LSR_ZPmZ_S
|
|
3160U, // LSR_ZZI_B
|
|
3160U, // LSR_ZZI_D
|
|
200U, // LSR_ZZI_H
|
|
3160U, // LSR_ZZI_S
|
|
134232U, // MADDWrrr
|
|
134232U, // MADDXrrr
|
|
86144U, // MAD_ZPmZZ_B
|
|
134349952U, // MAD_ZPmZZ_D
|
|
28978456U, // MAD_ZPmZZ_H
|
|
142739584U, // MAD_ZPmZZ_S
|
|
8530104U, // MATCH_PPzZZ_B
|
|
25832585U, // MATCH_PPzZZ_H
|
|
86144U, // MLA_ZPmZZ_B
|
|
134349952U, // MLA_ZPmZZ_D
|
|
28978456U, // MLA_ZPmZZ_H
|
|
142739584U, // MLA_ZPmZZ_S
|
|
27133016U, // MLA_ZZZI_D
|
|
39192U, // MLA_ZZZI_H
|
|
27134040U, // MLA_ZZZI_S
|
|
795792U, // MLAv16i8
|
|
926872U, // MLAv2i32
|
|
54273176U, // MLAv2i32_indexed
|
|
1057952U, // MLAv4i16
|
|
52438176U, // MLAv4i16_indexed
|
|
402544U, // MLAv4i32
|
|
54273136U, // MLAv4i32_indexed
|
|
533624U, // MLAv8i16
|
|
52438136U, // MLAv8i16_indexed
|
|
1189032U, // MLAv8i8
|
|
86144U, // MLS_ZPmZZ_B
|
|
134349952U, // MLS_ZPmZZ_D
|
|
28978456U, // MLS_ZPmZZ_H
|
|
142739584U, // MLS_ZPmZZ_S
|
|
27133016U, // MLS_ZZZI_D
|
|
39192U, // MLS_ZZZI_H
|
|
27134040U, // MLS_ZZZI_S
|
|
795792U, // MLSv16i8
|
|
926872U, // MLSv2i32
|
|
54273176U, // MLSv2i32_indexed
|
|
1057952U, // MLSv4i16
|
|
52438176U, // MLSv4i16_indexed
|
|
402544U, // MLSv4i32
|
|
54273136U, // MLSv4i32_indexed
|
|
533624U, // MLSv8i16
|
|
52438136U, // MLSv8i16_indexed
|
|
1189032U, // MLSv8i8
|
|
0U, // MOPSSETGE
|
|
0U, // MOPSSETGEN
|
|
0U, // MOPSSETGET
|
|
0U, // MOPSSETGETN
|
|
2U, // MOVID
|
|
34U, // MOVIv16b_ns
|
|
2U, // MOVIv2d_ns
|
|
586U, // MOVIv2i32
|
|
586U, // MOVIv2s_msl
|
|
586U, // MOVIv4i16
|
|
586U, // MOVIv4i32
|
|
586U, // MOVIv4s_msl
|
|
34U, // MOVIv8b_ns
|
|
586U, // MOVIv8i16
|
|
1U, // MOVKWi
|
|
1U, // MOVKXi
|
|
586U, // MOVNWi
|
|
586U, // MOVNXi
|
|
0U, // MOVPRFX_ZPmZ_B
|
|
8U, // MOVPRFX_ZPmZ_D
|
|
0U, // MOVPRFX_ZPmZ_H
|
|
16U, // MOVPRFX_ZPmZ_S
|
|
10424U, // MOVPRFX_ZPzZ_B
|
|
6328U, // MOVPRFX_ZPzZ_D
|
|
137U, // MOVPRFX_ZPzZ_H
|
|
12472U, // MOVPRFX_ZPzZ_S
|
|
32U, // MOVPRFX_ZZ
|
|
586U, // MOVZWi
|
|
586U, // MOVZXi
|
|
2U, // MRS
|
|
86144U, // MSB_ZPmZZ_B
|
|
134349952U, // MSB_ZPmZZ_D
|
|
28978456U, // MSB_ZPmZZ_H
|
|
142739584U, // MSB_ZPmZZ_S
|
|
0U, // MSR
|
|
0U, // MSRpstateImm1
|
|
0U, // MSRpstateImm4
|
|
0U, // MSRpstatesvcrImm1
|
|
134232U, // MSUBWrrr
|
|
134232U, // MSUBXrrr
|
|
3160U, // MUL_ZI_B
|
|
3160U, // MUL_ZI_D
|
|
200U, // MUL_ZI_H
|
|
3160U, // MUL_ZI_S
|
|
8530048U, // MUL_ZPmZ_B
|
|
16914560U, // MUL_ZPmZ_D
|
|
25832584U, // MUL_ZPmZ_H
|
|
33697920U, // MUL_ZPmZ_S
|
|
4462680U, // MUL_ZZZI_D
|
|
49288U, // MUL_ZZZI_H
|
|
4468824U, // MUL_ZZZI_S
|
|
10328U, // MUL_ZZZ_B
|
|
6232U, // MUL_ZZZ_D
|
|
136U, // MUL_ZZZ_H
|
|
12376U, // MUL_ZZZ_S
|
|
794768U, // MULv16i8
|
|
925848U, // MULv2i32
|
|
163324056U, // MULv2i32_indexed
|
|
1056928U, // MULv4i16
|
|
161489056U, // MULv4i16_indexed
|
|
401520U, // MULv4i32
|
|
163324016U, // MULv4i32_indexed
|
|
532600U, // MULv8i16
|
|
161489016U, // MULv8i16_indexed
|
|
1188008U, // MULv8i8
|
|
586U, // MVNIv2i32
|
|
586U, // MVNIv2s_msl
|
|
586U, // MVNIv4i16
|
|
586U, // MVNIv4i32
|
|
586U, // MVNIv4s_msl
|
|
586U, // MVNIv8i16
|
|
8530104U, // NANDS_PPzPP
|
|
8530104U, // NAND_PPzPP
|
|
16914520U, // NBSL_ZZZZ
|
|
0U, // NEG_ZPmZ_B
|
|
8U, // NEG_ZPmZ_D
|
|
0U, // NEG_ZPmZ_H
|
|
16U, // NEG_ZPmZ_S
|
|
24U, // NEGv16i8
|
|
32U, // NEGv1i64
|
|
40U, // NEGv2i32
|
|
48U, // NEGv2i64
|
|
56U, // NEGv4i16
|
|
64U, // NEGv4i32
|
|
72U, // NEGv8i16
|
|
80U, // NEGv8i8
|
|
8530104U, // NMATCH_PPzZZ_B
|
|
25832585U, // NMATCH_PPzZZ_H
|
|
8530104U, // NORS_PPzPP
|
|
8530104U, // NOR_PPzPP
|
|
0U, // NOT_ZPmZ_B
|
|
8U, // NOT_ZPmZ_D
|
|
0U, // NOT_ZPmZ_H
|
|
16U, // NOT_ZPmZ_S
|
|
24U, // NOTv16i8
|
|
80U, // NOTv8i8
|
|
8530104U, // ORNS_PPzPP
|
|
14424U, // ORNWrs
|
|
14424U, // ORNXrs
|
|
8530104U, // ORN_PPzPP
|
|
794768U, // ORNv16i8
|
|
1188008U, // ORNv8i8
|
|
8530104U, // ORRS_PPzPP
|
|
35928U, // ORRWri
|
|
14424U, // ORRWrs
|
|
36952U, // ORRXri
|
|
14424U, // ORRXrs
|
|
8530104U, // ORR_PPzPP
|
|
36952U, // ORR_ZI
|
|
8530048U, // ORR_ZPmZ_B
|
|
16914560U, // ORR_ZPmZ_D
|
|
25832584U, // ORR_ZPmZ_H
|
|
33697920U, // ORR_ZPmZ_S
|
|
6232U, // ORR_ZZZ
|
|
794768U, // ORRv16i8
|
|
1U, // ORRv2i32
|
|
1U, // ORRv4i16
|
|
1U, // ORRv4i32
|
|
1U, // ORRv8i16
|
|
1188008U, // ORRv8i8
|
|
0U, // ORV_VPZ_B
|
|
0U, // ORV_VPZ_D
|
|
0U, // ORV_VPZ_H
|
|
0U, // ORV_VPZ_S
|
|
33U, // PACDA
|
|
33U, // PACDB
|
|
0U, // PACDZA
|
|
0U, // PACDZB
|
|
3160U, // PACGA
|
|
33U, // PACIA
|
|
0U, // PACIA1716
|
|
0U, // PACIASP
|
|
0U, // PACIAZ
|
|
33U, // PACIB
|
|
0U, // PACIB1716
|
|
0U, // PACIBSP
|
|
0U, // PACIBZ
|
|
0U, // PACIZA
|
|
0U, // PACIZB
|
|
0U, // PFALSE
|
|
10328U, // PFIRST_B
|
|
12376U, // PMULLB_ZZZ_D
|
|
592U, // PMULLB_ZZZ_H
|
|
0U, // PMULLB_ZZZ_Q
|
|
12376U, // PMULLT_ZZZ_D
|
|
592U, // PMULLT_ZZZ_H
|
|
0U, // PMULLT_ZZZ_Q
|
|
794768U, // PMULLv16i8
|
|
3U, // PMULLv1i64
|
|
3U, // PMULLv2i64
|
|
1188008U, // PMULLv8i8
|
|
10328U, // PMUL_ZZZ_B
|
|
794768U, // PMULv16i8
|
|
1188008U, // PMULv8i8
|
|
10328U, // PNEXT_B
|
|
6232U, // PNEXT_D
|
|
136U, // PNEXT_H
|
|
12376U, // PNEXT_S
|
|
87360U, // PRFB_D_PZI
|
|
600U, // PRFB_D_SCALED
|
|
608U, // PRFB_D_SXTW_SCALED
|
|
616U, // PRFB_D_UXTW_SCALED
|
|
88384U, // PRFB_PRI
|
|
624U, // PRFB_PRR
|
|
87360U, // PRFB_S_PZI
|
|
632U, // PRFB_S_SXTW_SCALED
|
|
640U, // PRFB_S_UXTW_SCALED
|
|
648U, // PRFD_D_PZI
|
|
656U, // PRFD_D_SCALED
|
|
664U, // PRFD_D_SXTW_SCALED
|
|
672U, // PRFD_D_UXTW_SCALED
|
|
88384U, // PRFD_PRI
|
|
680U, // PRFD_PRR
|
|
648U, // PRFD_S_PZI
|
|
688U, // PRFD_S_SXTW_SCALED
|
|
696U, // PRFD_S_UXTW_SCALED
|
|
704U, // PRFH_D_PZI
|
|
712U, // PRFH_D_SCALED
|
|
720U, // PRFH_D_SXTW_SCALED
|
|
728U, // PRFH_D_UXTW_SCALED
|
|
88384U, // PRFH_PRI
|
|
736U, // PRFH_PRR
|
|
704U, // PRFH_S_PZI
|
|
744U, // PRFH_S_SXTW_SCALED
|
|
752U, // PRFH_S_UXTW_SCALED
|
|
1U, // PRFMl
|
|
243403864U, // PRFMroW
|
|
251792472U, // PRFMroX
|
|
82008U, // PRFMui
|
|
760U, // PRFS_PRR
|
|
2362456U, // PRFUMi
|
|
768U, // PRFW_D_PZI
|
|
776U, // PRFW_D_SCALED
|
|
784U, // PRFW_D_SXTW_SCALED
|
|
792U, // PRFW_D_UXTW_SCALED
|
|
88384U, // PRFW_PRI
|
|
768U, // PRFW_S_PZI
|
|
800U, // PRFW_S_SXTW_SCALED
|
|
808U, // PRFW_S_UXTW_SCALED
|
|
4991064U, // PSEL_PPPRI_B
|
|
4986968U, // PSEL_PPPRI_D
|
|
4985944U, // PSEL_PPPRI_H
|
|
4993112U, // PSEL_PPPRI_S
|
|
32U, // PTEST_PP
|
|
33U, // PTRUES_B
|
|
33U, // PTRUES_D
|
|
0U, // PTRUES_H
|
|
33U, // PTRUES_S
|
|
33U, // PTRUE_B
|
|
33U, // PTRUE_D
|
|
0U, // PTRUE_H
|
|
33U, // PTRUE_S
|
|
0U, // PUNPKHI_PP
|
|
0U, // PUNPKLO_PP
|
|
5208U, // RADDHNB_ZZZ_B
|
|
96U, // RADDHNB_ZZZ_H
|
|
6232U, // RADDHNB_ZZZ_S
|
|
7256U, // RADDHNT_ZZZ_B
|
|
16U, // RADDHNT_ZZZ_H
|
|
1112U, // RADDHNT_ZZZ_S
|
|
270440U, // RADDHNv2i64_v2i32
|
|
271464U, // RADDHNv2i64_v4i32
|
|
401520U, // RADDHNv4i32_v4i16
|
|
402544U, // RADDHNv4i32_v8i16
|
|
533624U, // RADDHNv8i16_v16i8
|
|
532600U, // RADDHNv8i16_v8i8
|
|
270440U, // RAX1
|
|
6232U, // RAX1_ZZZ_D
|
|
32U, // RBITWr
|
|
32U, // RBITXr
|
|
0U, // RBIT_ZPmZ_B
|
|
8U, // RBIT_ZPmZ_D
|
|
0U, // RBIT_ZPmZ_H
|
|
16U, // RBIT_ZPmZ_S
|
|
24U, // RBITv16i8
|
|
80U, // RBITv8i8
|
|
816U, // RDFFRS_PPz
|
|
816U, // RDFFR_PPz_REAL
|
|
0U, // RDFFR_P_REAL
|
|
32U, // RDVLI_XI
|
|
0U, // RET
|
|
0U, // RETAA
|
|
0U, // RETAB
|
|
32U, // REV16Wr
|
|
32U, // REV16Xr
|
|
24U, // REV16v16i8
|
|
80U, // REV16v8i8
|
|
32U, // REV32Xr
|
|
24U, // REV32v16i8
|
|
56U, // REV32v4i16
|
|
72U, // REV32v8i16
|
|
80U, // REV32v8i8
|
|
24U, // REV64v16i8
|
|
40U, // REV64v2i32
|
|
56U, // REV64v4i16
|
|
64U, // REV64v4i32
|
|
72U, // REV64v8i16
|
|
80U, // REV64v8i8
|
|
8U, // REVB_ZPmZ_D
|
|
0U, // REVB_ZPmZ_H
|
|
16U, // REVB_ZPmZ_S
|
|
3U, // REVD_ZPmZ
|
|
8U, // REVH_ZPmZ_D
|
|
16U, // REVH_ZPmZ_S
|
|
8U, // REVW_ZPmZ_D
|
|
32U, // REVWr
|
|
32U, // REVXr
|
|
32U, // REV_PP_B
|
|
32U, // REV_PP_D
|
|
0U, // REV_PP_H
|
|
32U, // REV_PP_S
|
|
32U, // REV_ZZ_B
|
|
32U, // REV_ZZ_D
|
|
0U, // REV_ZZ_H
|
|
32U, // REV_ZZ_S
|
|
3160U, // RMIF
|
|
3160U, // RORVWr
|
|
3160U, // RORVXr
|
|
3160U, // RSHRNB_ZZI_B
|
|
200U, // RSHRNB_ZZI_H
|
|
3160U, // RSHRNB_ZZI_S
|
|
37976U, // RSHRNT_ZZI_B
|
|
320U, // RSHRNT_ZZI_H
|
|
37976U, // RSHRNT_ZZI_S
|
|
38008U, // RSHRNv16i8_shift
|
|
3176U, // RSHRNv2i32_shift
|
|
3184U, // RSHRNv4i16_shift
|
|
37992U, // RSHRNv4i32_shift
|
|
38000U, // RSHRNv8i16_shift
|
|
3192U, // RSHRNv8i8_shift
|
|
5208U, // RSUBHNB_ZZZ_B
|
|
96U, // RSUBHNB_ZZZ_H
|
|
6232U, // RSUBHNB_ZZZ_S
|
|
7256U, // RSUBHNT_ZZZ_B
|
|
16U, // RSUBHNT_ZZZ_H
|
|
1112U, // RSUBHNT_ZZZ_S
|
|
270440U, // RSUBHNv2i64_v2i32
|
|
271464U, // RSUBHNv2i64_v4i32
|
|
401520U, // RSUBHNv4i32_v4i16
|
|
402544U, // RSUBHNv4i32_v8i16
|
|
533624U, // RSUBHNv8i16_v16i8
|
|
532600U, // RSUBHNv8i16_v8i8
|
|
2136U, // SABALB_ZZZ_D
|
|
0U, // SABALB_ZZZ_H
|
|
7256U, // SABALB_ZZZ_S
|
|
2136U, // SABALT_ZZZ_D
|
|
0U, // SABALT_ZZZ_H
|
|
7256U, // SABALT_ZZZ_S
|
|
795792U, // SABALv16i8_v8i16
|
|
926872U, // SABALv2i32_v2i64
|
|
1057952U, // SABALv4i16_v4i32
|
|
402544U, // SABALv4i32_v2i64
|
|
533624U, // SABALv8i16_v4i32
|
|
1189032U, // SABALv8i8_v8i16
|
|
1U, // SABA_ZZZ_B
|
|
1112U, // SABA_ZZZ_D
|
|
280U, // SABA_ZZZ_H
|
|
2136U, // SABA_ZZZ_S
|
|
795792U, // SABAv16i8
|
|
926872U, // SABAv2i32
|
|
1057952U, // SABAv4i16
|
|
402544U, // SABAv4i32
|
|
533624U, // SABAv8i16
|
|
1189032U, // SABAv8i8
|
|
12376U, // SABDLB_ZZZ_D
|
|
592U, // SABDLB_ZZZ_H
|
|
5208U, // SABDLB_ZZZ_S
|
|
12376U, // SABDLT_ZZZ_D
|
|
592U, // SABDLT_ZZZ_H
|
|
5208U, // SABDLT_ZZZ_S
|
|
794768U, // SABDLv16i8_v8i16
|
|
925848U, // SABDLv2i32_v2i64
|
|
1056928U, // SABDLv4i16_v4i32
|
|
401520U, // SABDLv4i32_v2i64
|
|
532600U, // SABDLv8i16_v4i32
|
|
1188008U, // SABDLv8i8_v8i16
|
|
8530048U, // SABD_ZPmZ_B
|
|
16914560U, // SABD_ZPmZ_D
|
|
25832584U, // SABD_ZPmZ_H
|
|
33697920U, // SABD_ZPmZ_S
|
|
794768U, // SABDv16i8
|
|
925848U, // SABDv2i32
|
|
1056928U, // SABDv4i16
|
|
401520U, // SABDv4i32
|
|
532600U, // SABDv8i16
|
|
1188008U, // SABDv8i8
|
|
2176U, // SADALP_ZPmZ_D
|
|
0U, // SADALP_ZPmZ_H
|
|
7296U, // SADALP_ZPmZ_S
|
|
24U, // SADALPv16i8_v8i16
|
|
40U, // SADALPv2i32_v1i64
|
|
56U, // SADALPv4i16_v2i32
|
|
64U, // SADALPv4i32_v2i64
|
|
72U, // SADALPv8i16_v4i32
|
|
80U, // SADALPv8i8_v4i16
|
|
12376U, // SADDLBT_ZZZ_D
|
|
592U, // SADDLBT_ZZZ_H
|
|
5208U, // SADDLBT_ZZZ_S
|
|
12376U, // SADDLB_ZZZ_D
|
|
592U, // SADDLB_ZZZ_H
|
|
5208U, // SADDLB_ZZZ_S
|
|
24U, // SADDLPv16i8_v8i16
|
|
40U, // SADDLPv2i32_v1i64
|
|
56U, // SADDLPv4i16_v2i32
|
|
64U, // SADDLPv4i32_v2i64
|
|
72U, // SADDLPv8i16_v4i32
|
|
80U, // SADDLPv8i8_v4i16
|
|
12376U, // SADDLT_ZZZ_D
|
|
592U, // SADDLT_ZZZ_H
|
|
5208U, // SADDLT_ZZZ_S
|
|
24U, // SADDLVv16i8v
|
|
56U, // SADDLVv4i16v
|
|
64U, // SADDLVv4i32v
|
|
72U, // SADDLVv8i16v
|
|
80U, // SADDLVv8i8v
|
|
794768U, // SADDLv16i8_v8i16
|
|
925848U, // SADDLv2i32_v2i64
|
|
1056928U, // SADDLv4i16_v4i32
|
|
401520U, // SADDLv4i32_v2i64
|
|
532600U, // SADDLv8i16_v4i32
|
|
1188008U, // SADDLv8i8_v8i16
|
|
0U, // SADDV_VPZ_B
|
|
0U, // SADDV_VPZ_H
|
|
0U, // SADDV_VPZ_S
|
|
12376U, // SADDWB_ZZZ_D
|
|
592U, // SADDWB_ZZZ_H
|
|
5208U, // SADDWB_ZZZ_S
|
|
12376U, // SADDWT_ZZZ_D
|
|
592U, // SADDWT_ZZZ_H
|
|
5208U, // SADDWT_ZZZ_S
|
|
794744U, // SADDWv16i8_v8i16
|
|
925800U, // SADDWv2i32_v2i64
|
|
1056880U, // SADDWv4i16_v4i32
|
|
401512U, // SADDWv4i32_v2i64
|
|
532592U, // SADDWv8i16_v4i32
|
|
1187960U, // SADDWv8i8_v8i16
|
|
0U, // SB
|
|
1112U, // SBCLB_ZZZ_D
|
|
2136U, // SBCLB_ZZZ_S
|
|
1112U, // SBCLT_ZZZ_D
|
|
2136U, // SBCLT_ZZZ_S
|
|
3160U, // SBCSWr
|
|
3160U, // SBCSXr
|
|
3160U, // SBCWr
|
|
3160U, // SBCXr
|
|
134232U, // SBFMWri
|
|
134232U, // SBFMXri
|
|
10328U, // SCLAMP_ZZZ_B
|
|
6232U, // SCLAMP_ZZZ_D
|
|
136U, // SCLAMP_ZZZ_H
|
|
12376U, // SCLAMP_ZZZ_S
|
|
3160U, // SCVTFSWDri
|
|
3160U, // SCVTFSWHri
|
|
3160U, // SCVTFSWSri
|
|
3160U, // SCVTFSXDri
|
|
3160U, // SCVTFSXHri
|
|
3160U, // SCVTFSXSri
|
|
32U, // SCVTFUWDri
|
|
32U, // SCVTFUWHri
|
|
32U, // SCVTFUWSri
|
|
32U, // SCVTFUXDri
|
|
32U, // SCVTFUXHri
|
|
32U, // SCVTFUXSri
|
|
8U, // SCVTF_ZPmZ_DtoD
|
|
2U, // SCVTF_ZPmZ_DtoH
|
|
8U, // SCVTF_ZPmZ_DtoS
|
|
0U, // SCVTF_ZPmZ_HtoH
|
|
16U, // SCVTF_ZPmZ_StoD
|
|
1U, // SCVTF_ZPmZ_StoH
|
|
16U, // SCVTF_ZPmZ_StoS
|
|
3160U, // SCVTFd
|
|
3160U, // SCVTFh
|
|
3160U, // SCVTFs
|
|
32U, // SCVTFv1i16
|
|
32U, // SCVTFv1i32
|
|
32U, // SCVTFv1i64
|
|
40U, // SCVTFv2f32
|
|
48U, // SCVTFv2f64
|
|
3224U, // SCVTFv2i32_shift
|
|
3176U, // SCVTFv2i64_shift
|
|
56U, // SCVTFv4f16
|
|
64U, // SCVTFv4f32
|
|
3232U, // SCVTFv4i16_shift
|
|
3184U, // SCVTFv4i32_shift
|
|
72U, // SCVTFv8f16
|
|
3192U, // SCVTFv8i16_shift
|
|
16914560U, // SDIVR_ZPmZ_D
|
|
33697920U, // SDIVR_ZPmZ_S
|
|
3160U, // SDIVWr
|
|
3160U, // SDIVXr
|
|
16914560U, // SDIV_ZPmZ_D
|
|
33697920U, // SDIV_ZPmZ_S
|
|
27139160U, // SDOT_ZZZI_D
|
|
38913U, // SDOT_ZZZI_S
|
|
7256U, // SDOT_ZZZ_D
|
|
1U, // SDOT_ZZZ_S
|
|
5121168U, // SDOTlanev16i8
|
|
5121192U, // SDOTlanev8i8
|
|
795792U, // SDOTv16i8
|
|
1189032U, // SDOTv8i8
|
|
8530008U, // SEL_PPPP
|
|
8530008U, // SEL_ZPZZ_B
|
|
16914520U, // SEL_ZPZZ_D
|
|
25832584U, // SEL_ZPZZ_H
|
|
33697880U, // SEL_ZPZZ_S
|
|
0U, // SETE
|
|
0U, // SETEN
|
|
0U, // SETET
|
|
0U, // SETETN
|
|
0U, // SETF16
|
|
0U, // SETF8
|
|
0U, // SETFFR
|
|
0U, // SETGM
|
|
0U, // SETGMN
|
|
0U, // SETGMT
|
|
0U, // SETGMTN
|
|
0U, // SETGP
|
|
0U, // SETGPN
|
|
0U, // SETGPT
|
|
0U, // SETGPTN
|
|
0U, // SETM
|
|
0U, // SETMN
|
|
0U, // SETMT
|
|
0U, // SETMTN
|
|
0U, // SETP
|
|
0U, // SETPN
|
|
0U, // SETPT
|
|
0U, // SETPTN
|
|
402521U, // SHA1Crrr
|
|
32U, // SHA1Hrr
|
|
402521U, // SHA1Mrrr
|
|
402521U, // SHA1Prrr
|
|
402544U, // SHA1SU0rrr
|
|
64U, // SHA1SU1rr
|
|
402521U, // SHA256H2rrr
|
|
402521U, // SHA256Hrrr
|
|
64U, // SHA256SU0rr
|
|
402544U, // SHA256SU1rrr
|
|
271449U, // SHA512H
|
|
271449U, // SHA512H2
|
|
48U, // SHA512SU0
|
|
271464U, // SHA512SU1
|
|
8530048U, // SHADD_ZPmZ_B
|
|
16914560U, // SHADD_ZPmZ_D
|
|
25832584U, // SHADD_ZPmZ_H
|
|
33697920U, // SHADD_ZPmZ_S
|
|
794768U, // SHADDv16i8
|
|
925848U, // SHADDv2i32
|
|
1056928U, // SHADDv4i16
|
|
401520U, // SHADDv4i32
|
|
532600U, // SHADDv8i16
|
|
1188008U, // SHADDv8i8
|
|
824U, // SHLLv16i8
|
|
832U, // SHLLv2i32
|
|
840U, // SHLLv4i16
|
|
848U, // SHLLv4i32
|
|
856U, // SHLLv8i16
|
|
864U, // SHLLv8i8
|
|
3160U, // SHLd
|
|
3216U, // SHLv16i8_shift
|
|
3224U, // SHLv2i32_shift
|
|
3176U, // SHLv2i64_shift
|
|
3232U, // SHLv4i16_shift
|
|
3184U, // SHLv4i32_shift
|
|
3192U, // SHLv8i16_shift
|
|
3240U, // SHLv8i8_shift
|
|
3160U, // SHRNB_ZZI_B
|
|
200U, // SHRNB_ZZI_H
|
|
3160U, // SHRNB_ZZI_S
|
|
37976U, // SHRNT_ZZI_B
|
|
320U, // SHRNT_ZZI_H
|
|
37976U, // SHRNT_ZZI_S
|
|
38008U, // SHRNv16i8_shift
|
|
3176U, // SHRNv2i32_shift
|
|
3184U, // SHRNv4i16_shift
|
|
37992U, // SHRNv4i32_shift
|
|
38000U, // SHRNv8i16_shift
|
|
3192U, // SHRNv8i8_shift
|
|
8530048U, // SHSUBR_ZPmZ_B
|
|
16914560U, // SHSUBR_ZPmZ_D
|
|
25832584U, // SHSUBR_ZPmZ_H
|
|
33697920U, // SHSUBR_ZPmZ_S
|
|
8530048U, // SHSUB_ZPmZ_B
|
|
16914560U, // SHSUB_ZPmZ_D
|
|
25832584U, // SHSUB_ZPmZ_H
|
|
33697920U, // SHSUB_ZPmZ_S
|
|
794768U, // SHSUBv16i8
|
|
925848U, // SHSUBv2i32
|
|
1056928U, // SHSUBv4i16
|
|
401520U, // SHSUBv4i32
|
|
532600U, // SHSUBv8i16
|
|
1188008U, // SHSUBv8i8
|
|
321U, // SLI_ZZI_B
|
|
37976U, // SLI_ZZI_D
|
|
320U, // SLI_ZZI_H
|
|
37976U, // SLI_ZZI_S
|
|
37977U, // SLId
|
|
38032U, // SLIv16i8_shift
|
|
38040U, // SLIv2i32_shift
|
|
37992U, // SLIv2i64_shift
|
|
38048U, // SLIv4i16_shift
|
|
38000U, // SLIv4i32_shift
|
|
38008U, // SLIv8i16_shift
|
|
38056U, // SLIv8i8_shift
|
|
402544U, // SM3PARTW1
|
|
402544U, // SM3PARTW2
|
|
3266584688U, // SM3SS1
|
|
54273136U, // SM3TT1A
|
|
54273136U, // SM3TT1B
|
|
54273136U, // SM3TT2A
|
|
54273136U, // SM3TT2B
|
|
64U, // SM4E
|
|
12376U, // SM4EKEY_ZZZ_S
|
|
401520U, // SM4ENCKEY
|
|
12376U, // SM4E_ZZZ_S
|
|
134232U, // SMADDLrrr
|
|
8530048U, // SMAXP_ZPmZ_B
|
|
16914560U, // SMAXP_ZPmZ_D
|
|
25832584U, // SMAXP_ZPmZ_H
|
|
33697920U, // SMAXP_ZPmZ_S
|
|
794768U, // SMAXPv16i8
|
|
925848U, // SMAXPv2i32
|
|
1056928U, // SMAXPv4i16
|
|
401520U, // SMAXPv4i32
|
|
532600U, // SMAXPv8i16
|
|
1188008U, // SMAXPv8i8
|
|
0U, // SMAXV_VPZ_B
|
|
0U, // SMAXV_VPZ_D
|
|
0U, // SMAXV_VPZ_H
|
|
0U, // SMAXV_VPZ_S
|
|
24U, // SMAXVv16i8v
|
|
56U, // SMAXVv4i16v
|
|
64U, // SMAXVv4i32v
|
|
72U, // SMAXVv8i16v
|
|
80U, // SMAXVv8i8v
|
|
3160U, // SMAX_ZI_B
|
|
3160U, // SMAX_ZI_D
|
|
200U, // SMAX_ZI_H
|
|
3160U, // SMAX_ZI_S
|
|
8530048U, // SMAX_ZPmZ_B
|
|
16914560U, // SMAX_ZPmZ_D
|
|
25832584U, // SMAX_ZPmZ_H
|
|
33697920U, // SMAX_ZPmZ_S
|
|
794768U, // SMAXv16i8
|
|
925848U, // SMAXv2i32
|
|
1056928U, // SMAXv4i16
|
|
401520U, // SMAXv4i32
|
|
532600U, // SMAXv8i16
|
|
1188008U, // SMAXv8i8
|
|
0U, // SMC
|
|
8530048U, // SMINP_ZPmZ_B
|
|
16914560U, // SMINP_ZPmZ_D
|
|
25832584U, // SMINP_ZPmZ_H
|
|
33697920U, // SMINP_ZPmZ_S
|
|
794768U, // SMINPv16i8
|
|
925848U, // SMINPv2i32
|
|
1056928U, // SMINPv4i16
|
|
401520U, // SMINPv4i32
|
|
532600U, // SMINPv8i16
|
|
1188008U, // SMINPv8i8
|
|
0U, // SMINV_VPZ_B
|
|
0U, // SMINV_VPZ_D
|
|
0U, // SMINV_VPZ_H
|
|
0U, // SMINV_VPZ_S
|
|
24U, // SMINVv16i8v
|
|
56U, // SMINVv4i16v
|
|
64U, // SMINVv4i32v
|
|
72U, // SMINVv8i16v
|
|
80U, // SMINVv8i8v
|
|
3160U, // SMIN_ZI_B
|
|
3160U, // SMIN_ZI_D
|
|
200U, // SMIN_ZI_H
|
|
3160U, // SMIN_ZI_S
|
|
8530048U, // SMIN_ZPmZ_B
|
|
16914560U, // SMIN_ZPmZ_D
|
|
25832584U, // SMIN_ZPmZ_H
|
|
33697920U, // SMIN_ZPmZ_S
|
|
794768U, // SMINv16i8
|
|
925848U, // SMINv2i32
|
|
1056928U, // SMINv4i16
|
|
401520U, // SMINv4i32
|
|
532600U, // SMINv8i16
|
|
1188008U, // SMINv8i8
|
|
27134040U, // SMLALB_ZZZI_D
|
|
27139160U, // SMLALB_ZZZI_S
|
|
2136U, // SMLALB_ZZZ_D
|
|
0U, // SMLALB_ZZZ_H
|
|
7256U, // SMLALB_ZZZ_S
|
|
27134040U, // SMLALT_ZZZI_D
|
|
27139160U, // SMLALT_ZZZI_S
|
|
2136U, // SMLALT_ZZZ_D
|
|
0U, // SMLALT_ZZZ_H
|
|
7256U, // SMLALT_ZZZ_S
|
|
795792U, // SMLALv16i8_v8i16
|
|
54273176U, // SMLALv2i32_indexed
|
|
926872U, // SMLALv2i32_v2i64
|
|
52438176U, // SMLALv4i16_indexed
|
|
1057952U, // SMLALv4i16_v4i32
|
|
54273136U, // SMLALv4i32_indexed
|
|
402544U, // SMLALv4i32_v2i64
|
|
52438136U, // SMLALv8i16_indexed
|
|
533624U, // SMLALv8i16_v4i32
|
|
1189032U, // SMLALv8i8_v8i16
|
|
27134040U, // SMLSLB_ZZZI_D
|
|
27139160U, // SMLSLB_ZZZI_S
|
|
2136U, // SMLSLB_ZZZ_D
|
|
0U, // SMLSLB_ZZZ_H
|
|
7256U, // SMLSLB_ZZZ_S
|
|
27134040U, // SMLSLT_ZZZI_D
|
|
27139160U, // SMLSLT_ZZZI_S
|
|
2136U, // SMLSLT_ZZZ_D
|
|
0U, // SMLSLT_ZZZ_H
|
|
7256U, // SMLSLT_ZZZ_S
|
|
795792U, // SMLSLv16i8_v8i16
|
|
54273176U, // SMLSLv2i32_indexed
|
|
926872U, // SMLSLv2i32_v2i64
|
|
52438176U, // SMLSLv4i16_indexed
|
|
1057952U, // SMLSLv4i16_v4i32
|
|
54273136U, // SMLSLv4i32_indexed
|
|
402544U, // SMLSLv4i32_v2i64
|
|
52438136U, // SMLSLv8i16_indexed
|
|
533624U, // SMLSLv8i16_v4i32
|
|
1189032U, // SMLSLv8i8_v8i16
|
|
795792U, // SMMLA
|
|
1U, // SMMLA_ZZZ
|
|
0U, // SMOPA_MPPZZ_D
|
|
0U, // SMOPA_MPPZZ_S
|
|
0U, // SMOPS_MPPZZ_D
|
|
0U, // SMOPS_MPPZZ_S
|
|
43352U, // SMOVvi16to32
|
|
43352U, // SMOVvi16to32_idx0
|
|
43352U, // SMOVvi16to64
|
|
43352U, // SMOVvi16to64_idx0
|
|
43360U, // SMOVvi32to64
|
|
43360U, // SMOVvi32to64_idx0
|
|
43376U, // SMOVvi8to32
|
|
43376U, // SMOVvi8to32_idx0
|
|
43376U, // SMOVvi8to64
|
|
43376U, // SMOVvi8to64_idx0
|
|
134232U, // SMSUBLrrr
|
|
8530048U, // SMULH_ZPmZ_B
|
|
16914560U, // SMULH_ZPmZ_D
|
|
25832584U, // SMULH_ZPmZ_H
|
|
33697920U, // SMULH_ZPmZ_S
|
|
10328U, // SMULH_ZZZ_B
|
|
6232U, // SMULH_ZZZ_D
|
|
136U, // SMULH_ZZZ_H
|
|
12376U, // SMULH_ZZZ_S
|
|
3160U, // SMULHrr
|
|
4468824U, // SMULLB_ZZZI_D
|
|
4461656U, // SMULLB_ZZZI_S
|
|
12376U, // SMULLB_ZZZ_D
|
|
592U, // SMULLB_ZZZ_H
|
|
5208U, // SMULLB_ZZZ_S
|
|
4468824U, // SMULLT_ZZZI_D
|
|
4461656U, // SMULLT_ZZZI_S
|
|
12376U, // SMULLT_ZZZ_D
|
|
592U, // SMULLT_ZZZ_H
|
|
5208U, // SMULLT_ZZZ_S
|
|
794768U, // SMULLv16i8_v8i16
|
|
163324056U, // SMULLv2i32_indexed
|
|
925848U, // SMULLv2i32_v2i64
|
|
161489056U, // SMULLv4i16_indexed
|
|
1056928U, // SMULLv4i16_v4i32
|
|
163324016U, // SMULLv4i32_indexed
|
|
401520U, // SMULLv4i32_v2i64
|
|
161489016U, // SMULLv8i16_indexed
|
|
532600U, // SMULLv8i16_v4i32
|
|
1188008U, // SMULLv8i8_v8i16
|
|
89176U, // SPLICE_ZPZZ_B
|
|
90200U, // SPLICE_ZPZZ_D
|
|
872U, // SPLICE_ZPZZ_H
|
|
91224U, // SPLICE_ZPZZ_S
|
|
8530008U, // SPLICE_ZPZ_B
|
|
16914520U, // SPLICE_ZPZ_D
|
|
25832584U, // SPLICE_ZPZ_H
|
|
33697880U, // SPLICE_ZPZ_S
|
|
0U, // SQABS_ZPmZ_B
|
|
8U, // SQABS_ZPmZ_D
|
|
0U, // SQABS_ZPmZ_H
|
|
16U, // SQABS_ZPmZ_S
|
|
24U, // SQABSv16i8
|
|
32U, // SQABSv1i16
|
|
32U, // SQABSv1i32
|
|
32U, // SQABSv1i64
|
|
32U, // SQABSv1i8
|
|
40U, // SQABSv2i32
|
|
48U, // SQABSv2i64
|
|
56U, // SQABSv4i16
|
|
64U, // SQABSv4i32
|
|
72U, // SQABSv8i16
|
|
80U, // SQABSv8i8
|
|
16472U, // SQADD_ZI_B
|
|
17496U, // SQADD_ZI_D
|
|
176U, // SQADD_ZI_H
|
|
18520U, // SQADD_ZI_S
|
|
8530048U, // SQADD_ZPmZ_B
|
|
16914560U, // SQADD_ZPmZ_D
|
|
25832584U, // SQADD_ZPmZ_H
|
|
33697920U, // SQADD_ZPmZ_S
|
|
10328U, // SQADD_ZZZ_B
|
|
6232U, // SQADD_ZZZ_D
|
|
136U, // SQADD_ZZZ_H
|
|
12376U, // SQADD_ZZZ_S
|
|
794768U, // SQADDv16i8
|
|
3160U, // SQADDv1i16
|
|
3160U, // SQADDv1i32
|
|
3160U, // SQADDv1i64
|
|
3160U, // SQADDv1i8
|
|
925848U, // SQADDv2i32
|
|
270440U, // SQADDv2i64
|
|
1056928U, // SQADDv4i16
|
|
401520U, // SQADDv4i32
|
|
532600U, // SQADDv8i16
|
|
1188008U, // SQADDv8i8
|
|
67250264U, // SQCADD_ZZI_B
|
|
67246168U, // SQCADD_ZZI_D
|
|
2239624U, // SQCADD_ZZI_H
|
|
67252312U, // SQCADD_ZZI_S
|
|
1U, // SQDECB_XPiI
|
|
3U, // SQDECB_XPiWdI
|
|
1U, // SQDECD_XPiI
|
|
3U, // SQDECD_XPiWdI
|
|
1U, // SQDECD_ZPiI
|
|
1U, // SQDECH_XPiI
|
|
3U, // SQDECH_XPiWdI
|
|
0U, // SQDECH_ZPiI
|
|
92248U, // SQDECP_XPWd_B
|
|
92248U, // SQDECP_XPWd_D
|
|
92248U, // SQDECP_XPWd_H
|
|
92248U, // SQDECP_XPWd_S
|
|
32U, // SQDECP_XP_B
|
|
32U, // SQDECP_XP_D
|
|
32U, // SQDECP_XP_H
|
|
32U, // SQDECP_XP_S
|
|
32U, // SQDECP_ZP_D
|
|
0U, // SQDECP_ZP_H
|
|
32U, // SQDECP_ZP_S
|
|
1U, // SQDECW_XPiI
|
|
3U, // SQDECW_XPiWdI
|
|
1U, // SQDECW_ZPiI
|
|
2136U, // SQDMLALBT_ZZZ_D
|
|
0U, // SQDMLALBT_ZZZ_H
|
|
7256U, // SQDMLALBT_ZZZ_S
|
|
27134040U, // SQDMLALB_ZZZI_D
|
|
27139160U, // SQDMLALB_ZZZI_S
|
|
2136U, // SQDMLALB_ZZZ_D
|
|
0U, // SQDMLALB_ZZZ_H
|
|
7256U, // SQDMLALB_ZZZ_S
|
|
27134040U, // SQDMLALT_ZZZI_D
|
|
27139160U, // SQDMLALT_ZZZI_S
|
|
2136U, // SQDMLALT_ZZZ_D
|
|
0U, // SQDMLALT_ZZZ_H
|
|
7256U, // SQDMLALT_ZZZ_S
|
|
37977U, // SQDMLALi16
|
|
37977U, // SQDMLALi32
|
|
52438105U, // SQDMLALv1i32_indexed
|
|
54273113U, // SQDMLALv1i64_indexed
|
|
54273176U, // SQDMLALv2i32_indexed
|
|
926872U, // SQDMLALv2i32_v2i64
|
|
52438176U, // SQDMLALv4i16_indexed
|
|
1057952U, // SQDMLALv4i16_v4i32
|
|
54273136U, // SQDMLALv4i32_indexed
|
|
402544U, // SQDMLALv4i32_v2i64
|
|
52438136U, // SQDMLALv8i16_indexed
|
|
533624U, // SQDMLALv8i16_v4i32
|
|
2136U, // SQDMLSLBT_ZZZ_D
|
|
0U, // SQDMLSLBT_ZZZ_H
|
|
7256U, // SQDMLSLBT_ZZZ_S
|
|
27134040U, // SQDMLSLB_ZZZI_D
|
|
27139160U, // SQDMLSLB_ZZZI_S
|
|
2136U, // SQDMLSLB_ZZZ_D
|
|
0U, // SQDMLSLB_ZZZ_H
|
|
7256U, // SQDMLSLB_ZZZ_S
|
|
27134040U, // SQDMLSLT_ZZZI_D
|
|
27139160U, // SQDMLSLT_ZZZI_S
|
|
2136U, // SQDMLSLT_ZZZ_D
|
|
0U, // SQDMLSLT_ZZZ_H
|
|
7256U, // SQDMLSLT_ZZZ_S
|
|
37977U, // SQDMLSLi16
|
|
37977U, // SQDMLSLi32
|
|
52438105U, // SQDMLSLv1i32_indexed
|
|
54273113U, // SQDMLSLv1i64_indexed
|
|
54273176U, // SQDMLSLv2i32_indexed
|
|
926872U, // SQDMLSLv2i32_v2i64
|
|
52438176U, // SQDMLSLv4i16_indexed
|
|
1057952U, // SQDMLSLv4i16_v4i32
|
|
54273136U, // SQDMLSLv4i32_indexed
|
|
402544U, // SQDMLSLv4i32_v2i64
|
|
52438136U, // SQDMLSLv8i16_indexed
|
|
533624U, // SQDMLSLv8i16_v4i32
|
|
4462680U, // SQDMULH_ZZZI_D
|
|
49288U, // SQDMULH_ZZZI_H
|
|
4468824U, // SQDMULH_ZZZI_S
|
|
10328U, // SQDMULH_ZZZ_B
|
|
6232U, // SQDMULH_ZZZ_D
|
|
136U, // SQDMULH_ZZZ_H
|
|
12376U, // SQDMULH_ZZZ_S
|
|
3160U, // SQDMULHv1i16
|
|
161488984U, // SQDMULHv1i16_indexed
|
|
3160U, // SQDMULHv1i32
|
|
163323992U, // SQDMULHv1i32_indexed
|
|
925848U, // SQDMULHv2i32
|
|
163324056U, // SQDMULHv2i32_indexed
|
|
1056928U, // SQDMULHv4i16
|
|
161489056U, // SQDMULHv4i16_indexed
|
|
401520U, // SQDMULHv4i32
|
|
163324016U, // SQDMULHv4i32_indexed
|
|
532600U, // SQDMULHv8i16
|
|
161489016U, // SQDMULHv8i16_indexed
|
|
4468824U, // SQDMULLB_ZZZI_D
|
|
4461656U, // SQDMULLB_ZZZI_S
|
|
12376U, // SQDMULLB_ZZZ_D
|
|
592U, // SQDMULLB_ZZZ_H
|
|
5208U, // SQDMULLB_ZZZ_S
|
|
4468824U, // SQDMULLT_ZZZI_D
|
|
4461656U, // SQDMULLT_ZZZI_S
|
|
12376U, // SQDMULLT_ZZZ_D
|
|
592U, // SQDMULLT_ZZZ_H
|
|
5208U, // SQDMULLT_ZZZ_S
|
|
3160U, // SQDMULLi16
|
|
3160U, // SQDMULLi32
|
|
161488984U, // SQDMULLv1i32_indexed
|
|
163323992U, // SQDMULLv1i64_indexed
|
|
163324056U, // SQDMULLv2i32_indexed
|
|
925848U, // SQDMULLv2i32_v2i64
|
|
161489056U, // SQDMULLv4i16_indexed
|
|
1056928U, // SQDMULLv4i16_v4i32
|
|
163324016U, // SQDMULLv4i32_indexed
|
|
401520U, // SQDMULLv4i32_v2i64
|
|
161489016U, // SQDMULLv8i16_indexed
|
|
532600U, // SQDMULLv8i16_v4i32
|
|
1U, // SQINCB_XPiI
|
|
3U, // SQINCB_XPiWdI
|
|
1U, // SQINCD_XPiI
|
|
3U, // SQINCD_XPiWdI
|
|
1U, // SQINCD_ZPiI
|
|
1U, // SQINCH_XPiI
|
|
3U, // SQINCH_XPiWdI
|
|
0U, // SQINCH_ZPiI
|
|
92248U, // SQINCP_XPWd_B
|
|
92248U, // SQINCP_XPWd_D
|
|
92248U, // SQINCP_XPWd_H
|
|
92248U, // SQINCP_XPWd_S
|
|
32U, // SQINCP_XP_B
|
|
32U, // SQINCP_XP_D
|
|
32U, // SQINCP_XP_H
|
|
32U, // SQINCP_XP_S
|
|
32U, // SQINCP_ZP_D
|
|
0U, // SQINCP_ZP_H
|
|
32U, // SQINCP_ZP_S
|
|
1U, // SQINCW_XPiI
|
|
3U, // SQINCW_XPiWdI
|
|
1U, // SQINCW_ZPiI
|
|
0U, // SQNEG_ZPmZ_B
|
|
8U, // SQNEG_ZPmZ_D
|
|
0U, // SQNEG_ZPmZ_H
|
|
16U, // SQNEG_ZPmZ_S
|
|
24U, // SQNEGv16i8
|
|
32U, // SQNEGv1i16
|
|
32U, // SQNEGv1i32
|
|
32U, // SQNEGv1i64
|
|
32U, // SQNEGv1i8
|
|
40U, // SQNEGv2i32
|
|
48U, // SQNEGv2i64
|
|
56U, // SQNEGv4i16
|
|
64U, // SQNEGv4i32
|
|
72U, // SQNEGv8i16
|
|
80U, // SQNEGv8i8
|
|
92444952U, // SQRDCMLAH_ZZZI_H
|
|
1159596120U, // SQRDCMLAH_ZZZI_S
|
|
2501633U, // SQRDCMLAH_ZZZ_B
|
|
100795480U, // SQRDCMLAH_ZZZ_D
|
|
2501912U, // SQRDCMLAH_ZZZ_H
|
|
100796504U, // SQRDCMLAH_ZZZ_S
|
|
27133016U, // SQRDMLAH_ZZZI_D
|
|
39192U, // SQRDMLAH_ZZZI_H
|
|
27134040U, // SQRDMLAH_ZZZI_S
|
|
1U, // SQRDMLAH_ZZZ_B
|
|
1112U, // SQRDMLAH_ZZZ_D
|
|
280U, // SQRDMLAH_ZZZ_H
|
|
2136U, // SQRDMLAH_ZZZ_S
|
|
52438105U, // SQRDMLAHi16_indexed
|
|
54273113U, // SQRDMLAHi32_indexed
|
|
37977U, // SQRDMLAHv1i16
|
|
37977U, // SQRDMLAHv1i32
|
|
926872U, // SQRDMLAHv2i32
|
|
54273176U, // SQRDMLAHv2i32_indexed
|
|
1057952U, // SQRDMLAHv4i16
|
|
52438176U, // SQRDMLAHv4i16_indexed
|
|
402544U, // SQRDMLAHv4i32
|
|
54273136U, // SQRDMLAHv4i32_indexed
|
|
533624U, // SQRDMLAHv8i16
|
|
52438136U, // SQRDMLAHv8i16_indexed
|
|
27133016U, // SQRDMLSH_ZZZI_D
|
|
39192U, // SQRDMLSH_ZZZI_H
|
|
27134040U, // SQRDMLSH_ZZZI_S
|
|
1U, // SQRDMLSH_ZZZ_B
|
|
1112U, // SQRDMLSH_ZZZ_D
|
|
280U, // SQRDMLSH_ZZZ_H
|
|
2136U, // SQRDMLSH_ZZZ_S
|
|
52438105U, // SQRDMLSHi16_indexed
|
|
54273113U, // SQRDMLSHi32_indexed
|
|
37977U, // SQRDMLSHv1i16
|
|
37977U, // SQRDMLSHv1i32
|
|
926872U, // SQRDMLSHv2i32
|
|
54273176U, // SQRDMLSHv2i32_indexed
|
|
1057952U, // SQRDMLSHv4i16
|
|
52438176U, // SQRDMLSHv4i16_indexed
|
|
402544U, // SQRDMLSHv4i32
|
|
54273136U, // SQRDMLSHv4i32_indexed
|
|
533624U, // SQRDMLSHv8i16
|
|
52438136U, // SQRDMLSHv8i16_indexed
|
|
4462680U, // SQRDMULH_ZZZI_D
|
|
49288U, // SQRDMULH_ZZZI_H
|
|
4468824U, // SQRDMULH_ZZZI_S
|
|
10328U, // SQRDMULH_ZZZ_B
|
|
6232U, // SQRDMULH_ZZZ_D
|
|
136U, // SQRDMULH_ZZZ_H
|
|
12376U, // SQRDMULH_ZZZ_S
|
|
3160U, // SQRDMULHv1i16
|
|
161488984U, // SQRDMULHv1i16_indexed
|
|
3160U, // SQRDMULHv1i32
|
|
163323992U, // SQRDMULHv1i32_indexed
|
|
925848U, // SQRDMULHv2i32
|
|
163324056U, // SQRDMULHv2i32_indexed
|
|
1056928U, // SQRDMULHv4i16
|
|
161489056U, // SQRDMULHv4i16_indexed
|
|
401520U, // SQRDMULHv4i32
|
|
163324016U, // SQRDMULHv4i32_indexed
|
|
532600U, // SQRDMULHv8i16
|
|
161489016U, // SQRDMULHv8i16_indexed
|
|
8530048U, // SQRSHLR_ZPmZ_B
|
|
16914560U, // SQRSHLR_ZPmZ_D
|
|
25832584U, // SQRSHLR_ZPmZ_H
|
|
33697920U, // SQRSHLR_ZPmZ_S
|
|
8530048U, // SQRSHL_ZPmZ_B
|
|
16914560U, // SQRSHL_ZPmZ_D
|
|
25832584U, // SQRSHL_ZPmZ_H
|
|
33697920U, // SQRSHL_ZPmZ_S
|
|
794768U, // SQRSHLv16i8
|
|
3160U, // SQRSHLv1i16
|
|
3160U, // SQRSHLv1i32
|
|
3160U, // SQRSHLv1i64
|
|
3160U, // SQRSHLv1i8
|
|
925848U, // SQRSHLv2i32
|
|
270440U, // SQRSHLv2i64
|
|
1056928U, // SQRSHLv4i16
|
|
401520U, // SQRSHLv4i32
|
|
532600U, // SQRSHLv8i16
|
|
1188008U, // SQRSHLv8i8
|
|
3160U, // SQRSHRNB_ZZI_B
|
|
200U, // SQRSHRNB_ZZI_H
|
|
3160U, // SQRSHRNB_ZZI_S
|
|
37976U, // SQRSHRNT_ZZI_B
|
|
320U, // SQRSHRNT_ZZI_H
|
|
37976U, // SQRSHRNT_ZZI_S
|
|
3160U, // SQRSHRNb
|
|
3160U, // SQRSHRNh
|
|
3160U, // SQRSHRNs
|
|
38008U, // SQRSHRNv16i8_shift
|
|
3176U, // SQRSHRNv2i32_shift
|
|
3184U, // SQRSHRNv4i16_shift
|
|
37992U, // SQRSHRNv4i32_shift
|
|
38000U, // SQRSHRNv8i16_shift
|
|
3192U, // SQRSHRNv8i8_shift
|
|
3160U, // SQRSHRUNB_ZZI_B
|
|
200U, // SQRSHRUNB_ZZI_H
|
|
3160U, // SQRSHRUNB_ZZI_S
|
|
37976U, // SQRSHRUNT_ZZI_B
|
|
320U, // SQRSHRUNT_ZZI_H
|
|
37976U, // SQRSHRUNT_ZZI_S
|
|
3160U, // SQRSHRUNb
|
|
3160U, // SQRSHRUNh
|
|
3160U, // SQRSHRUNs
|
|
38008U, // SQRSHRUNv16i8_shift
|
|
3176U, // SQRSHRUNv2i32_shift
|
|
3184U, // SQRSHRUNv4i16_shift
|
|
37992U, // SQRSHRUNv4i32_shift
|
|
38000U, // SQRSHRUNv8i16_shift
|
|
3192U, // SQRSHRUNv8i8_shift
|
|
8530048U, // SQSHLR_ZPmZ_B
|
|
16914560U, // SQSHLR_ZPmZ_D
|
|
25832584U, // SQSHLR_ZPmZ_H
|
|
33697920U, // SQSHLR_ZPmZ_S
|
|
141440U, // SQSHLU_ZPmI_B
|
|
137344U, // SQSHLU_ZPmI_D
|
|
1453192U, // SQSHLU_ZPmI_H
|
|
143488U, // SQSHLU_ZPmI_S
|
|
3160U, // SQSHLUb
|
|
3160U, // SQSHLUd
|
|
3160U, // SQSHLUh
|
|
3160U, // SQSHLUs
|
|
3216U, // SQSHLUv16i8_shift
|
|
3224U, // SQSHLUv2i32_shift
|
|
3176U, // SQSHLUv2i64_shift
|
|
3232U, // SQSHLUv4i16_shift
|
|
3184U, // SQSHLUv4i32_shift
|
|
3192U, // SQSHLUv8i16_shift
|
|
3240U, // SQSHLUv8i8_shift
|
|
141440U, // SQSHL_ZPmI_B
|
|
137344U, // SQSHL_ZPmI_D
|
|
1453192U, // SQSHL_ZPmI_H
|
|
143488U, // SQSHL_ZPmI_S
|
|
8530048U, // SQSHL_ZPmZ_B
|
|
16914560U, // SQSHL_ZPmZ_D
|
|
25832584U, // SQSHL_ZPmZ_H
|
|
33697920U, // SQSHL_ZPmZ_S
|
|
3160U, // SQSHLb
|
|
3160U, // SQSHLd
|
|
3160U, // SQSHLh
|
|
3160U, // SQSHLs
|
|
794768U, // SQSHLv16i8
|
|
3216U, // SQSHLv16i8_shift
|
|
3160U, // SQSHLv1i16
|
|
3160U, // SQSHLv1i32
|
|
3160U, // SQSHLv1i64
|
|
3160U, // SQSHLv1i8
|
|
925848U, // SQSHLv2i32
|
|
3224U, // SQSHLv2i32_shift
|
|
270440U, // SQSHLv2i64
|
|
3176U, // SQSHLv2i64_shift
|
|
1056928U, // SQSHLv4i16
|
|
3232U, // SQSHLv4i16_shift
|
|
401520U, // SQSHLv4i32
|
|
3184U, // SQSHLv4i32_shift
|
|
532600U, // SQSHLv8i16
|
|
3192U, // SQSHLv8i16_shift
|
|
1188008U, // SQSHLv8i8
|
|
3240U, // SQSHLv8i8_shift
|
|
3160U, // SQSHRNB_ZZI_B
|
|
200U, // SQSHRNB_ZZI_H
|
|
3160U, // SQSHRNB_ZZI_S
|
|
37976U, // SQSHRNT_ZZI_B
|
|
320U, // SQSHRNT_ZZI_H
|
|
37976U, // SQSHRNT_ZZI_S
|
|
3160U, // SQSHRNb
|
|
3160U, // SQSHRNh
|
|
3160U, // SQSHRNs
|
|
38008U, // SQSHRNv16i8_shift
|
|
3176U, // SQSHRNv2i32_shift
|
|
3184U, // SQSHRNv4i16_shift
|
|
37992U, // SQSHRNv4i32_shift
|
|
38000U, // SQSHRNv8i16_shift
|
|
3192U, // SQSHRNv8i8_shift
|
|
3160U, // SQSHRUNB_ZZI_B
|
|
200U, // SQSHRUNB_ZZI_H
|
|
3160U, // SQSHRUNB_ZZI_S
|
|
37976U, // SQSHRUNT_ZZI_B
|
|
320U, // SQSHRUNT_ZZI_H
|
|
37976U, // SQSHRUNT_ZZI_S
|
|
3160U, // SQSHRUNb
|
|
3160U, // SQSHRUNh
|
|
3160U, // SQSHRUNs
|
|
38008U, // SQSHRUNv16i8_shift
|
|
3176U, // SQSHRUNv2i32_shift
|
|
3184U, // SQSHRUNv4i16_shift
|
|
37992U, // SQSHRUNv4i32_shift
|
|
38000U, // SQSHRUNv8i16_shift
|
|
3192U, // SQSHRUNv8i8_shift
|
|
8530048U, // SQSUBR_ZPmZ_B
|
|
16914560U, // SQSUBR_ZPmZ_D
|
|
25832584U, // SQSUBR_ZPmZ_H
|
|
33697920U, // SQSUBR_ZPmZ_S
|
|
16472U, // SQSUB_ZI_B
|
|
17496U, // SQSUB_ZI_D
|
|
176U, // SQSUB_ZI_H
|
|
18520U, // SQSUB_ZI_S
|
|
8530048U, // SQSUB_ZPmZ_B
|
|
16914560U, // SQSUB_ZPmZ_D
|
|
25832584U, // SQSUB_ZPmZ_H
|
|
33697920U, // SQSUB_ZPmZ_S
|
|
10328U, // SQSUB_ZZZ_B
|
|
6232U, // SQSUB_ZZZ_D
|
|
136U, // SQSUB_ZZZ_H
|
|
12376U, // SQSUB_ZZZ_S
|
|
794768U, // SQSUBv16i8
|
|
3160U, // SQSUBv1i16
|
|
3160U, // SQSUBv1i32
|
|
3160U, // SQSUBv1i64
|
|
3160U, // SQSUBv1i8
|
|
925848U, // SQSUBv2i32
|
|
270440U, // SQSUBv2i64
|
|
1056928U, // SQSUBv4i16
|
|
401520U, // SQSUBv4i32
|
|
532600U, // SQSUBv8i16
|
|
1188008U, // SQSUBv8i8
|
|
32U, // SQXTNB_ZZ_B
|
|
0U, // SQXTNB_ZZ_H
|
|
32U, // SQXTNB_ZZ_S
|
|
32U, // SQXTNT_ZZ_B
|
|
0U, // SQXTNT_ZZ_H
|
|
32U, // SQXTNT_ZZ_S
|
|
72U, // SQXTNv16i8
|
|
32U, // SQXTNv1i16
|
|
32U, // SQXTNv1i32
|
|
32U, // SQXTNv1i8
|
|
48U, // SQXTNv2i32
|
|
64U, // SQXTNv4i16
|
|
48U, // SQXTNv4i32
|
|
64U, // SQXTNv8i16
|
|
72U, // SQXTNv8i8
|
|
32U, // SQXTUNB_ZZ_B
|
|
0U, // SQXTUNB_ZZ_H
|
|
32U, // SQXTUNB_ZZ_S
|
|
32U, // SQXTUNT_ZZ_B
|
|
0U, // SQXTUNT_ZZ_H
|
|
32U, // SQXTUNT_ZZ_S
|
|
72U, // SQXTUNv16i8
|
|
32U, // SQXTUNv1i16
|
|
32U, // SQXTUNv1i32
|
|
32U, // SQXTUNv1i8
|
|
48U, // SQXTUNv2i32
|
|
64U, // SQXTUNv4i16
|
|
48U, // SQXTUNv4i32
|
|
64U, // SQXTUNv8i16
|
|
72U, // SQXTUNv8i8
|
|
8530048U, // SRHADD_ZPmZ_B
|
|
16914560U, // SRHADD_ZPmZ_D
|
|
25832584U, // SRHADD_ZPmZ_H
|
|
33697920U, // SRHADD_ZPmZ_S
|
|
794768U, // SRHADDv16i8
|
|
925848U, // SRHADDv2i32
|
|
1056928U, // SRHADDv4i16
|
|
401520U, // SRHADDv4i32
|
|
532600U, // SRHADDv8i16
|
|
1188008U, // SRHADDv8i8
|
|
321U, // SRI_ZZI_B
|
|
37976U, // SRI_ZZI_D
|
|
320U, // SRI_ZZI_H
|
|
37976U, // SRI_ZZI_S
|
|
37977U, // SRId
|
|
38032U, // SRIv16i8_shift
|
|
38040U, // SRIv2i32_shift
|
|
37992U, // SRIv2i64_shift
|
|
38048U, // SRIv4i16_shift
|
|
38000U, // SRIv4i32_shift
|
|
38008U, // SRIv8i16_shift
|
|
38056U, // SRIv8i8_shift
|
|
8530048U, // SRSHLR_ZPmZ_B
|
|
16914560U, // SRSHLR_ZPmZ_D
|
|
25832584U, // SRSHLR_ZPmZ_H
|
|
33697920U, // SRSHLR_ZPmZ_S
|
|
8530048U, // SRSHL_ZPmZ_B
|
|
16914560U, // SRSHL_ZPmZ_D
|
|
25832584U, // SRSHL_ZPmZ_H
|
|
33697920U, // SRSHL_ZPmZ_S
|
|
794768U, // SRSHLv16i8
|
|
3160U, // SRSHLv1i64
|
|
925848U, // SRSHLv2i32
|
|
270440U, // SRSHLv2i64
|
|
1056928U, // SRSHLv4i16
|
|
401520U, // SRSHLv4i32
|
|
532600U, // SRSHLv8i16
|
|
1188008U, // SRSHLv8i8
|
|
141440U, // SRSHR_ZPmI_B
|
|
137344U, // SRSHR_ZPmI_D
|
|
1453192U, // SRSHR_ZPmI_H
|
|
143488U, // SRSHR_ZPmI_S
|
|
3160U, // SRSHRd
|
|
3216U, // SRSHRv16i8_shift
|
|
3224U, // SRSHRv2i32_shift
|
|
3176U, // SRSHRv2i64_shift
|
|
3232U, // SRSHRv4i16_shift
|
|
3184U, // SRSHRv4i32_shift
|
|
3192U, // SRSHRv8i16_shift
|
|
3240U, // SRSHRv8i8_shift
|
|
321U, // SRSRA_ZZI_B
|
|
37976U, // SRSRA_ZZI_D
|
|
320U, // SRSRA_ZZI_H
|
|
37976U, // SRSRA_ZZI_S
|
|
37977U, // SRSRAd
|
|
38032U, // SRSRAv16i8_shift
|
|
38040U, // SRSRAv2i32_shift
|
|
37992U, // SRSRAv2i64_shift
|
|
38048U, // SRSRAv4i16_shift
|
|
38000U, // SRSRAv4i32_shift
|
|
38008U, // SRSRAv8i16_shift
|
|
38056U, // SRSRAv8i8_shift
|
|
3160U, // SSHLLB_ZZI_D
|
|
200U, // SSHLLB_ZZI_H
|
|
3160U, // SSHLLB_ZZI_S
|
|
3160U, // SSHLLT_ZZI_D
|
|
200U, // SSHLLT_ZZI_H
|
|
3160U, // SSHLLT_ZZI_S
|
|
3216U, // SSHLLv16i8_shift
|
|
3224U, // SSHLLv2i32_shift
|
|
3232U, // SSHLLv4i16_shift
|
|
3184U, // SSHLLv4i32_shift
|
|
3192U, // SSHLLv8i16_shift
|
|
3240U, // SSHLLv8i8_shift
|
|
794768U, // SSHLv16i8
|
|
3160U, // SSHLv1i64
|
|
925848U, // SSHLv2i32
|
|
270440U, // SSHLv2i64
|
|
1056928U, // SSHLv4i16
|
|
401520U, // SSHLv4i32
|
|
532600U, // SSHLv8i16
|
|
1188008U, // SSHLv8i8
|
|
3160U, // SSHRd
|
|
3216U, // SSHRv16i8_shift
|
|
3224U, // SSHRv2i32_shift
|
|
3176U, // SSHRv2i64_shift
|
|
3232U, // SSHRv4i16_shift
|
|
3184U, // SSHRv4i32_shift
|
|
3192U, // SSHRv8i16_shift
|
|
3240U, // SSHRv8i8_shift
|
|
321U, // SSRA_ZZI_B
|
|
37976U, // SSRA_ZZI_D
|
|
320U, // SSRA_ZZI_H
|
|
37976U, // SSRA_ZZI_S
|
|
37977U, // SSRAd
|
|
38032U, // SSRAv16i8_shift
|
|
38040U, // SSRAv2i32_shift
|
|
37992U, // SSRAv2i64_shift
|
|
38048U, // SSRAv4i16_shift
|
|
38000U, // SSRAv4i32_shift
|
|
38008U, // SSRAv8i16_shift
|
|
38056U, // SSRAv8i8_shift
|
|
2397272U, // SST1B_D_IMM
|
|
50265U, // SST1B_D_REAL
|
|
51289U, // SST1B_D_SXTW
|
|
52313U, // SST1B_D_UXTW
|
|
2397272U, // SST1B_S_IMM
|
|
53337U, // SST1B_S_SXTW
|
|
54361U, // SST1B_S_UXTW
|
|
2414680U, // SST1D_IMM
|
|
50265U, // SST1D_REAL
|
|
56409U, // SST1D_SCALED_SCALED_REAL
|
|
51289U, // SST1D_SXTW
|
|
57433U, // SST1D_SXTW_SCALED
|
|
52313U, // SST1D_UXTW
|
|
58457U, // SST1D_UXTW_SCALED
|
|
2418776U, // SST1H_D_IMM
|
|
50265U, // SST1H_D_REAL
|
|
60505U, // SST1H_D_SCALED_SCALED_REAL
|
|
51289U, // SST1H_D_SXTW
|
|
61529U, // SST1H_D_SXTW_SCALED
|
|
52313U, // SST1H_D_UXTW
|
|
62553U, // SST1H_D_UXTW_SCALED
|
|
2418776U, // SST1H_S_IMM
|
|
53337U, // SST1H_S_SXTW
|
|
63577U, // SST1H_S_SXTW_SCALED
|
|
54361U, // SST1H_S_UXTW
|
|
64601U, // SST1H_S_UXTW_SCALED
|
|
2424920U, // SST1W_D_IMM
|
|
50265U, // SST1W_D_REAL
|
|
66649U, // SST1W_D_SCALED_SCALED_REAL
|
|
51289U, // SST1W_D_SXTW
|
|
67673U, // SST1W_D_SXTW_SCALED
|
|
52313U, // SST1W_D_UXTW
|
|
68697U, // SST1W_D_UXTW_SCALED
|
|
2424920U, // SST1W_IMM
|
|
53337U, // SST1W_SXTW
|
|
69721U, // SST1W_SXTW_SCALED
|
|
54361U, // SST1W_UXTW
|
|
70745U, // SST1W_UXTW_SCALED
|
|
12376U, // SSUBLBT_ZZZ_D
|
|
592U, // SSUBLBT_ZZZ_H
|
|
5208U, // SSUBLBT_ZZZ_S
|
|
12376U, // SSUBLB_ZZZ_D
|
|
592U, // SSUBLB_ZZZ_H
|
|
5208U, // SSUBLB_ZZZ_S
|
|
12376U, // SSUBLTB_ZZZ_D
|
|
592U, // SSUBLTB_ZZZ_H
|
|
5208U, // SSUBLTB_ZZZ_S
|
|
12376U, // SSUBLT_ZZZ_D
|
|
592U, // SSUBLT_ZZZ_H
|
|
5208U, // SSUBLT_ZZZ_S
|
|
794768U, // SSUBLv16i8_v8i16
|
|
925848U, // SSUBLv2i32_v2i64
|
|
1056928U, // SSUBLv4i16_v4i32
|
|
401520U, // SSUBLv4i32_v2i64
|
|
532600U, // SSUBLv8i16_v4i32
|
|
1188008U, // SSUBLv8i8_v8i16
|
|
12376U, // SSUBWB_ZZZ_D
|
|
592U, // SSUBWB_ZZZ_H
|
|
5208U, // SSUBWB_ZZZ_S
|
|
12376U, // SSUBWT_ZZZ_D
|
|
592U, // SSUBWT_ZZZ_H
|
|
5208U, // SSUBWT_ZZZ_S
|
|
794744U, // SSUBWv16i8_v8i16
|
|
925800U, // SSUBWv2i32_v2i64
|
|
1056880U, // SSUBWv4i16_v4i32
|
|
401512U, // SSUBWv4i32_v2i64
|
|
532592U, // SSUBWv8i16_v4i32
|
|
1187960U, // SSUBWv8i8_v8i16
|
|
72793U, // ST1B
|
|
72793U, // ST1B_D
|
|
4625497U, // ST1B_D_IMM
|
|
72793U, // ST1B_H
|
|
4625497U, // ST1B_H_IMM
|
|
4625497U, // ST1B_IMM
|
|
72793U, // ST1B_S
|
|
4625497U, // ST1B_S_IMM
|
|
73817U, // ST1D
|
|
4625497U, // ST1D_IMM
|
|
0U, // ST1Fourv16b
|
|
0U, // ST1Fourv16b_POST
|
|
0U, // ST1Fourv1d
|
|
0U, // ST1Fourv1d_POST
|
|
0U, // ST1Fourv2d
|
|
0U, // ST1Fourv2d_POST
|
|
0U, // ST1Fourv2s
|
|
0U, // ST1Fourv2s_POST
|
|
0U, // ST1Fourv4h
|
|
0U, // ST1Fourv4h_POST
|
|
0U, // ST1Fourv4s
|
|
0U, // ST1Fourv4s_POST
|
|
0U, // ST1Fourv8b
|
|
0U, // ST1Fourv8b_POST
|
|
0U, // ST1Fourv8h
|
|
0U, // ST1Fourv8h_POST
|
|
74841U, // ST1H
|
|
74841U, // ST1H_D
|
|
4625497U, // ST1H_D_IMM
|
|
4625497U, // ST1H_IMM
|
|
74841U, // ST1H_S
|
|
4625497U, // ST1H_S_IMM
|
|
0U, // ST1Onev16b
|
|
0U, // ST1Onev16b_POST
|
|
0U, // ST1Onev1d
|
|
0U, // ST1Onev1d_POST
|
|
0U, // ST1Onev2d
|
|
0U, // ST1Onev2d_POST
|
|
0U, // ST1Onev2s
|
|
0U, // ST1Onev2s_POST
|
|
0U, // ST1Onev4h
|
|
0U, // ST1Onev4h_POST
|
|
0U, // ST1Onev4s
|
|
0U, // ST1Onev4s_POST
|
|
0U, // ST1Onev8b
|
|
0U, // ST1Onev8b_POST
|
|
0U, // ST1Onev8h
|
|
0U, // ST1Onev8h_POST
|
|
0U, // ST1Threev16b
|
|
0U, // ST1Threev16b_POST
|
|
0U, // ST1Threev1d
|
|
0U, // ST1Threev1d_POST
|
|
0U, // ST1Threev2d
|
|
0U, // ST1Threev2d_POST
|
|
0U, // ST1Threev2s
|
|
0U, // ST1Threev2s_POST
|
|
0U, // ST1Threev4h
|
|
0U, // ST1Threev4h_POST
|
|
0U, // ST1Threev4s
|
|
0U, // ST1Threev4s_POST
|
|
0U, // ST1Threev8b
|
|
0U, // ST1Threev8b_POST
|
|
0U, // ST1Threev8h
|
|
0U, // ST1Threev8h_POST
|
|
0U, // ST1Twov16b
|
|
0U, // ST1Twov16b_POST
|
|
0U, // ST1Twov1d
|
|
0U, // ST1Twov1d_POST
|
|
0U, // ST1Twov2d
|
|
0U, // ST1Twov2d_POST
|
|
0U, // ST1Twov2s
|
|
0U, // ST1Twov2s_POST
|
|
0U, // ST1Twov4h
|
|
0U, // ST1Twov4h_POST
|
|
0U, // ST1Twov4s
|
|
0U, // ST1Twov4s_POST
|
|
0U, // ST1Twov8b
|
|
0U, // ST1Twov8b_POST
|
|
0U, // ST1Twov8h
|
|
0U, // ST1Twov8h_POST
|
|
76889U, // ST1W
|
|
76889U, // ST1W_D
|
|
4625497U, // ST1W_D_IMM
|
|
4625497U, // ST1W_IMM
|
|
531U, // ST1_MXIPXX_H_B
|
|
539U, // ST1_MXIPXX_H_D
|
|
547U, // ST1_MXIPXX_H_H
|
|
555U, // ST1_MXIPXX_H_Q
|
|
563U, // ST1_MXIPXX_H_S
|
|
531U, // ST1_MXIPXX_V_B
|
|
539U, // ST1_MXIPXX_V_D
|
|
547U, // ST1_MXIPXX_V_H
|
|
555U, // ST1_MXIPXX_V_Q
|
|
563U, // ST1_MXIPXX_V_S
|
|
0U, // ST1i16
|
|
3U, // ST1i16_POST
|
|
0U, // ST1i32
|
|
3U, // ST1i32_POST
|
|
0U, // ST1i64
|
|
3U, // ST1i64_POST
|
|
0U, // ST1i8
|
|
3U, // ST1i8_POST
|
|
72793U, // ST2B
|
|
4647001U, // ST2B_IMM
|
|
73817U, // ST2D
|
|
4647001U, // ST2D_IMM
|
|
2363480U, // ST2GOffset
|
|
78401U, // ST2GPostIndex
|
|
4927577U, // ST2GPreIndex
|
|
74841U, // ST2H
|
|
4647001U, // ST2H_IMM
|
|
0U, // ST2Twov16b
|
|
0U, // ST2Twov16b_POST
|
|
0U, // ST2Twov2d
|
|
0U, // ST2Twov2d_POST
|
|
0U, // ST2Twov2s
|
|
0U, // ST2Twov2s_POST
|
|
0U, // ST2Twov4h
|
|
0U, // ST2Twov4h_POST
|
|
0U, // ST2Twov4s
|
|
0U, // ST2Twov4s_POST
|
|
0U, // ST2Twov8b
|
|
0U, // ST2Twov8b_POST
|
|
0U, // ST2Twov8h
|
|
0U, // ST2Twov8h_POST
|
|
76889U, // ST2W
|
|
4647001U, // ST2W_IMM
|
|
0U, // ST2i16
|
|
3U, // ST2i16_POST
|
|
0U, // ST2i32
|
|
3U, // ST2i32_POST
|
|
0U, // ST2i64
|
|
3U, // ST2i64_POST
|
|
0U, // ST2i8
|
|
3U, // ST2i8_POST
|
|
72793U, // ST3B
|
|
78937U, // ST3B_IMM
|
|
73817U, // ST3D
|
|
78937U, // ST3D_IMM
|
|
74841U, // ST3H
|
|
78937U, // ST3H_IMM
|
|
0U, // ST3Threev16b
|
|
0U, // ST3Threev16b_POST
|
|
0U, // ST3Threev2d
|
|
0U, // ST3Threev2d_POST
|
|
0U, // ST3Threev2s
|
|
0U, // ST3Threev2s_POST
|
|
0U, // ST3Threev4h
|
|
0U, // ST3Threev4h_POST
|
|
0U, // ST3Threev4s
|
|
0U, // ST3Threev4s_POST
|
|
0U, // ST3Threev8b
|
|
0U, // ST3Threev8b_POST
|
|
0U, // ST3Threev8h
|
|
0U, // ST3Threev8h_POST
|
|
76889U, // ST3W
|
|
78937U, // ST3W_IMM
|
|
0U, // ST3i16
|
|
3U, // ST3i16_POST
|
|
0U, // ST3i32
|
|
3U, // ST3i32_POST
|
|
0U, // ST3i64
|
|
3U, // ST3i64_POST
|
|
0U, // ST3i8
|
|
3U, // ST3i8_POST
|
|
72793U, // ST4B
|
|
4653145U, // ST4B_IMM
|
|
73817U, // ST4D
|
|
4653145U, // ST4D_IMM
|
|
0U, // ST4Fourv16b
|
|
0U, // ST4Fourv16b_POST
|
|
0U, // ST4Fourv2d
|
|
0U, // ST4Fourv2d_POST
|
|
0U, // ST4Fourv2s
|
|
0U, // ST4Fourv2s_POST
|
|
0U, // ST4Fourv4h
|
|
0U, // ST4Fourv4h_POST
|
|
0U, // ST4Fourv4s
|
|
0U, // ST4Fourv4s_POST
|
|
0U, // ST4Fourv8b
|
|
0U, // ST4Fourv8b_POST
|
|
0U, // ST4Fourv8h
|
|
0U, // ST4Fourv8h_POST
|
|
74841U, // ST4H
|
|
4653145U, // ST4H_IMM
|
|
76889U, // ST4W
|
|
4653145U, // ST4W_IMM
|
|
0U, // ST4i16
|
|
3U, // ST4i16_POST
|
|
0U, // ST4i32
|
|
3U, // ST4i32_POST
|
|
0U, // ST4i64
|
|
3U, // ST4i64_POST
|
|
0U, // ST4i8
|
|
3U, // ST4i8_POST
|
|
0U, // ST64B
|
|
3U, // ST64BV
|
|
3U, // ST64BV0
|
|
568U, // STGM
|
|
2363480U, // STGOffset
|
|
184683728U, // STGPi
|
|
78401U, // STGPostIndex
|
|
214471889U, // STGPpost
|
|
2894238929U, // STGPpre
|
|
4927577U, // STGPreIndex
|
|
568U, // STLLRB
|
|
568U, // STLLRH
|
|
568U, // STLLRW
|
|
568U, // STLLRX
|
|
568U, // STLRB
|
|
568U, // STLRH
|
|
568U, // STLRW
|
|
568U, // STLRX
|
|
2362456U, // STLURBi
|
|
2362456U, // STLURHi
|
|
2362456U, // STLURWi
|
|
2362456U, // STLURXi
|
|
5246040U, // STLXPW
|
|
5246040U, // STLXPX
|
|
2362576U, // STLXRB
|
|
2362576U, // STLXRH
|
|
2362576U, // STLXRW
|
|
2362576U, // STLXRX
|
|
176295120U, // STNPDi
|
|
184683728U, // STNPQi
|
|
193072336U, // STNPSi
|
|
193072336U, // STNPWi
|
|
176295120U, // STNPXi
|
|
4625497U, // STNT1B_ZRI
|
|
72793U, // STNT1B_ZRR
|
|
2397272U, // STNT1B_ZZR_D_REAL
|
|
2397272U, // STNT1B_ZZR_S_REAL
|
|
4625497U, // STNT1D_ZRI
|
|
73817U, // STNT1D_ZRR
|
|
2397272U, // STNT1D_ZZR_D_REAL
|
|
4625497U, // STNT1H_ZRI
|
|
74841U, // STNT1H_ZRR
|
|
2397272U, // STNT1H_ZZR_D_REAL
|
|
2397272U, // STNT1H_ZZR_S_REAL
|
|
4625497U, // STNT1W_ZRI
|
|
76889U, // STNT1W_ZRR
|
|
2397272U, // STNT1W_ZZR_D_REAL
|
|
2397272U, // STNT1W_ZZR_S_REAL
|
|
176295120U, // STPDi
|
|
206083281U, // STPDpost
|
|
2885850321U, // STPDpre
|
|
184683728U, // STPQi
|
|
214471889U, // STPQpost
|
|
2894238929U, // STPQpre
|
|
193072336U, // STPSi
|
|
222860497U, // STPSpost
|
|
2902627537U, // STPSpre
|
|
193072336U, // STPWi
|
|
222860497U, // STPWpost
|
|
2902627537U, // STPWpre
|
|
176295120U, // STPXi
|
|
206083281U, // STPXpost
|
|
2885850321U, // STPXpre
|
|
38465U, // STRBBpost
|
|
4887641U, // STRBBpre
|
|
226626648U, // STRBBroW
|
|
235015256U, // STRBBroX
|
|
80984U, // STRBBui
|
|
38465U, // STRBpost
|
|
4887641U, // STRBpre
|
|
226626648U, // STRBroW
|
|
235015256U, // STRBroX
|
|
80984U, // STRBui
|
|
38465U, // STRDpost
|
|
4887641U, // STRDpre
|
|
243403864U, // STRDroW
|
|
251792472U, // STRDroX
|
|
82008U, // STRDui
|
|
38465U, // STRHHpost
|
|
4887641U, // STRHHpre
|
|
260181080U, // STRHHroW
|
|
268569688U, // STRHHroX
|
|
83032U, // STRHHui
|
|
38465U, // STRHpost
|
|
4887641U, // STRHpre
|
|
260181080U, // STRHroW
|
|
268569688U, // STRHroX
|
|
83032U, // STRHui
|
|
38465U, // STRQpost
|
|
4887641U, // STRQpre
|
|
276958296U, // STRQroW
|
|
285346904U, // STRQroX
|
|
84056U, // STRQui
|
|
38465U, // STRSpost
|
|
4887641U, // STRSpre
|
|
293735512U, // STRSroW
|
|
302124120U, // STRSroX
|
|
85080U, // STRSui
|
|
38465U, // STRWpost
|
|
4887641U, // STRWpre
|
|
293735512U, // STRWroW
|
|
302124120U, // STRWroX
|
|
85080U, // STRWui
|
|
38465U, // STRXpost
|
|
4887641U, // STRXpre
|
|
243403864U, // STRXroW
|
|
251792472U, // STRXroX
|
|
82008U, // STRXui
|
|
4590680U, // STR_PXI
|
|
0U, // STR_ZA
|
|
4590680U, // STR_ZXI
|
|
2362456U, // STTRBi
|
|
2362456U, // STTRHi
|
|
2362456U, // STTRWi
|
|
2362456U, // STTRXi
|
|
2362456U, // STURBBi
|
|
2362456U, // STURBi
|
|
2362456U, // STURDi
|
|
2362456U, // STURHHi
|
|
2362456U, // STURHi
|
|
2362456U, // STURQi
|
|
2362456U, // STURSi
|
|
2362456U, // STURWi
|
|
2362456U, // STURXi
|
|
5246040U, // STXPW
|
|
5246040U, // STXPX
|
|
2362576U, // STXRB
|
|
2362576U, // STXRH
|
|
2362576U, // STXRW
|
|
2362576U, // STXRX
|
|
2363480U, // STZ2GOffset
|
|
78401U, // STZ2GPostIndex
|
|
4927577U, // STZ2GPreIndex
|
|
568U, // STZGM
|
|
2363480U, // STZGOffset
|
|
78401U, // STZGPostIndex
|
|
4927577U, // STZGPreIndex
|
|
135256U, // SUBG
|
|
5208U, // SUBHNB_ZZZ_B
|
|
96U, // SUBHNB_ZZZ_H
|
|
6232U, // SUBHNB_ZZZ_S
|
|
7256U, // SUBHNT_ZZZ_B
|
|
16U, // SUBHNT_ZZZ_H
|
|
1112U, // SUBHNT_ZZZ_S
|
|
270440U, // SUBHNv2i64_v2i32
|
|
271464U, // SUBHNv2i64_v4i32
|
|
401520U, // SUBHNv4i32_v4i16
|
|
402544U, // SUBHNv4i32_v8i16
|
|
533624U, // SUBHNv8i16_v16i8
|
|
532600U, // SUBHNv8i16_v8i8
|
|
3160U, // SUBP
|
|
3160U, // SUBPS
|
|
16472U, // SUBR_ZI_B
|
|
17496U, // SUBR_ZI_D
|
|
176U, // SUBR_ZI_H
|
|
18520U, // SUBR_ZI_S
|
|
8530048U, // SUBR_ZPmZ_B
|
|
16914560U, // SUBR_ZPmZ_D
|
|
25832584U, // SUBR_ZPmZ_H
|
|
33697920U, // SUBR_ZPmZ_S
|
|
13400U, // SUBSWri
|
|
14424U, // SUBSWrs
|
|
15448U, // SUBSWrx
|
|
13400U, // SUBSXri
|
|
14424U, // SUBSXrs
|
|
15448U, // SUBSXrx
|
|
1313880U, // SUBSXrx64
|
|
13400U, // SUBWri
|
|
14424U, // SUBWrs
|
|
15448U, // SUBWrx
|
|
13400U, // SUBXri
|
|
14424U, // SUBXrs
|
|
15448U, // SUBXrx
|
|
1313880U, // SUBXrx64
|
|
16472U, // SUB_ZI_B
|
|
17496U, // SUB_ZI_D
|
|
176U, // SUB_ZI_H
|
|
18520U, // SUB_ZI_S
|
|
8530048U, // SUB_ZPmZ_B
|
|
16914560U, // SUB_ZPmZ_D
|
|
25832584U, // SUB_ZPmZ_H
|
|
33697920U, // SUB_ZPmZ_S
|
|
10328U, // SUB_ZZZ_B
|
|
6232U, // SUB_ZZZ_D
|
|
136U, // SUB_ZZZ_H
|
|
12376U, // SUB_ZZZ_S
|
|
794768U, // SUBv16i8
|
|
3160U, // SUBv1i64
|
|
925848U, // SUBv2i32
|
|
270440U, // SUBv2i64
|
|
1056928U, // SUBv4i16
|
|
401520U, // SUBv4i32
|
|
532600U, // SUBv8i16
|
|
1188008U, // SUBv8i8
|
|
38913U, // SUDOT_ZZZI
|
|
5121168U, // SUDOTlanev16i8
|
|
5121192U, // SUDOTlanev8i8
|
|
0U, // SUMOPA_MPPZZ_D
|
|
0U, // SUMOPA_MPPZZ_S
|
|
0U, // SUMOPS_MPPZZ_D
|
|
0U, // SUMOPS_MPPZZ_S
|
|
32U, // SUNPKHI_ZZ_D
|
|
0U, // SUNPKHI_ZZ_H
|
|
32U, // SUNPKHI_ZZ_S
|
|
32U, // SUNPKLO_ZZ_D
|
|
0U, // SUNPKLO_ZZ_H
|
|
32U, // SUNPKLO_ZZ_S
|
|
8530048U, // SUQADD_ZPmZ_B
|
|
16914560U, // SUQADD_ZPmZ_D
|
|
25832584U, // SUQADD_ZPmZ_H
|
|
33697920U, // SUQADD_ZPmZ_S
|
|
24U, // SUQADDv16i8
|
|
33U, // SUQADDv1i16
|
|
33U, // SUQADDv1i32
|
|
33U, // SUQADDv1i64
|
|
33U, // SUQADDv1i8
|
|
40U, // SUQADDv2i32
|
|
48U, // SUQADDv2i64
|
|
56U, // SUQADDv4i16
|
|
64U, // SUQADDv4i32
|
|
72U, // SUQADDv8i16
|
|
80U, // SUQADDv8i8
|
|
0U, // SVC
|
|
2U, // SWPAB
|
|
2U, // SWPAH
|
|
2U, // SWPALB
|
|
2U, // SWPALH
|
|
2U, // SWPALW
|
|
2U, // SWPALX
|
|
2U, // SWPAW
|
|
2U, // SWPAX
|
|
2U, // SWPB
|
|
2U, // SWPH
|
|
2U, // SWPLB
|
|
2U, // SWPLH
|
|
2U, // SWPLW
|
|
2U, // SWPLX
|
|
2U, // SWPW
|
|
2U, // SWPX
|
|
8U, // SXTB_ZPmZ_D
|
|
0U, // SXTB_ZPmZ_H
|
|
16U, // SXTB_ZPmZ_S
|
|
8U, // SXTH_ZPmZ_D
|
|
16U, // SXTH_ZPmZ_S
|
|
8U, // SXTW_ZPmZ_D
|
|
93272U, // SYSLxt
|
|
4U, // SYSxt
|
|
594U, // TBL_ZZZZ_B
|
|
4U, // TBL_ZZZZ_D
|
|
0U, // TBL_ZZZZ_H
|
|
4U, // TBL_ZZZZ_S
|
|
594U, // TBL_ZZZ_B
|
|
4U, // TBL_ZZZ_D
|
|
0U, // TBL_ZZZ_H
|
|
4U, // TBL_ZZZ_S
|
|
28U, // TBLv16i8Four
|
|
28U, // TBLv16i8One
|
|
28U, // TBLv16i8Three
|
|
28U, // TBLv16i8Two
|
|
84U, // TBLv8i8Four
|
|
84U, // TBLv8i8One
|
|
84U, // TBLv8i8Three
|
|
84U, // TBLv8i8Two
|
|
94296U, // TBNZW
|
|
94296U, // TBNZX
|
|
1U, // TBX_ZZZ_B
|
|
1112U, // TBX_ZZZ_D
|
|
280U, // TBX_ZZZ_H
|
|
2136U, // TBX_ZZZ_S
|
|
28U, // TBXv16i8Four
|
|
28U, // TBXv16i8One
|
|
28U, // TBXv16i8Three
|
|
28U, // TBXv16i8Two
|
|
84U, // TBXv8i8Four
|
|
84U, // TBXv8i8One
|
|
84U, // TBXv8i8Three
|
|
84U, // TBXv8i8Two
|
|
94296U, // TBZW
|
|
94296U, // TBZX
|
|
0U, // TCANCEL
|
|
0U, // TCOMMIT
|
|
10328U, // TRN1_PPP_B
|
|
6232U, // TRN1_PPP_D
|
|
136U, // TRN1_PPP_H
|
|
12376U, // TRN1_PPP_S
|
|
10328U, // TRN1_ZZZ_B
|
|
6232U, // TRN1_ZZZ_D
|
|
136U, // TRN1_ZZZ_H
|
|
880U, // TRN1_ZZZ_Q
|
|
12376U, // TRN1_ZZZ_S
|
|
794768U, // TRN1v16i8
|
|
925848U, // TRN1v2i32
|
|
270440U, // TRN1v2i64
|
|
1056928U, // TRN1v4i16
|
|
401520U, // TRN1v4i32
|
|
532600U, // TRN1v8i16
|
|
1188008U, // TRN1v8i8
|
|
10328U, // TRN2_PPP_B
|
|
6232U, // TRN2_PPP_D
|
|
136U, // TRN2_PPP_H
|
|
12376U, // TRN2_PPP_S
|
|
10328U, // TRN2_ZZZ_B
|
|
6232U, // TRN2_ZZZ_D
|
|
136U, // TRN2_ZZZ_H
|
|
880U, // TRN2_ZZZ_Q
|
|
12376U, // TRN2_ZZZ_S
|
|
794768U, // TRN2v16i8
|
|
925848U, // TRN2v2i32
|
|
270440U, // TRN2v2i64
|
|
1056928U, // TRN2v4i16
|
|
401520U, // TRN2v4i32
|
|
532600U, // TRN2v8i16
|
|
1188008U, // TRN2v8i8
|
|
0U, // TSB
|
|
0U, // TSTART
|
|
0U, // TTEST
|
|
2136U, // UABALB_ZZZ_D
|
|
0U, // UABALB_ZZZ_H
|
|
7256U, // UABALB_ZZZ_S
|
|
2136U, // UABALT_ZZZ_D
|
|
0U, // UABALT_ZZZ_H
|
|
7256U, // UABALT_ZZZ_S
|
|
795792U, // UABALv16i8_v8i16
|
|
926872U, // UABALv2i32_v2i64
|
|
1057952U, // UABALv4i16_v4i32
|
|
402544U, // UABALv4i32_v2i64
|
|
533624U, // UABALv8i16_v4i32
|
|
1189032U, // UABALv8i8_v8i16
|
|
1U, // UABA_ZZZ_B
|
|
1112U, // UABA_ZZZ_D
|
|
280U, // UABA_ZZZ_H
|
|
2136U, // UABA_ZZZ_S
|
|
795792U, // UABAv16i8
|
|
926872U, // UABAv2i32
|
|
1057952U, // UABAv4i16
|
|
402544U, // UABAv4i32
|
|
533624U, // UABAv8i16
|
|
1189032U, // UABAv8i8
|
|
12376U, // UABDLB_ZZZ_D
|
|
592U, // UABDLB_ZZZ_H
|
|
5208U, // UABDLB_ZZZ_S
|
|
12376U, // UABDLT_ZZZ_D
|
|
592U, // UABDLT_ZZZ_H
|
|
5208U, // UABDLT_ZZZ_S
|
|
794768U, // UABDLv16i8_v8i16
|
|
925848U, // UABDLv2i32_v2i64
|
|
1056928U, // UABDLv4i16_v4i32
|
|
401520U, // UABDLv4i32_v2i64
|
|
532600U, // UABDLv8i16_v4i32
|
|
1188008U, // UABDLv8i8_v8i16
|
|
8530048U, // UABD_ZPmZ_B
|
|
16914560U, // UABD_ZPmZ_D
|
|
25832584U, // UABD_ZPmZ_H
|
|
33697920U, // UABD_ZPmZ_S
|
|
794768U, // UABDv16i8
|
|
925848U, // UABDv2i32
|
|
1056928U, // UABDv4i16
|
|
401520U, // UABDv4i32
|
|
532600U, // UABDv8i16
|
|
1188008U, // UABDv8i8
|
|
2176U, // UADALP_ZPmZ_D
|
|
0U, // UADALP_ZPmZ_H
|
|
7296U, // UADALP_ZPmZ_S
|
|
24U, // UADALPv16i8_v8i16
|
|
40U, // UADALPv2i32_v1i64
|
|
56U, // UADALPv4i16_v2i32
|
|
64U, // UADALPv4i32_v2i64
|
|
72U, // UADALPv8i16_v4i32
|
|
80U, // UADALPv8i8_v4i16
|
|
12376U, // UADDLB_ZZZ_D
|
|
592U, // UADDLB_ZZZ_H
|
|
5208U, // UADDLB_ZZZ_S
|
|
24U, // UADDLPv16i8_v8i16
|
|
40U, // UADDLPv2i32_v1i64
|
|
56U, // UADDLPv4i16_v2i32
|
|
64U, // UADDLPv4i32_v2i64
|
|
72U, // UADDLPv8i16_v4i32
|
|
80U, // UADDLPv8i8_v4i16
|
|
12376U, // UADDLT_ZZZ_D
|
|
592U, // UADDLT_ZZZ_H
|
|
5208U, // UADDLT_ZZZ_S
|
|
24U, // UADDLVv16i8v
|
|
56U, // UADDLVv4i16v
|
|
64U, // UADDLVv4i32v
|
|
72U, // UADDLVv8i16v
|
|
80U, // UADDLVv8i8v
|
|
794768U, // UADDLv16i8_v8i16
|
|
925848U, // UADDLv2i32_v2i64
|
|
1056928U, // UADDLv4i16_v4i32
|
|
401520U, // UADDLv4i32_v2i64
|
|
532600U, // UADDLv8i16_v4i32
|
|
1188008U, // UADDLv8i8_v8i16
|
|
0U, // UADDV_VPZ_B
|
|
0U, // UADDV_VPZ_D
|
|
0U, // UADDV_VPZ_H
|
|
0U, // UADDV_VPZ_S
|
|
12376U, // UADDWB_ZZZ_D
|
|
592U, // UADDWB_ZZZ_H
|
|
5208U, // UADDWB_ZZZ_S
|
|
12376U, // UADDWT_ZZZ_D
|
|
592U, // UADDWT_ZZZ_H
|
|
5208U, // UADDWT_ZZZ_S
|
|
794744U, // UADDWv16i8_v8i16
|
|
925800U, // UADDWv2i32_v2i64
|
|
1056880U, // UADDWv4i16_v4i32
|
|
401512U, // UADDWv4i32_v2i64
|
|
532592U, // UADDWv8i16_v4i32
|
|
1187960U, // UADDWv8i8_v8i16
|
|
134232U, // UBFMWri
|
|
134232U, // UBFMXri
|
|
10328U, // UCLAMP_ZZZ_B
|
|
6232U, // UCLAMP_ZZZ_D
|
|
136U, // UCLAMP_ZZZ_H
|
|
12376U, // UCLAMP_ZZZ_S
|
|
3160U, // UCVTFSWDri
|
|
3160U, // UCVTFSWHri
|
|
3160U, // UCVTFSWSri
|
|
3160U, // UCVTFSXDri
|
|
3160U, // UCVTFSXHri
|
|
3160U, // UCVTFSXSri
|
|
32U, // UCVTFUWDri
|
|
32U, // UCVTFUWHri
|
|
32U, // UCVTFUWSri
|
|
32U, // UCVTFUXDri
|
|
32U, // UCVTFUXHri
|
|
32U, // UCVTFUXSri
|
|
8U, // UCVTF_ZPmZ_DtoD
|
|
2U, // UCVTF_ZPmZ_DtoH
|
|
8U, // UCVTF_ZPmZ_DtoS
|
|
0U, // UCVTF_ZPmZ_HtoH
|
|
16U, // UCVTF_ZPmZ_StoD
|
|
1U, // UCVTF_ZPmZ_StoH
|
|
16U, // UCVTF_ZPmZ_StoS
|
|
3160U, // UCVTFd
|
|
3160U, // UCVTFh
|
|
3160U, // UCVTFs
|
|
32U, // UCVTFv1i16
|
|
32U, // UCVTFv1i32
|
|
32U, // UCVTFv1i64
|
|
40U, // UCVTFv2f32
|
|
48U, // UCVTFv2f64
|
|
3224U, // UCVTFv2i32_shift
|
|
3176U, // UCVTFv2i64_shift
|
|
56U, // UCVTFv4f16
|
|
64U, // UCVTFv4f32
|
|
3232U, // UCVTFv4i16_shift
|
|
3184U, // UCVTFv4i32_shift
|
|
72U, // UCVTFv8f16
|
|
3192U, // UCVTFv8i16_shift
|
|
0U, // UDF
|
|
16914560U, // UDIVR_ZPmZ_D
|
|
33697920U, // UDIVR_ZPmZ_S
|
|
3160U, // UDIVWr
|
|
3160U, // UDIVXr
|
|
16914560U, // UDIV_ZPmZ_D
|
|
33697920U, // UDIV_ZPmZ_S
|
|
27139160U, // UDOT_ZZZI_D
|
|
38913U, // UDOT_ZZZI_S
|
|
7256U, // UDOT_ZZZ_D
|
|
1U, // UDOT_ZZZ_S
|
|
5121168U, // UDOTlanev16i8
|
|
5121192U, // UDOTlanev8i8
|
|
795792U, // UDOTv16i8
|
|
1189032U, // UDOTv8i8
|
|
8530048U, // UHADD_ZPmZ_B
|
|
16914560U, // UHADD_ZPmZ_D
|
|
25832584U, // UHADD_ZPmZ_H
|
|
33697920U, // UHADD_ZPmZ_S
|
|
794768U, // UHADDv16i8
|
|
925848U, // UHADDv2i32
|
|
1056928U, // UHADDv4i16
|
|
401520U, // UHADDv4i32
|
|
532600U, // UHADDv8i16
|
|
1188008U, // UHADDv8i8
|
|
8530048U, // UHSUBR_ZPmZ_B
|
|
16914560U, // UHSUBR_ZPmZ_D
|
|
25832584U, // UHSUBR_ZPmZ_H
|
|
33697920U, // UHSUBR_ZPmZ_S
|
|
8530048U, // UHSUB_ZPmZ_B
|
|
16914560U, // UHSUB_ZPmZ_D
|
|
25832584U, // UHSUB_ZPmZ_H
|
|
33697920U, // UHSUB_ZPmZ_S
|
|
794768U, // UHSUBv16i8
|
|
925848U, // UHSUBv2i32
|
|
1056928U, // UHSUBv4i16
|
|
401520U, // UHSUBv4i32
|
|
532600U, // UHSUBv8i16
|
|
1188008U, // UHSUBv8i8
|
|
134232U, // UMADDLrrr
|
|
8530048U, // UMAXP_ZPmZ_B
|
|
16914560U, // UMAXP_ZPmZ_D
|
|
25832584U, // UMAXP_ZPmZ_H
|
|
33697920U, // UMAXP_ZPmZ_S
|
|
794768U, // UMAXPv16i8
|
|
925848U, // UMAXPv2i32
|
|
1056928U, // UMAXPv4i16
|
|
401520U, // UMAXPv4i32
|
|
532600U, // UMAXPv8i16
|
|
1188008U, // UMAXPv8i8
|
|
0U, // UMAXV_VPZ_B
|
|
0U, // UMAXV_VPZ_D
|
|
0U, // UMAXV_VPZ_H
|
|
0U, // UMAXV_VPZ_S
|
|
24U, // UMAXVv16i8v
|
|
56U, // UMAXVv4i16v
|
|
64U, // UMAXVv4i32v
|
|
72U, // UMAXVv8i16v
|
|
80U, // UMAXVv8i8v
|
|
95320U, // UMAX_ZI_B
|
|
95320U, // UMAX_ZI_D
|
|
392U, // UMAX_ZI_H
|
|
95320U, // UMAX_ZI_S
|
|
8530048U, // UMAX_ZPmZ_B
|
|
16914560U, // UMAX_ZPmZ_D
|
|
25832584U, // UMAX_ZPmZ_H
|
|
33697920U, // UMAX_ZPmZ_S
|
|
794768U, // UMAXv16i8
|
|
925848U, // UMAXv2i32
|
|
1056928U, // UMAXv4i16
|
|
401520U, // UMAXv4i32
|
|
532600U, // UMAXv8i16
|
|
1188008U, // UMAXv8i8
|
|
8530048U, // UMINP_ZPmZ_B
|
|
16914560U, // UMINP_ZPmZ_D
|
|
25832584U, // UMINP_ZPmZ_H
|
|
33697920U, // UMINP_ZPmZ_S
|
|
794768U, // UMINPv16i8
|
|
925848U, // UMINPv2i32
|
|
1056928U, // UMINPv4i16
|
|
401520U, // UMINPv4i32
|
|
532600U, // UMINPv8i16
|
|
1188008U, // UMINPv8i8
|
|
0U, // UMINV_VPZ_B
|
|
0U, // UMINV_VPZ_D
|
|
0U, // UMINV_VPZ_H
|
|
0U, // UMINV_VPZ_S
|
|
24U, // UMINVv16i8v
|
|
56U, // UMINVv4i16v
|
|
64U, // UMINVv4i32v
|
|
72U, // UMINVv8i16v
|
|
80U, // UMINVv8i8v
|
|
95320U, // UMIN_ZI_B
|
|
95320U, // UMIN_ZI_D
|
|
392U, // UMIN_ZI_H
|
|
95320U, // UMIN_ZI_S
|
|
8530048U, // UMIN_ZPmZ_B
|
|
16914560U, // UMIN_ZPmZ_D
|
|
25832584U, // UMIN_ZPmZ_H
|
|
33697920U, // UMIN_ZPmZ_S
|
|
794768U, // UMINv16i8
|
|
925848U, // UMINv2i32
|
|
1056928U, // UMINv4i16
|
|
401520U, // UMINv4i32
|
|
532600U, // UMINv8i16
|
|
1188008U, // UMINv8i8
|
|
27134040U, // UMLALB_ZZZI_D
|
|
27139160U, // UMLALB_ZZZI_S
|
|
2136U, // UMLALB_ZZZ_D
|
|
0U, // UMLALB_ZZZ_H
|
|
7256U, // UMLALB_ZZZ_S
|
|
27134040U, // UMLALT_ZZZI_D
|
|
27139160U, // UMLALT_ZZZI_S
|
|
2136U, // UMLALT_ZZZ_D
|
|
0U, // UMLALT_ZZZ_H
|
|
7256U, // UMLALT_ZZZ_S
|
|
795792U, // UMLALv16i8_v8i16
|
|
54273176U, // UMLALv2i32_indexed
|
|
926872U, // UMLALv2i32_v2i64
|
|
52438176U, // UMLALv4i16_indexed
|
|
1057952U, // UMLALv4i16_v4i32
|
|
54273136U, // UMLALv4i32_indexed
|
|
402544U, // UMLALv4i32_v2i64
|
|
52438136U, // UMLALv8i16_indexed
|
|
533624U, // UMLALv8i16_v4i32
|
|
1189032U, // UMLALv8i8_v8i16
|
|
27134040U, // UMLSLB_ZZZI_D
|
|
27139160U, // UMLSLB_ZZZI_S
|
|
2136U, // UMLSLB_ZZZ_D
|
|
0U, // UMLSLB_ZZZ_H
|
|
7256U, // UMLSLB_ZZZ_S
|
|
27134040U, // UMLSLT_ZZZI_D
|
|
27139160U, // UMLSLT_ZZZI_S
|
|
2136U, // UMLSLT_ZZZ_D
|
|
0U, // UMLSLT_ZZZ_H
|
|
7256U, // UMLSLT_ZZZ_S
|
|
795792U, // UMLSLv16i8_v8i16
|
|
54273176U, // UMLSLv2i32_indexed
|
|
926872U, // UMLSLv2i32_v2i64
|
|
52438176U, // UMLSLv4i16_indexed
|
|
1057952U, // UMLSLv4i16_v4i32
|
|
54273136U, // UMLSLv4i32_indexed
|
|
402544U, // UMLSLv4i32_v2i64
|
|
52438136U, // UMLSLv8i16_indexed
|
|
533624U, // UMLSLv8i16_v4i32
|
|
1189032U, // UMLSLv8i8_v8i16
|
|
795792U, // UMMLA
|
|
1U, // UMMLA_ZZZ
|
|
0U, // UMOPA_MPPZZ_D
|
|
0U, // UMOPA_MPPZZ_S
|
|
0U, // UMOPS_MPPZZ_D
|
|
0U, // UMOPS_MPPZZ_S
|
|
43352U, // UMOVvi16
|
|
43352U, // UMOVvi16_idx0
|
|
43360U, // UMOVvi32
|
|
43360U, // UMOVvi32_idx0
|
|
43368U, // UMOVvi64
|
|
43368U, // UMOVvi64_idx0
|
|
43376U, // UMOVvi8
|
|
43376U, // UMOVvi8_idx0
|
|
134232U, // UMSUBLrrr
|
|
8530048U, // UMULH_ZPmZ_B
|
|
16914560U, // UMULH_ZPmZ_D
|
|
25832584U, // UMULH_ZPmZ_H
|
|
33697920U, // UMULH_ZPmZ_S
|
|
10328U, // UMULH_ZZZ_B
|
|
6232U, // UMULH_ZZZ_D
|
|
136U, // UMULH_ZZZ_H
|
|
12376U, // UMULH_ZZZ_S
|
|
3160U, // UMULHrr
|
|
4468824U, // UMULLB_ZZZI_D
|
|
4461656U, // UMULLB_ZZZI_S
|
|
12376U, // UMULLB_ZZZ_D
|
|
592U, // UMULLB_ZZZ_H
|
|
5208U, // UMULLB_ZZZ_S
|
|
4468824U, // UMULLT_ZZZI_D
|
|
4461656U, // UMULLT_ZZZI_S
|
|
12376U, // UMULLT_ZZZ_D
|
|
592U, // UMULLT_ZZZ_H
|
|
5208U, // UMULLT_ZZZ_S
|
|
794768U, // UMULLv16i8_v8i16
|
|
163324056U, // UMULLv2i32_indexed
|
|
925848U, // UMULLv2i32_v2i64
|
|
161489056U, // UMULLv4i16_indexed
|
|
1056928U, // UMULLv4i16_v4i32
|
|
163324016U, // UMULLv4i32_indexed
|
|
401520U, // UMULLv4i32_v2i64
|
|
161489016U, // UMULLv8i16_indexed
|
|
532600U, // UMULLv8i16_v4i32
|
|
1188008U, // UMULLv8i8_v8i16
|
|
16472U, // UQADD_ZI_B
|
|
17496U, // UQADD_ZI_D
|
|
176U, // UQADD_ZI_H
|
|
18520U, // UQADD_ZI_S
|
|
8530048U, // UQADD_ZPmZ_B
|
|
16914560U, // UQADD_ZPmZ_D
|
|
25832584U, // UQADD_ZPmZ_H
|
|
33697920U, // UQADD_ZPmZ_S
|
|
10328U, // UQADD_ZZZ_B
|
|
6232U, // UQADD_ZZZ_D
|
|
136U, // UQADD_ZZZ_H
|
|
12376U, // UQADD_ZZZ_S
|
|
794768U, // UQADDv16i8
|
|
3160U, // UQADDv1i16
|
|
3160U, // UQADDv1i32
|
|
3160U, // UQADDv1i64
|
|
3160U, // UQADDv1i8
|
|
925848U, // UQADDv2i32
|
|
270440U, // UQADDv2i64
|
|
1056928U, // UQADDv4i16
|
|
401520U, // UQADDv4i32
|
|
532600U, // UQADDv8i16
|
|
1188008U, // UQADDv8i8
|
|
1U, // UQDECB_WPiI
|
|
1U, // UQDECB_XPiI
|
|
1U, // UQDECD_WPiI
|
|
1U, // UQDECD_XPiI
|
|
1U, // UQDECD_ZPiI
|
|
1U, // UQDECH_WPiI
|
|
1U, // UQDECH_XPiI
|
|
0U, // UQDECH_ZPiI
|
|
32U, // UQDECP_WP_B
|
|
32U, // UQDECP_WP_D
|
|
32U, // UQDECP_WP_H
|
|
32U, // UQDECP_WP_S
|
|
32U, // UQDECP_XP_B
|
|
32U, // UQDECP_XP_D
|
|
32U, // UQDECP_XP_H
|
|
32U, // UQDECP_XP_S
|
|
32U, // UQDECP_ZP_D
|
|
0U, // UQDECP_ZP_H
|
|
32U, // UQDECP_ZP_S
|
|
1U, // UQDECW_WPiI
|
|
1U, // UQDECW_XPiI
|
|
1U, // UQDECW_ZPiI
|
|
1U, // UQINCB_WPiI
|
|
1U, // UQINCB_XPiI
|
|
1U, // UQINCD_WPiI
|
|
1U, // UQINCD_XPiI
|
|
1U, // UQINCD_ZPiI
|
|
1U, // UQINCH_WPiI
|
|
1U, // UQINCH_XPiI
|
|
0U, // UQINCH_ZPiI
|
|
32U, // UQINCP_WP_B
|
|
32U, // UQINCP_WP_D
|
|
32U, // UQINCP_WP_H
|
|
32U, // UQINCP_WP_S
|
|
32U, // UQINCP_XP_B
|
|
32U, // UQINCP_XP_D
|
|
32U, // UQINCP_XP_H
|
|
32U, // UQINCP_XP_S
|
|
32U, // UQINCP_ZP_D
|
|
0U, // UQINCP_ZP_H
|
|
32U, // UQINCP_ZP_S
|
|
1U, // UQINCW_WPiI
|
|
1U, // UQINCW_XPiI
|
|
1U, // UQINCW_ZPiI
|
|
8530048U, // UQRSHLR_ZPmZ_B
|
|
16914560U, // UQRSHLR_ZPmZ_D
|
|
25832584U, // UQRSHLR_ZPmZ_H
|
|
33697920U, // UQRSHLR_ZPmZ_S
|
|
8530048U, // UQRSHL_ZPmZ_B
|
|
16914560U, // UQRSHL_ZPmZ_D
|
|
25832584U, // UQRSHL_ZPmZ_H
|
|
33697920U, // UQRSHL_ZPmZ_S
|
|
794768U, // UQRSHLv16i8
|
|
3160U, // UQRSHLv1i16
|
|
3160U, // UQRSHLv1i32
|
|
3160U, // UQRSHLv1i64
|
|
3160U, // UQRSHLv1i8
|
|
925848U, // UQRSHLv2i32
|
|
270440U, // UQRSHLv2i64
|
|
1056928U, // UQRSHLv4i16
|
|
401520U, // UQRSHLv4i32
|
|
532600U, // UQRSHLv8i16
|
|
1188008U, // UQRSHLv8i8
|
|
3160U, // UQRSHRNB_ZZI_B
|
|
200U, // UQRSHRNB_ZZI_H
|
|
3160U, // UQRSHRNB_ZZI_S
|
|
37976U, // UQRSHRNT_ZZI_B
|
|
320U, // UQRSHRNT_ZZI_H
|
|
37976U, // UQRSHRNT_ZZI_S
|
|
3160U, // UQRSHRNb
|
|
3160U, // UQRSHRNh
|
|
3160U, // UQRSHRNs
|
|
38008U, // UQRSHRNv16i8_shift
|
|
3176U, // UQRSHRNv2i32_shift
|
|
3184U, // UQRSHRNv4i16_shift
|
|
37992U, // UQRSHRNv4i32_shift
|
|
38000U, // UQRSHRNv8i16_shift
|
|
3192U, // UQRSHRNv8i8_shift
|
|
8530048U, // UQSHLR_ZPmZ_B
|
|
16914560U, // UQSHLR_ZPmZ_D
|
|
25832584U, // UQSHLR_ZPmZ_H
|
|
33697920U, // UQSHLR_ZPmZ_S
|
|
141440U, // UQSHL_ZPmI_B
|
|
137344U, // UQSHL_ZPmI_D
|
|
1453192U, // UQSHL_ZPmI_H
|
|
143488U, // UQSHL_ZPmI_S
|
|
8530048U, // UQSHL_ZPmZ_B
|
|
16914560U, // UQSHL_ZPmZ_D
|
|
25832584U, // UQSHL_ZPmZ_H
|
|
33697920U, // UQSHL_ZPmZ_S
|
|
3160U, // UQSHLb
|
|
3160U, // UQSHLd
|
|
3160U, // UQSHLh
|
|
3160U, // UQSHLs
|
|
794768U, // UQSHLv16i8
|
|
3216U, // UQSHLv16i8_shift
|
|
3160U, // UQSHLv1i16
|
|
3160U, // UQSHLv1i32
|
|
3160U, // UQSHLv1i64
|
|
3160U, // UQSHLv1i8
|
|
925848U, // UQSHLv2i32
|
|
3224U, // UQSHLv2i32_shift
|
|
270440U, // UQSHLv2i64
|
|
3176U, // UQSHLv2i64_shift
|
|
1056928U, // UQSHLv4i16
|
|
3232U, // UQSHLv4i16_shift
|
|
401520U, // UQSHLv4i32
|
|
3184U, // UQSHLv4i32_shift
|
|
532600U, // UQSHLv8i16
|
|
3192U, // UQSHLv8i16_shift
|
|
1188008U, // UQSHLv8i8
|
|
3240U, // UQSHLv8i8_shift
|
|
3160U, // UQSHRNB_ZZI_B
|
|
200U, // UQSHRNB_ZZI_H
|
|
3160U, // UQSHRNB_ZZI_S
|
|
37976U, // UQSHRNT_ZZI_B
|
|
320U, // UQSHRNT_ZZI_H
|
|
37976U, // UQSHRNT_ZZI_S
|
|
3160U, // UQSHRNb
|
|
3160U, // UQSHRNh
|
|
3160U, // UQSHRNs
|
|
38008U, // UQSHRNv16i8_shift
|
|
3176U, // UQSHRNv2i32_shift
|
|
3184U, // UQSHRNv4i16_shift
|
|
37992U, // UQSHRNv4i32_shift
|
|
38000U, // UQSHRNv8i16_shift
|
|
3192U, // UQSHRNv8i8_shift
|
|
8530048U, // UQSUBR_ZPmZ_B
|
|
16914560U, // UQSUBR_ZPmZ_D
|
|
25832584U, // UQSUBR_ZPmZ_H
|
|
33697920U, // UQSUBR_ZPmZ_S
|
|
16472U, // UQSUB_ZI_B
|
|
17496U, // UQSUB_ZI_D
|
|
176U, // UQSUB_ZI_H
|
|
18520U, // UQSUB_ZI_S
|
|
8530048U, // UQSUB_ZPmZ_B
|
|
16914560U, // UQSUB_ZPmZ_D
|
|
25832584U, // UQSUB_ZPmZ_H
|
|
33697920U, // UQSUB_ZPmZ_S
|
|
10328U, // UQSUB_ZZZ_B
|
|
6232U, // UQSUB_ZZZ_D
|
|
136U, // UQSUB_ZZZ_H
|
|
12376U, // UQSUB_ZZZ_S
|
|
794768U, // UQSUBv16i8
|
|
3160U, // UQSUBv1i16
|
|
3160U, // UQSUBv1i32
|
|
3160U, // UQSUBv1i64
|
|
3160U, // UQSUBv1i8
|
|
925848U, // UQSUBv2i32
|
|
270440U, // UQSUBv2i64
|
|
1056928U, // UQSUBv4i16
|
|
401520U, // UQSUBv4i32
|
|
532600U, // UQSUBv8i16
|
|
1188008U, // UQSUBv8i8
|
|
32U, // UQXTNB_ZZ_B
|
|
0U, // UQXTNB_ZZ_H
|
|
32U, // UQXTNB_ZZ_S
|
|
32U, // UQXTNT_ZZ_B
|
|
0U, // UQXTNT_ZZ_H
|
|
32U, // UQXTNT_ZZ_S
|
|
72U, // UQXTNv16i8
|
|
32U, // UQXTNv1i16
|
|
32U, // UQXTNv1i32
|
|
32U, // UQXTNv1i8
|
|
48U, // UQXTNv2i32
|
|
64U, // UQXTNv4i16
|
|
48U, // UQXTNv4i32
|
|
64U, // UQXTNv8i16
|
|
72U, // UQXTNv8i8
|
|
16U, // URECPE_ZPmZ_S
|
|
40U, // URECPEv2i32
|
|
64U, // URECPEv4i32
|
|
8530048U, // URHADD_ZPmZ_B
|
|
16914560U, // URHADD_ZPmZ_D
|
|
25832584U, // URHADD_ZPmZ_H
|
|
33697920U, // URHADD_ZPmZ_S
|
|
794768U, // URHADDv16i8
|
|
925848U, // URHADDv2i32
|
|
1056928U, // URHADDv4i16
|
|
401520U, // URHADDv4i32
|
|
532600U, // URHADDv8i16
|
|
1188008U, // URHADDv8i8
|
|
8530048U, // URSHLR_ZPmZ_B
|
|
16914560U, // URSHLR_ZPmZ_D
|
|
25832584U, // URSHLR_ZPmZ_H
|
|
33697920U, // URSHLR_ZPmZ_S
|
|
8530048U, // URSHL_ZPmZ_B
|
|
16914560U, // URSHL_ZPmZ_D
|
|
25832584U, // URSHL_ZPmZ_H
|
|
33697920U, // URSHL_ZPmZ_S
|
|
794768U, // URSHLv16i8
|
|
3160U, // URSHLv1i64
|
|
925848U, // URSHLv2i32
|
|
270440U, // URSHLv2i64
|
|
1056928U, // URSHLv4i16
|
|
401520U, // URSHLv4i32
|
|
532600U, // URSHLv8i16
|
|
1188008U, // URSHLv8i8
|
|
141440U, // URSHR_ZPmI_B
|
|
137344U, // URSHR_ZPmI_D
|
|
1453192U, // URSHR_ZPmI_H
|
|
143488U, // URSHR_ZPmI_S
|
|
3160U, // URSHRd
|
|
3216U, // URSHRv16i8_shift
|
|
3224U, // URSHRv2i32_shift
|
|
3176U, // URSHRv2i64_shift
|
|
3232U, // URSHRv4i16_shift
|
|
3184U, // URSHRv4i32_shift
|
|
3192U, // URSHRv8i16_shift
|
|
3240U, // URSHRv8i8_shift
|
|
16U, // URSQRTE_ZPmZ_S
|
|
40U, // URSQRTEv2i32
|
|
64U, // URSQRTEv4i32
|
|
321U, // URSRA_ZZI_B
|
|
37976U, // URSRA_ZZI_D
|
|
320U, // URSRA_ZZI_H
|
|
37976U, // URSRA_ZZI_S
|
|
37977U, // URSRAd
|
|
38032U, // URSRAv16i8_shift
|
|
38040U, // URSRAv2i32_shift
|
|
37992U, // URSRAv2i64_shift
|
|
38048U, // URSRAv4i16_shift
|
|
38000U, // URSRAv4i32_shift
|
|
38008U, // URSRAv8i16_shift
|
|
38056U, // URSRAv8i8_shift
|
|
1U, // USDOT_ZZZ
|
|
38913U, // USDOT_ZZZI
|
|
5121168U, // USDOTlanev16i8
|
|
5121192U, // USDOTlanev8i8
|
|
795792U, // USDOTv16i8
|
|
1189032U, // USDOTv8i8
|
|
3160U, // USHLLB_ZZI_D
|
|
200U, // USHLLB_ZZI_H
|
|
3160U, // USHLLB_ZZI_S
|
|
3160U, // USHLLT_ZZI_D
|
|
200U, // USHLLT_ZZI_H
|
|
3160U, // USHLLT_ZZI_S
|
|
3216U, // USHLLv16i8_shift
|
|
3224U, // USHLLv2i32_shift
|
|
3232U, // USHLLv4i16_shift
|
|
3184U, // USHLLv4i32_shift
|
|
3192U, // USHLLv8i16_shift
|
|
3240U, // USHLLv8i8_shift
|
|
794768U, // USHLv16i8
|
|
3160U, // USHLv1i64
|
|
925848U, // USHLv2i32
|
|
270440U, // USHLv2i64
|
|
1056928U, // USHLv4i16
|
|
401520U, // USHLv4i32
|
|
532600U, // USHLv8i16
|
|
1188008U, // USHLv8i8
|
|
3160U, // USHRd
|
|
3216U, // USHRv16i8_shift
|
|
3224U, // USHRv2i32_shift
|
|
3176U, // USHRv2i64_shift
|
|
3232U, // USHRv4i16_shift
|
|
3184U, // USHRv4i32_shift
|
|
3192U, // USHRv8i16_shift
|
|
3240U, // USHRv8i8_shift
|
|
795792U, // USMMLA
|
|
1U, // USMMLA_ZZZ
|
|
0U, // USMOPA_MPPZZ_D
|
|
0U, // USMOPA_MPPZZ_S
|
|
0U, // USMOPS_MPPZZ_D
|
|
0U, // USMOPS_MPPZZ_S
|
|
8530048U, // USQADD_ZPmZ_B
|
|
16914560U, // USQADD_ZPmZ_D
|
|
25832584U, // USQADD_ZPmZ_H
|
|
33697920U, // USQADD_ZPmZ_S
|
|
24U, // USQADDv16i8
|
|
33U, // USQADDv1i16
|
|
33U, // USQADDv1i32
|
|
33U, // USQADDv1i64
|
|
33U, // USQADDv1i8
|
|
40U, // USQADDv2i32
|
|
48U, // USQADDv2i64
|
|
56U, // USQADDv4i16
|
|
64U, // USQADDv4i32
|
|
72U, // USQADDv8i16
|
|
80U, // USQADDv8i8
|
|
321U, // USRA_ZZI_B
|
|
37976U, // USRA_ZZI_D
|
|
320U, // USRA_ZZI_H
|
|
37976U, // USRA_ZZI_S
|
|
37977U, // USRAd
|
|
38032U, // USRAv16i8_shift
|
|
38040U, // USRAv2i32_shift
|
|
37992U, // USRAv2i64_shift
|
|
38048U, // USRAv4i16_shift
|
|
38000U, // USRAv4i32_shift
|
|
38008U, // USRAv8i16_shift
|
|
38056U, // USRAv8i8_shift
|
|
12376U, // USUBLB_ZZZ_D
|
|
592U, // USUBLB_ZZZ_H
|
|
5208U, // USUBLB_ZZZ_S
|
|
12376U, // USUBLT_ZZZ_D
|
|
592U, // USUBLT_ZZZ_H
|
|
5208U, // USUBLT_ZZZ_S
|
|
794768U, // USUBLv16i8_v8i16
|
|
925848U, // USUBLv2i32_v2i64
|
|
1056928U, // USUBLv4i16_v4i32
|
|
401520U, // USUBLv4i32_v2i64
|
|
532600U, // USUBLv8i16_v4i32
|
|
1188008U, // USUBLv8i8_v8i16
|
|
12376U, // USUBWB_ZZZ_D
|
|
592U, // USUBWB_ZZZ_H
|
|
5208U, // USUBWB_ZZZ_S
|
|
12376U, // USUBWT_ZZZ_D
|
|
592U, // USUBWT_ZZZ_H
|
|
5208U, // USUBWT_ZZZ_S
|
|
794744U, // USUBWv16i8_v8i16
|
|
925800U, // USUBWv2i32_v2i64
|
|
1056880U, // USUBWv4i16_v4i32
|
|
401512U, // USUBWv4i32_v2i64
|
|
532592U, // USUBWv8i16_v4i32
|
|
1187960U, // USUBWv8i8_v8i16
|
|
32U, // UUNPKHI_ZZ_D
|
|
0U, // UUNPKHI_ZZ_H
|
|
32U, // UUNPKHI_ZZ_S
|
|
32U, // UUNPKLO_ZZ_D
|
|
0U, // UUNPKLO_ZZ_H
|
|
32U, // UUNPKLO_ZZ_S
|
|
8U, // UXTB_ZPmZ_D
|
|
0U, // UXTB_ZPmZ_H
|
|
16U, // UXTB_ZPmZ_S
|
|
8U, // UXTH_ZPmZ_D
|
|
16U, // UXTH_ZPmZ_S
|
|
8U, // UXTW_ZPmZ_D
|
|
10328U, // UZP1_PPP_B
|
|
6232U, // UZP1_PPP_D
|
|
136U, // UZP1_PPP_H
|
|
12376U, // UZP1_PPP_S
|
|
10328U, // UZP1_ZZZ_B
|
|
6232U, // UZP1_ZZZ_D
|
|
136U, // UZP1_ZZZ_H
|
|
880U, // UZP1_ZZZ_Q
|
|
12376U, // UZP1_ZZZ_S
|
|
794768U, // UZP1v16i8
|
|
925848U, // UZP1v2i32
|
|
270440U, // UZP1v2i64
|
|
1056928U, // UZP1v4i16
|
|
401520U, // UZP1v4i32
|
|
532600U, // UZP1v8i16
|
|
1188008U, // UZP1v8i8
|
|
10328U, // UZP2_PPP_B
|
|
6232U, // UZP2_PPP_D
|
|
136U, // UZP2_PPP_H
|
|
12376U, // UZP2_PPP_S
|
|
10328U, // UZP2_ZZZ_B
|
|
6232U, // UZP2_ZZZ_D
|
|
136U, // UZP2_ZZZ_H
|
|
880U, // UZP2_ZZZ_Q
|
|
12376U, // UZP2_ZZZ_S
|
|
794768U, // UZP2v16i8
|
|
925848U, // UZP2v2i32
|
|
270440U, // UZP2v2i64
|
|
1056928U, // UZP2v4i16
|
|
401520U, // UZP2v4i32
|
|
532600U, // UZP2v8i16
|
|
1188008U, // UZP2v8i8
|
|
0U, // WFET
|
|
0U, // WFIT
|
|
3160U, // WHILEGE_PWW_B
|
|
3160U, // WHILEGE_PWW_D
|
|
200U, // WHILEGE_PWW_H
|
|
3160U, // WHILEGE_PWW_S
|
|
3160U, // WHILEGE_PXX_B
|
|
3160U, // WHILEGE_PXX_D
|
|
200U, // WHILEGE_PXX_H
|
|
3160U, // WHILEGE_PXX_S
|
|
3160U, // WHILEGT_PWW_B
|
|
3160U, // WHILEGT_PWW_D
|
|
200U, // WHILEGT_PWW_H
|
|
3160U, // WHILEGT_PWW_S
|
|
3160U, // WHILEGT_PXX_B
|
|
3160U, // WHILEGT_PXX_D
|
|
200U, // WHILEGT_PXX_H
|
|
3160U, // WHILEGT_PXX_S
|
|
3160U, // WHILEHI_PWW_B
|
|
3160U, // WHILEHI_PWW_D
|
|
200U, // WHILEHI_PWW_H
|
|
3160U, // WHILEHI_PWW_S
|
|
3160U, // WHILEHI_PXX_B
|
|
3160U, // WHILEHI_PXX_D
|
|
200U, // WHILEHI_PXX_H
|
|
3160U, // WHILEHI_PXX_S
|
|
3160U, // WHILEHS_PWW_B
|
|
3160U, // WHILEHS_PWW_D
|
|
200U, // WHILEHS_PWW_H
|
|
3160U, // WHILEHS_PWW_S
|
|
3160U, // WHILEHS_PXX_B
|
|
3160U, // WHILEHS_PXX_D
|
|
200U, // WHILEHS_PXX_H
|
|
3160U, // WHILEHS_PXX_S
|
|
3160U, // WHILELE_PWW_B
|
|
3160U, // WHILELE_PWW_D
|
|
200U, // WHILELE_PWW_H
|
|
3160U, // WHILELE_PWW_S
|
|
3160U, // WHILELE_PXX_B
|
|
3160U, // WHILELE_PXX_D
|
|
200U, // WHILELE_PXX_H
|
|
3160U, // WHILELE_PXX_S
|
|
3160U, // WHILELO_PWW_B
|
|
3160U, // WHILELO_PWW_D
|
|
200U, // WHILELO_PWW_H
|
|
3160U, // WHILELO_PWW_S
|
|
3160U, // WHILELO_PXX_B
|
|
3160U, // WHILELO_PXX_D
|
|
200U, // WHILELO_PXX_H
|
|
3160U, // WHILELO_PXX_S
|
|
3160U, // WHILELS_PWW_B
|
|
3160U, // WHILELS_PWW_D
|
|
200U, // WHILELS_PWW_H
|
|
3160U, // WHILELS_PWW_S
|
|
3160U, // WHILELS_PXX_B
|
|
3160U, // WHILELS_PXX_D
|
|
200U, // WHILELS_PXX_H
|
|
3160U, // WHILELS_PXX_S
|
|
3160U, // WHILELT_PWW_B
|
|
3160U, // WHILELT_PWW_D
|
|
200U, // WHILELT_PWW_H
|
|
3160U, // WHILELT_PWW_S
|
|
3160U, // WHILELT_PXX_B
|
|
3160U, // WHILELT_PXX_D
|
|
200U, // WHILELT_PXX_H
|
|
3160U, // WHILELT_PXX_S
|
|
3160U, // WHILERW_PXX_B
|
|
3160U, // WHILERW_PXX_D
|
|
200U, // WHILERW_PXX_H
|
|
3160U, // WHILERW_PXX_S
|
|
3160U, // WHILEWR_PXX_B
|
|
3160U, // WHILEWR_PXX_D
|
|
200U, // WHILEWR_PXX_H
|
|
3160U, // WHILEWR_PXX_S
|
|
0U, // WRFFR
|
|
0U, // XAFLAG
|
|
3154024U, // XAR
|
|
141400U, // XAR_ZZZI_B
|
|
137304U, // XAR_ZZZI_D
|
|
1453192U, // XAR_ZZZI_H
|
|
143448U, // XAR_ZZZI_S
|
|
0U, // XPACD
|
|
0U, // XPACI
|
|
0U, // XPACLRI
|
|
72U, // XTNv16i8
|
|
48U, // XTNv2i32
|
|
64U, // XTNv4i16
|
|
48U, // XTNv4i32
|
|
64U, // XTNv8i16
|
|
72U, // XTNv8i8
|
|
0U, // ZERO_M
|
|
10328U, // ZIP1_PPP_B
|
|
6232U, // ZIP1_PPP_D
|
|
136U, // ZIP1_PPP_H
|
|
12376U, // ZIP1_PPP_S
|
|
10328U, // ZIP1_ZZZ_B
|
|
6232U, // ZIP1_ZZZ_D
|
|
136U, // ZIP1_ZZZ_H
|
|
880U, // ZIP1_ZZZ_Q
|
|
12376U, // ZIP1_ZZZ_S
|
|
794768U, // ZIP1v16i8
|
|
925848U, // ZIP1v2i32
|
|
270440U, // ZIP1v2i64
|
|
1056928U, // ZIP1v4i16
|
|
401520U, // ZIP1v4i32
|
|
532600U, // ZIP1v8i16
|
|
1188008U, // ZIP1v8i8
|
|
10328U, // ZIP2_PPP_B
|
|
6232U, // ZIP2_PPP_D
|
|
136U, // ZIP2_PPP_H
|
|
12376U, // ZIP2_PPP_S
|
|
10328U, // ZIP2_ZZZ_B
|
|
6232U, // ZIP2_ZZZ_D
|
|
136U, // ZIP2_ZZZ_H
|
|
880U, // ZIP2_ZZZ_Q
|
|
12376U, // ZIP2_ZZZ_S
|
|
794768U, // ZIP2v16i8
|
|
925848U, // ZIP2v2i32
|
|
270440U, // ZIP2v2i64
|
|
1056928U, // ZIP2v4i16
|
|
401520U, // ZIP2v4i32
|
|
532600U, // ZIP2v8i16
|
|
1188008U, // ZIP2v8i8
|
|
0U, // anonymous_13987
|
|
0U, // anonymous_13988
|
|
0U, // anonymous_5384
|
|
0U, // anonymous_5385
|
|
};
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits = 0;
|
|
Bits |= (uint64_t)OpInfo0[opcode] << 0;
|
|
Bits |= (uint64_t)OpInfo1[opcode] << 32;
|
|
#ifndef CAPSTONE_DIET
|
|
SStream_concat0(O, AsmStrs+(Bits & 16383)-1);
|
|
#endif
|
|
return Bits;
|
|
|
|
}
|
|
/// printInstruction - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
static void printInstruction(MCInst *MI, SStream *O)
|
|
{
|
|
unsigned int opcode = MCInst_getOpcode(MI);
|
|
// printf("opcode = %u\n", opcode);
|
|
|
|
|
|
|
|
uint64_t Bits = getMnemonic(MI, O, opcode);
|
|
|
|
// Fragment 0 encoded into 7 bits for 68 unique commands.
|
|
// printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 127));
|
|
switch ((Bits >> 14) & 127) {
|
|
default: // unreachable
|
|
case 0:
|
|
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// TLSDESCCALL, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm...
|
|
printSVERegOp(MI, 0, O, 'b');
|
|
break;
|
|
case 3:
|
|
// ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_...
|
|
printSVERegOp(MI, 0, O, 'd');
|
|
break;
|
|
case 4:
|
|
// ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm...
|
|
printSVERegOp(MI, 0, O, 'h');
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 5:
|
|
// ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP...
|
|
printSVERegOp(MI, 0, O, 's');
|
|
break;
|
|
case 6:
|
|
// ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
|
|
printVRegOperand(MI, 0, O);
|
|
break;
|
|
case 7:
|
|
// ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, FMOPA_MPPZZ_D,...
|
|
printMatrixTile(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, "/m, ");
|
|
printSVERegOp(MI, 2, O, 0);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 8:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 9:
|
|
// ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ...
|
|
printZPRasFPR(MI, 0, O, 8);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 2, O, 'b');
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV...
|
|
printZPRasFPR(MI, 0, O, 64);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 11:
|
|
// ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV...
|
|
printZPRasFPR(MI, 0, O, 16);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV...
|
|
printZPRasFPR(MI, 0, O, 32);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 13:
|
|
// AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 14:
|
|
// B, BL
|
|
printAlignedLabel(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// BCcc, Bcc
|
|
printCondCode(MI, 0, O);
|
|
SStream_concat0(O, "\t");
|
|
printAlignedLabel(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
|
|
printImmHex(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// CASPALW, CASPAW, CASPLW, CASPW
|
|
printGPRSeqPairsClassOperand(MI, 1, O, 32);
|
|
SStream_concat0(O, ", ");
|
|
printGPRSeqPairsClassOperand(MI, 2, O, 32);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// CASPALX, CASPAX, CASPLX, CASPX
|
|
printGPRSeqPairsClassOperand(MI, 1, O, 64);
|
|
SStream_concat0(O, ", ");
|
|
printGPRSeqPairsClassOperand(MI, 2, O, 64);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET...
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "]!, [");
|
|
set_mem_access(MI, false);
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "]!, ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 5, O);
|
|
SStream_concat0(O, "!");
|
|
return;
|
|
break;
|
|
case 20:
|
|
// DMB, DSB, ISB, TSB
|
|
printBarrierOption(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// DSBnXS
|
|
printBarriernXSOption(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, PMULLB_ZZZ_Q, PMULLT_...
|
|
printSVERegOp(MI, 0, O, 'q');
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 23:
|
|
// GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
|
|
printTypedVectorList(MI, 0, O, 0,'d');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 24:
|
|
// GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE...
|
|
printTypedVectorList(MI, 0, O, 0,'s');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 25:
|
|
// HINT
|
|
printImm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
printMatrixTileVector(MI, 0, O, 0);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 2, O);
|
|
break;
|
|
case 27:
|
|
// INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q...
|
|
printMatrixTileVector(MI, 0, O, 1);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 2, O);
|
|
break;
|
|
case 28:
|
|
// LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RO_B, LD1RO_B_IMM, LD1RQ_B, LD1RQ_B...
|
|
printTypedVectorList(MI, 0, O, 0,'b');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 29:
|
|
// LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ...
|
|
printTypedVectorList(MI, 0, O, 0,'h');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 30:
|
|
// LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,...
|
|
printTypedVectorList(MI, 0, O, 16, 'b');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L...
|
|
printTypedVectorList(MI, 1, O, 16, 'b');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 32:
|
|
// LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv...
|
|
printTypedVectorList(MI, 0, O, 1, 'd');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 1, 'd');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 34:
|
|
// LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 2, 'd');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 2, 'd');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 36:
|
|
// LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 2, 's');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 2, 's');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 38:
|
|
// LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 4, 'h');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 4, 'h');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 40:
|
|
// LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 4, 's');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 41:
|
|
// LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 4, 's');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 42:
|
|
// LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 8, 'b');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 8, 'b');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 44:
|
|
// LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw...
|
|
printTypedVectorList(MI, 0, O, 8, 'h');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw...
|
|
printTypedVectorList(MI, 1, O, 8, 'h');
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 46:
|
|
// LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,...
|
|
printTypedVectorList(MI, 1, O, 0, 'h');
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 47:
|
|
// LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST
|
|
printTypedVectorList(MI, 2, O, 0, 'h');
|
|
printVectorIndex(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 48:
|
|
// LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,...
|
|
printTypedVectorList(MI, 1, O, 0, 's');
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 49:
|
|
// LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST
|
|
printTypedVectorList(MI, 2, O, 0, 's');
|
|
printVectorIndex(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 50:
|
|
// LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,...
|
|
printTypedVectorList(MI, 1, O, 0, 'd');
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 51:
|
|
// LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST
|
|
printTypedVectorList(MI, 2, O, 0, 'd');
|
|
printVectorIndex(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 52:
|
|
// LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_...
|
|
printTypedVectorList(MI, 1, O, 0, 'b');
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 53:
|
|
// LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST
|
|
printTypedVectorList(MI, 2, O, 0, 'b');
|
|
printVectorIndex(MI, 3, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 54:
|
|
// LD64B, ST64B
|
|
printGPR64x8(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H...
|
|
printSVERegOp(MI, 0, O, 0);
|
|
break;
|
|
case 56:
|
|
// LDR_ZA, STR_ZA
|
|
printMatrix(MI, 0, O, 0);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 2, O);
|
|
SStream_concat0(O, "], [");
|
|
set_mem_access(MI, false);
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", mul vl]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE...
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]!, ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "!, ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// MSR
|
|
printMSRSystemRegister(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 59:
|
|
// MSRpstateImm1, MSRpstateImm4
|
|
printSystemPStateField(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// MSRpstatesvcrImm1
|
|
printSVCROp(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 61:
|
|
// PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF...
|
|
printPrefetchOp(MI, 0, O, true);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 1, O, 0);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 62:
|
|
// PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi
|
|
printPrefetchOp(MI, 0, O, false);
|
|
break;
|
|
case 63:
|
|
// ST1i16, ST2i16, ST3i16, ST4i16
|
|
printTypedVectorList(MI, 0, O, 0, 'h');
|
|
printVectorIndex(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// ST1i32, ST2i32, ST3i32, ST4i32
|
|
printTypedVectorList(MI, 0, O, 0, 's');
|
|
printVectorIndex(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 65:
|
|
// ST1i64, ST2i64, ST3i64, ST4i64
|
|
printTypedVectorList(MI, 0, O, 0, 'd');
|
|
printVectorIndex(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 66:
|
|
// ST1i8, ST2i8, ST3i8, ST4i8
|
|
printTypedVectorList(MI, 0, O, 0, 'b');
|
|
printVectorIndex(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// ZERO_M
|
|
printMatrixTileList(MI, 0, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 7 bits for 69 unique commands.
|
|
// printf("Fragment 1: %"PRIu64"\n", ((Bits >> 21) & 127));
|
|
switch ((Bits >> 21) & 127) {
|
|
default: // unreachable
|
|
case 0:
|
|
// TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCLB_ZZZ_D, ADCLB_ZZZ_S...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm...
|
|
printSVERegOp(MI, 2, O, 0);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 3:
|
|
// ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM...
|
|
SStream_concat0(O, ".16b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
break;
|
|
case 4:
|
|
// ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF...
|
|
SStream_concat0(O, ".2s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
break;
|
|
case 5:
|
|
// ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE...
|
|
SStream_concat0(O, ".2d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
break;
|
|
case 6:
|
|
// ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS...
|
|
SStream_concat0(O, ".4h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
break;
|
|
case 7:
|
|
// ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BF16DOTlanev8bf16, BF...
|
|
SStream_concat0(O, ".4s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
break;
|
|
case 8:
|
|
// ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BFCVTN2, BICv8i16, CL...
|
|
SStream_concat0(O, ".8h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
break;
|
|
case 9:
|
|
// ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8...
|
|
SStream_concat0(O, ".8b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
break;
|
|
case 10:
|
|
// ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
break;
|
|
case 11:
|
|
// ADDHA_MPPZ_S, ADDVA_MPPZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S
|
|
printSVERegOp(MI, 3, O, 's');
|
|
break;
|
|
case 12:
|
|
// ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,...
|
|
printSVERegOp(MI, 1, O, 's');
|
|
break;
|
|
case 13:
|
|
// ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAX...
|
|
printSVERegOp(MI, 2, O, 's');
|
|
break;
|
|
case 14:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 15:
|
|
// ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H...
|
|
printSVERegOp(MI, 1, O, 'h');
|
|
break;
|
|
case 16:
|
|
// ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD...
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 17:
|
|
// ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV_VPZ_D, FMINN...
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
break;
|
|
case 18:
|
|
// ANDV_VPZ_H, CMLA_ZZZI_H, CMLA_ZZZ_H, DECP_ZP_H, EORBT_ZZZ_H, EORTB_ZZZ...
|
|
printSVERegOp(MI, 2, O, 'h');
|
|
break;
|
|
case 19:
|
|
// DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP...
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// DUP_ZI_H
|
|
printImm8OptLsl32(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, WHILEGE_PWW_H, WHILEGE_PXX_H, WHILEG...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 22:
|
|
// DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q,...
|
|
printSVERegOp(MI, 1, O, 'q');
|
|
break;
|
|
case 23:
|
|
// FADDA_VPZ_D
|
|
printZPRasFPR(MI, 2, O, 64);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
return;
|
|
break;
|
|
case 24:
|
|
// FADDA_VPZ_H, INSR_ZV_H
|
|
printZPRasFPR(MI, 2, O, 16);
|
|
break;
|
|
case 25:
|
|
// FADDA_VPZ_S
|
|
printZPRasFPR(MI, 2, O, 32);
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 3, O, 's');
|
|
return;
|
|
break;
|
|
case 26:
|
|
// FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri
|
|
SStream_concat0(O, ", #0.0");
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// FDUP_ZI_H
|
|
printFPImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// FMOVXDHighr, INSvi64gpr, INSvi64lane
|
|
SStream_concat0(O, ".d");
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 29:
|
|
// GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
|
|
SStream_concat0(O, "/z, [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 30:
|
|
// INDEX_II_H, INDEX_IR_H
|
|
printSImm(MI, 1, O, 16);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 31:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 32:
|
|
// INSR_ZR_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRFB...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 33:
|
|
// INSvi16gpr, INSvi16lane
|
|
SStream_concat0(O, ".h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 34:
|
|
// INSvi32gpr, INSvi32lane
|
|
SStream_concat0(O, ".s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 35:
|
|
// INSvi8gpr, INSvi8lane
|
|
SStream_concat0(O, ".b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B);
|
|
printVectorIndex(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 36:
|
|
// LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L...
|
|
printPostIncOperand(MI, 3, O, 64);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD...
|
|
printPostIncOperand(MI, 3, O, 32);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw...
|
|
printPostIncOperand(MI, 3, O, 16);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1...
|
|
printPostIncOperand(MI, 3, O, 8);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// LD1Rv16b_POST, LD1Rv8b_POST
|
|
printPostIncOperand(MI, 3, O, 1);
|
|
return;
|
|
break;
|
|
case 41:
|
|
// LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,...
|
|
printPostIncOperand(MI, 3, O, 4);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST
|
|
printPostIncOperand(MI, 3, O, 2);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS...
|
|
printPostIncOperand(MI, 3, O, 48);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST...
|
|
printPostIncOperand(MI, 3, O, 24);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX...
|
|
SStream_concat0(O, "]}, ");
|
|
set_mem_access(MI, false);
|
|
printSVERegOp(MI, 3, O, 0);
|
|
break;
|
|
case 46:
|
|
// LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ...
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// LD1i16_POST, LD2i8_POST
|
|
printPostIncOperand(MI, 5, O, 2);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// LD1i32_POST, LD2i16_POST, LD4i8_POST
|
|
printPostIncOperand(MI, 5, O, 4);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// LD1i64_POST, LD2i32_POST, LD4i16_POST
|
|
printPostIncOperand(MI, 5, O, 8);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// LD1i8_POST
|
|
printPostIncOperand(MI, 5, O, 1);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// LD2i64_POST, LD4i32_POST
|
|
printPostIncOperand(MI, 5, O, 16);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// LD3Rv16b_POST, LD3Rv8b_POST
|
|
printPostIncOperand(MI, 3, O, 3);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// LD3Rv2s_POST, LD3Rv4s_POST
|
|
printPostIncOperand(MI, 3, O, 12);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// LD3Rv4h_POST, LD3Rv8h_POST
|
|
printPostIncOperand(MI, 3, O, 6);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// LD3i16_POST
|
|
printPostIncOperand(MI, 5, O, 6);
|
|
return;
|
|
break;
|
|
case 56:
|
|
// LD3i32_POST
|
|
printPostIncOperand(MI, 5, O, 12);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// LD3i64_POST
|
|
printPostIncOperand(MI, 5, O, 24);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// LD3i8_POST
|
|
printPostIncOperand(MI, 5, O, 3);
|
|
return;
|
|
break;
|
|
case 59:
|
|
// LD4i64_POST
|
|
printPostIncOperand(MI, 5, O, 32);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD...
|
|
printSVERegOp(MI, 1, O, 'b');
|
|
break;
|
|
case 61:
|
|
// PMULLB_ZZZ_Q, PMULLT_ZZZ_Q
|
|
printSVERegOp(MI, 1, O, 'd');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
return;
|
|
break;
|
|
case 62:
|
|
// PMULLv1i64, PMULLv2i64
|
|
SStream_concat0(O, ".1q, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q);
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 63:
|
|
// PTRUES_H, PTRUE_H
|
|
printSVEPattern(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// SABALB_ZZZ_H, SABALT_ZZZ_H, SADDV_VPZ_B, SMLALB_ZZZ_H, SMLALT_ZZZ_H, S...
|
|
printSVERegOp(MI, 2, O, 'b');
|
|
break;
|
|
case 65:
|
|
// SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v...
|
|
SStream_concat0(O, ".1d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
|
|
break;
|
|
case 66:
|
|
// SMOPA_MPPZZ_D, SMOPS_MPPZZ_D, SUMOPA_MPPZZ_D, SUMOPS_MPPZZ_D, UMOPA_MP...
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 4, O, 'h');
|
|
return;
|
|
break;
|
|
case 67:
|
|
// SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMOPA_MPPZZ_S, SUMOPS_MPPZZ_S, UMOPA_MP...
|
|
printSVERegOp(MI, 3, O, 'b');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 4, O, 'b');
|
|
return;
|
|
break;
|
|
case 68:
|
|
// TBL_ZZZZ_H, TBL_ZZZ_H
|
|
printTypedVectorList(MI, 1, O, 0,'h');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 2, O, 'h');
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 7 bits for 69 unique commands.
|
|
// printf("Fragment 2: %"PRIu64"\n", ((Bits >> 28) & 127));
|
|
switch ((Bits >> 28) & 127) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ...
|
|
printSVERegOp(MI, 2, O, 0);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 1:
|
|
// ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ...
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
|
|
printVRegOperand(MI, 1, O);
|
|
break;
|
|
case 3:
|
|
// ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDSWri, ADDS...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 4:
|
|
// ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z...
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
break;
|
|
case 5:
|
|
// ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ...
|
|
printSVERegOp(MI, 2, O, 's');
|
|
break;
|
|
case 6:
|
|
// ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, ANDV_VPZ_D, AN...
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH...
|
|
printSVERegOp(MI, 1, O, 'h');
|
|
break;
|
|
case 8:
|
|
// ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 9:
|
|
// ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A...
|
|
printSVERegOp(MI, 1, O, 'd');
|
|
break;
|
|
case 10:
|
|
// ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
|
|
printSVERegOp(MI, 2, O, 'h');
|
|
break;
|
|
case 11:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 12:
|
|
// ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
|
|
printSVERegOp(MI, 1, O, 0);
|
|
break;
|
|
case 13:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 14:
|
|
// ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ...
|
|
printSVERegOp(MI, 1, O, 'b');
|
|
break;
|
|
case 15:
|
|
// ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2...
|
|
printSVERegOp(MI, 1, O, 's');
|
|
break;
|
|
case 16:
|
|
// ADRP
|
|
printAdrpLabel(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 18:
|
|
// BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, SCVTF_ZPmZ...
|
|
printSVERegOp(MI, 3, O, 's');
|
|
return;
|
|
break;
|
|
case 19:
|
|
// BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv...
|
|
printImm(MI, 2, O);
|
|
printShifter(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P...
|
|
printAlignedLabel(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ...
|
|
printSVERegOp(MI, 2, O, 'b');
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 22:
|
|
// CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE...
|
|
SStream_concat0(O, "/z, ");
|
|
break;
|
|
case 23:
|
|
// CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES...
|
|
printSVEPattern(MI, 1, O);
|
|
break;
|
|
case 24:
|
|
// CPY_ZPmI_H
|
|
printImm8OptLsl32(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB...
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// DUPM_ZI
|
|
printLogicalImm64(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// DUP_ZI_B
|
|
printImm8OptLsl32(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// DUP_ZI_D
|
|
printImm8OptLsl64(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// DUP_ZI_S
|
|
printImm8OptLsl32(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// DUP_ZZI_H, DUP_ZZI_Q
|
|
printVectorIndex(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// EXT_ZZI_B, TBL_ZZZZ_B, TBL_ZZZ_B
|
|
printTypedVectorList(MI, 1, O, 0,'b');
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 33:
|
|
// FCPY_ZPmI_H
|
|
printFPImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// FCVT_ZPmZ_DtoH, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
return;
|
|
break;
|
|
case 35:
|
|
// FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_...
|
|
printFPImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// INDEX_II_B, INDEX_IR_B
|
|
printSImm(MI, 1, O, 8);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 37:
|
|
// INDEX_II_H
|
|
printSImm(MI, 2, O, 16);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q...
|
|
printSVERegOp(MI, 3, O, 0);
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 39:
|
|
// INSR_ZV_B
|
|
printZPRasFPR(MI, 2, O, 8);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// INSR_ZV_D
|
|
printZPRasFPR(MI, 2, O, 64);
|
|
return;
|
|
break;
|
|
case 41:
|
|
// INSR_ZV_S
|
|
printZPRasFPR(MI, 2, O, 32);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 43:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX...
|
|
SStream_concat0(O, "/z, [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 44:
|
|
// LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA...
|
|
printOperand(MI, 0, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// MOVID, MOVIv2d_ns
|
|
printSIMDType10Operand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl...
|
|
printImm(MI, 1, O);
|
|
break;
|
|
case 47:
|
|
// MRS
|
|
printMRSSystemRegister(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// PMULLv1i64
|
|
SStream_concat0(O, ".1d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
|
|
printVRegOperand(MI, 2, O);
|
|
SStream_concat0(O, ".1d");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// PMULLv2i64
|
|
SStream_concat0(O, ".2d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
printVRegOperand(MI, 2, O);
|
|
SStream_concat0(O, ".2d");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// REVD_ZPmZ
|
|
printSVERegOp(MI, 3, O, 'q');
|
|
return;
|
|
break;
|
|
case 51:
|
|
// SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi...
|
|
printGPR64as32(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSVEPattern(MI, 2, O);
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX...
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 53:
|
|
// ST1i16_POST, ST2i8_POST
|
|
printPostIncOperand(MI, 4, O, 2);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// ST1i32_POST, ST2i16_POST, ST4i8_POST
|
|
printPostIncOperand(MI, 4, O, 4);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// ST1i64_POST, ST2i32_POST, ST4i16_POST
|
|
printPostIncOperand(MI, 4, O, 8);
|
|
return;
|
|
break;
|
|
case 56:
|
|
// ST1i8_POST
|
|
printPostIncOperand(MI, 4, O, 1);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// ST2i64_POST, ST4i32_POST
|
|
printPostIncOperand(MI, 4, O, 16);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// ST3i16_POST
|
|
printPostIncOperand(MI, 4, O, 6);
|
|
return;
|
|
break;
|
|
case 59:
|
|
// ST3i32_POST
|
|
printPostIncOperand(MI, 4, O, 12);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// ST3i64_POST
|
|
printPostIncOperand(MI, 4, O, 24);
|
|
return;
|
|
break;
|
|
case 61:
|
|
// ST3i8_POST
|
|
printPostIncOperand(MI, 4, O, 3);
|
|
return;
|
|
break;
|
|
case 62:
|
|
// ST4i64_POST
|
|
printPostIncOperand(MI, 4, O, 32);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// ST64BV, ST64BV0
|
|
printGPR64x8(MI, 1, O);
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// SYSxt
|
|
printSysCROperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printSysCROperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 65:
|
|
// TBL_ZZZZ_D, TBL_ZZZ_D
|
|
printTypedVectorList(MI, 1, O, 0,'d');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
return;
|
|
break;
|
|
case 66:
|
|
// TBL_ZZZZ_S, TBL_ZZZ_S
|
|
printTypedVectorList(MI, 1, O, 0,'s');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 2, O, 's');
|
|
return;
|
|
break;
|
|
case 67:
|
|
// TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB...
|
|
printTypedVectorList(MI, 1, O, 16, 'b');
|
|
SStream_concat0(O, ", ");
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 68:
|
|
// TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB...
|
|
printTypedVectorList(MI, 2, O, 16, 'b');
|
|
SStream_concat0(O, ", ");
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 7 bits for 111 unique commands.
|
|
// printf("Fragment 3: %"PRIu64"\n", ((Bits >> 35) & 127));
|
|
switch ((Bits >> 35) & 127) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,...
|
|
printSVERegOp(MI, 3, O, 'b');
|
|
break;
|
|
case 1:
|
|
// ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ...
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm...
|
|
printSVERegOp(MI, 3, O, 's');
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ...
|
|
SStream_concat0(O, ".16b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ABSv1i64, ADR, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, AUTIB, BF...
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV...
|
|
SStream_concat0(O, ".2s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64...
|
|
SStream_concat0(O, ".2d");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT...
|
|
SStream_concat0(O, ".4h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ...
|
|
SStream_concat0(O, ".4s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT...
|
|
SStream_concat0(O, ".8h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv...
|
|
SStream_concat0(O, ".8b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSUBHNB_ZZZ_H, SUBHNB_ZZZ_H
|
|
printSVERegOp(MI, 2, O, 's');
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
|
|
SStream_concat0(O, ".2d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
break;
|
|
case 14:
|
|
// ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
|
|
SStream_concat0(O, ".4s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
break;
|
|
case 15:
|
|
// ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b...
|
|
SStream_concat0(O, ".8h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
break;
|
|
case 16:
|
|
// ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
|
|
SStream_concat0(O, "/m, ");
|
|
break;
|
|
case 17:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ...
|
|
printSVERegOp(MI, 2, O, 'h');
|
|
break;
|
|
case 18:
|
|
// ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL...
|
|
SStream_concat0(O, ".16b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
break;
|
|
case 19:
|
|
// ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
|
|
SStream_concat0(O, ".2s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
break;
|
|
case 20:
|
|
// ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4...
|
|
SStream_concat0(O, ".4h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
break;
|
|
case 21:
|
|
// ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
|
|
SStream_concat0(O, ".8b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
break;
|
|
case 22:
|
|
// ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS...
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B...
|
|
SStream_concat0(O, "/z, ");
|
|
break;
|
|
case 24:
|
|
// ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ASR_ZZI_H, INDEX_IR_B, INDEX_RR_H, LSL_ZZI_H, LSR_ZZI_H, MUL_ZI_H, RSH...
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 27:
|
|
// CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz
|
|
SStream_concat0(O, ".16b, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz
|
|
SStream_concat0(O, ", #0");
|
|
op_addImm(MI, 0);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz
|
|
SStream_concat0(O, ".2s, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz
|
|
SStream_concat0(O, ".2d, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz
|
|
SStream_concat0(O, ".4h, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz
|
|
SStream_concat0(O, ".4s, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz
|
|
SStream_concat0(O, ".8h, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz
|
|
SStream_concat0(O, ".8b, #0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
arm64_op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// CMLA_ZZZI_H, CMLA_ZZZ_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FADDA_VPZ_H, FCMLA_...
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
break;
|
|
case 36:
|
|
// CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI
|
|
SStream_concat0(O, ", mul ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// CPY_ZPmI_B
|
|
printImm8OptLsl32(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// CPY_ZPmI_D
|
|
printImm8OptLsl64(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// CPY_ZPmI_S
|
|
printImm8OptLsl32(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 41:
|
|
// CPY_ZPzI_H
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S
|
|
printVectorIndex(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// DUPi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1...
|
|
SStream_concat0(O, ".h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);
|
|
break;
|
|
case 44:
|
|
// DUPi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, SMOVvi3...
|
|
SStream_concat0(O, ".s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
|
|
break;
|
|
case 45:
|
|
// DUPi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64, UMOVvi64_idx...
|
|
SStream_concat0(O, ".d");
|
|
break;
|
|
case 46:
|
|
// DUPi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to32...
|
|
SStream_concat0(O, ".b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B);
|
|
break;
|
|
case 47:
|
|
// EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q
|
|
printMatrixTileVector(MI, 2, O, 0);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 4, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q
|
|
printMatrixTileVector(MI, 2, O, 1);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 4, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H
|
|
printImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p
|
|
SStream_concat0(O, ".2h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ...
|
|
SStream_concat0(O, ", #0.0");
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz
|
|
SStream_concat0(O, ".2s, #0.0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz
|
|
SStream_concat0(O, ".2d, #0.0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz
|
|
SStream_concat0(O, ".4h, #0.0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz
|
|
SStream_concat0(O, ".4s, #0.0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 56:
|
|
// FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz
|
|
SStream_concat0(O, ".8h, #0.0");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// FCPY_ZPmI_D, FCPY_ZPmI_S
|
|
printFPImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4...
|
|
SStream_concat0(O, ".2h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 59:
|
|
// FMOPA_MPPZZ_D, FMOPS_MPPZZ_D, INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D
|
|
printSVERegOp(MI, 4, O, 'd');
|
|
return;
|
|
break;
|
|
case 60:
|
|
// FMOPA_MPPZZ_S, FMOPS_MPPZZ_S, INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S
|
|
printSVERegOp(MI, 4, O, 's');
|
|
return;
|
|
break;
|
|
case 61:
|
|
// INDEX_II_B
|
|
printSImm(MI, 2, O, 8);
|
|
return;
|
|
break;
|
|
case 62:
|
|
// INDEX_RI_H
|
|
printSImm(MI, 2, O, 16);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// INSERT_MXIPZ_H_B, INSERT_MXIPZ_V_B
|
|
printSVERegOp(MI, 4, O, 'b');
|
|
return;
|
|
break;
|
|
case 64:
|
|
// INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H
|
|
printSVERegOp(MI, 4, O, 'h');
|
|
return;
|
|
break;
|
|
case 65:
|
|
// INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q
|
|
printSVERegOp(MI, 4, O, 'q');
|
|
return;
|
|
break;
|
|
case 66:
|
|
// LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B
|
|
printRegWithShiftExtend(MI, 5, O, false, 8, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D
|
|
printRegWithShiftExtend(MI, 5, O, false, 64, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 68:
|
|
// LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H
|
|
printRegWithShiftExtend(MI, 5, O, false, 16, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q
|
|
printRegWithShiftExtend(MI, 5, O, false, 128, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S
|
|
printRegWithShiftExtend(MI, 5, O, false, 32, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD...
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo...
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 73:
|
|
// MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ...
|
|
printShifter(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 74:
|
|
// PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H, SABDLT_ZZZ_H, SADDLBT_ZZZ_H,...
|
|
printSVERegOp(MI, 2, O, 'b');
|
|
return;
|
|
break;
|
|
case 75:
|
|
// PRFB_D_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// PRFB_D_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 77:
|
|
// PRFB_D_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// PRFB_PRR
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 79:
|
|
// PRFB_S_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// PRFB_S_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// PRFD_D_PZI, PRFD_S_PZI
|
|
printImmScale(MI, 3, O, 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// PRFD_D_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// PRFD_D_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 84:
|
|
// PRFD_D_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// PRFD_PRR
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// PRFD_S_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 87:
|
|
// PRFD_S_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 88:
|
|
// PRFH_D_PZI, PRFH_S_PZI
|
|
printImmScale(MI, 3, O, 2);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 89:
|
|
// PRFH_D_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 90:
|
|
// PRFH_D_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 91:
|
|
// PRFH_D_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 92:
|
|
// PRFH_PRR
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 93:
|
|
// PRFH_S_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 94:
|
|
// PRFH_S_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 95:
|
|
// PRFS_PRR
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 96:
|
|
// PRFW_D_PZI, PRFW_S_PZI
|
|
printImmScale(MI, 3, O, 4);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 97:
|
|
// PRFW_D_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 98:
|
|
// PRFW_D_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 99:
|
|
// PRFW_D_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 100:
|
|
// PRFW_S_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 101:
|
|
// PRFW_S_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 102:
|
|
// RDFFRS_PPz, RDFFR_PPz_REAL
|
|
SStream_concat0(O, "/z");
|
|
return;
|
|
break;
|
|
case 103:
|
|
// SHLLv16i8
|
|
SStream_concat0(O, ".16b, #8");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
arm64_op_addImm(MI, 8);
|
|
return;
|
|
break;
|
|
case 104:
|
|
// SHLLv2i32
|
|
SStream_concat0(O, ".2s, #32");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
arm64_op_addImm(MI, 32);
|
|
return;
|
|
break;
|
|
case 105:
|
|
// SHLLv4i16
|
|
SStream_concat0(O, ".4h, #16");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
arm64_op_addImm(MI, 16);
|
|
return;
|
|
break;
|
|
case 106:
|
|
// SHLLv4i32
|
|
SStream_concat0(O, ".4s, #32");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
arm64_op_addImm(MI, 32);
|
|
return;
|
|
break;
|
|
case 107:
|
|
// SHLLv8i16
|
|
SStream_concat0(O, ".8h, #16");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
arm64_op_addImm(MI, 16);
|
|
return;
|
|
break;
|
|
case 108:
|
|
// SHLLv8i8
|
|
SStream_concat0(O, ".8b, #8");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
arm64_op_addImm(MI, 8);
|
|
return;
|
|
break;
|
|
case 109:
|
|
// SPLICE_ZPZZ_H
|
|
printTypedVectorList(MI, 2, O, 0,'h');
|
|
return;
|
|
break;
|
|
case 110:
|
|
// TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q, ZIP2_ZZZ_Q
|
|
printSVERegOp(MI, 2, O, 'q');
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 7 bits for 94 unique commands.
|
|
// printf("Fragment 4: %"PRIu64"\n", ((Bits >> 42) & 127));
|
|
switch ((Bits >> 42) & 127) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ABS_ZPmZ_B, ADD_ZZZ_H, BDEP_ZZZ_H, BEXT_ZZZ_H, BGRP_ZZZ_H, BRKA_PPmP, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB...
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
break;
|
|
case 2:
|
|
// ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_...
|
|
printSVERegOp(MI, 3, O, 's');
|
|
break;
|
|
case 3:
|
|
// ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 4:
|
|
// ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG
|
|
printImmScale(MI, 2, O, 16);
|
|
break;
|
|
case 5:
|
|
// ADDHNB_ZZZ_B, CNTP_XPP_H, LASTA_RPZ_H, LASTA_VPZ_H, LASTB_RPZ_H, LASTB...
|
|
printSVERegOp(MI, 2, O, 'h');
|
|
break;
|
|
case 6:
|
|
// ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, AND_ZPmZ_D, AND_ZZZ,...
|
|
printSVERegOp(MI, 2, O, 'd');
|
|
break;
|
|
case 7:
|
|
// ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
break;
|
|
case 8:
|
|
// ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2...
|
|
printVRegOperand(MI, 2, O);
|
|
break;
|
|
case 9:
|
|
// ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1...
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 10:
|
|
// ADDP_ZPmZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, ANDS_PPzPP...
|
|
printSVERegOp(MI, 2, O, 'b');
|
|
break;
|
|
case 11:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 12:
|
|
// ADDP_ZPmZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ...
|
|
printSVERegOp(MI, 2, O, 's');
|
|
break;
|
|
case 13:
|
|
// ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri
|
|
printAddSubImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI...
|
|
printShiftedRegister(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx
|
|
printExtendedRegister(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS...
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS...
|
|
printImm8OptLsl64(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS...
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ADR_LSL_ZZZ_D_0
|
|
printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ADR_LSL_ZZZ_D_1
|
|
printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ADR_LSL_ZZZ_D_2
|
|
printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ADR_LSL_ZZZ_D_3
|
|
printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ADR_LSL_ZZZ_S_0
|
|
printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ADR_LSL_ZZZ_S_1
|
|
printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ADR_LSL_ZZZ_S_2
|
|
printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ADR_LSL_ZZZ_S_3
|
|
printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ADR_SXTW_ZZZ_D_0
|
|
printRegWithShiftExtend(MI, 2, O, true, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ADR_SXTW_ZZZ_D_1
|
|
printRegWithShiftExtend(MI, 2, O, true, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// ADR_SXTW_ZZZ_D_2
|
|
printRegWithShiftExtend(MI, 2, O, true, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// ADR_SXTW_ZZZ_D_3
|
|
printRegWithShiftExtend(MI, 2, O, true, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// ADR_UXTW_ZZZ_D_0
|
|
printRegWithShiftExtend(MI, 2, O, false, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// ADR_UXTW_ZZZ_D_1
|
|
printRegWithShiftExtend(MI, 2, O, false, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// ADR_UXTW_ZZZ_D_2
|
|
printRegWithShiftExtend(MI, 2, O, false, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// ADR_UXTW_ZZZ_D_3
|
|
printRegWithShiftExtend(MI, 2, O, false, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// ANDSWri, ANDWri, EORWri, ORRWri
|
|
printLogicalImm32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI
|
|
printLogicalImm64(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 38:
|
|
// CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H, INSv...
|
|
printVectorIndex(MI, 4, O);
|
|
break;
|
|
case 39:
|
|
// CPY_ZPzI_B
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// CPY_ZPzI_D
|
|
printImm8OptLsl64(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 41:
|
|
// CPY_ZPzI_S
|
|
printImm8OptLsl32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// DUPi16, DUPi32, DUPi64, DUPi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan...
|
|
printVectorIndex(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S
|
|
printMatrixTileVector(MI, 2, O, 0);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 4, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S
|
|
printMatrixTileVector(MI, 2, O, 1);
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 4, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ...
|
|
SStream_concat0(O, ", #0.0");
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16
|
|
SStream_concat0(O, ".h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);
|
|
printVectorIndex(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16
|
|
SStream_concat0(O, ".2h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H
|
|
printVectorIndex(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ...
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R...
|
|
printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R...
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT...
|
|
printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT...
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, LDRAAwriteback, LDRABwrit...
|
|
printImmScale(MI, 3, O, 8);
|
|
break;
|
|
case 55:
|
|
// GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED_SCALED_REAL
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 56:
|
|
// GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 57:
|
|
// GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 58:
|
|
// GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE...
|
|
printImmScale(MI, 3, O, 2);
|
|
break;
|
|
case 59:
|
|
// GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF...
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC...
|
|
printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 61:
|
|
// GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC...
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 62:
|
|
// GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC...
|
|
printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC...
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE...
|
|
printImmScale(MI, 3, O, 4);
|
|
break;
|
|
case 65:
|
|
// GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD...
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 66:
|
|
// GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S...
|
|
printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S...
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 68:
|
|
// GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's');
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// INDEX_RI_B
|
|
printSImm(MI, 2, O, 8);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RO_B, LD1RQ_B, LD1SB_D, LD1SB_H, LD1S...
|
|
printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// LD1D, LD1RO_D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1...
|
|
printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 73:
|
|
// LD1H, LD1H_D, LD1H_S, LD1RO_H, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, ...
|
|
printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 74:
|
|
// LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM
|
|
printImmScale(MI, 3, O, 32);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 75:
|
|
// LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_R...
|
|
printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM, LDG, ST2GPostIndex...
|
|
printImmScale(MI, 3, O, 16);
|
|
break;
|
|
case 77:
|
|
// LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ...
|
|
printImmScale(MI, 3, O, 3);
|
|
SStream_concat0(O, ", mul vl]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// LDRAAindexed, LDRABindexed
|
|
printImmScale(MI, 2, O, 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 79:
|
|
// LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui
|
|
printUImm12Offset(MI, 2, O, 1);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// LDRDui, LDRXui, PRFMui, STRDui, STRXui
|
|
printUImm12Offset(MI, 2, O, 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui
|
|
printUImm12Offset(MI, 2, O, 2);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// LDRQui, STRQui
|
|
printUImm12Offset(MI, 2, O, 16);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// LDRSWui, LDRSui, LDRWui, STRSui, STRWui
|
|
printUImm12Offset(MI, 2, O, 4);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 84:
|
|
// MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B
|
|
printSVERegOp(MI, 3, O, 'b');
|
|
SStream_concat0(O, ", ");
|
|
printSVERegOp(MI, 4, O, 'b');
|
|
return;
|
|
break;
|
|
case 85:
|
|
// PRFB_D_PZI, PRFB_S_PZI
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI
|
|
SStream_concat0(O, ", mul vl]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 87:
|
|
// SPLICE_ZPZZ_B
|
|
printTypedVectorList(MI, 2, O, 0,'b');
|
|
return;
|
|
break;
|
|
case 88:
|
|
// SPLICE_ZPZZ_D
|
|
printTypedVectorList(MI, 2, O, 0,'d');
|
|
return;
|
|
break;
|
|
case 89:
|
|
// SPLICE_ZPZZ_S
|
|
printTypedVectorList(MI, 2, O, 0,'s');
|
|
return;
|
|
break;
|
|
case 90:
|
|
// SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW...
|
|
printGPR64as32(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 91:
|
|
// SYSLxt
|
|
printSysCROperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printSysCROperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 92:
|
|
// TBNZW, TBNZX, TBZW, TBZX
|
|
printAlignedLabel(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 93:
|
|
// UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S
|
|
printImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 6 bits for 41 unique commands.
|
|
// printf("Fragment 5: %"PRIu64"\n", ((Bits >> 49) & 63));
|
|
switch ((Bits >> 49) & 63) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
|
|
SStream_concat0(O, ".2d");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
|
|
SStream_concat0(O, ".4s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B...
|
|
SStream_concat0(O, ".8h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ...
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
break;
|
|
case 6:
|
|
// ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,...
|
|
SStream_concat0(O, ".16b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
|
|
SStream_concat0(O, ".2s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH...
|
|
SStream_concat0(O, ".4h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
|
|
SStream_concat0(O, ".8b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64
|
|
printArithExtend(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP...
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
return;
|
|
break;
|
|
case 13:
|
|
// BCAX, EOR3, EXTv16i8
|
|
SStream_concat0(O, ".16b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
break;
|
|
case 14:
|
|
// BF16DOTlanev4bf16, BF16DOTlanev8bf16
|
|
SStream_concat0(O, ".2h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);
|
|
printVectorIndex(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// BFDOT_ZZI, BFMMLA_B_ZZI, BFMMLA_T_ZZI, CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA...
|
|
printVectorIndex(MI, 4, O);
|
|
break;
|
|
case 16:
|
|
// BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2...
|
|
SStream_concat0(O, ".h");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);
|
|
break;
|
|
case 17:
|
|
// CADD_ZZI_H, SQCADD_ZZI_H
|
|
printComplexRotationOp(MI, 3, O, 180, 90);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H
|
|
printComplexRotationOp(MI, 4, O, 90, 0);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H
|
|
printImm(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// EXTv8i8
|
|
SStream_concat0(O, ".8b, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// FCADDv2f32, FCMLAv2f32
|
|
SStream_concat0(O, ".2s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
|
|
break;
|
|
case 24:
|
|
// FCADDv2f64, FCMLAv2f64, XAR
|
|
SStream_concat0(O, ".2d, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
|
|
break;
|
|
case 25:
|
|
// FCADDv4f16, FCMLAv4f16
|
|
SStream_concat0(O, ".4h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
|
|
break;
|
|
case 26:
|
|
// FCADDv4f32, FCMLAv4f32, SM3SS1
|
|
SStream_concat0(O, ".4s, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
break;
|
|
case 27:
|
|
// FCADDv8f16, FCMLAv8f16
|
|
SStream_concat0(O, ".8h, ");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
|
|
break;
|
|
case 28:
|
|
// FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ...
|
|
SStream_concat0(O, ", #0.0");
|
|
arm64_op_addFP(MI, 0);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,...
|
|
printSVERegOp(MI, 4, O, 'h');
|
|
break;
|
|
case 30:
|
|
// FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in...
|
|
SStream_concat0(O, ".s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
|
|
break;
|
|
case 31:
|
|
// FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind...
|
|
SStream_concat0(O, ".d");
|
|
break;
|
|
case 33:
|
|
// FMUL_ZPmI_H
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL...
|
|
printVectorIndex(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D...
|
|
SStream_concat0(O, ", mul vl]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,...
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 37:
|
|
// LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ...
|
|
SStream_concat0(O, "]!");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S
|
|
SStream_concat0(O, "[");
|
|
set_sme_index(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printMatrixIndex(MI, 4, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev16i8, SUDOTlanev8i8, UDOTlanev1...
|
|
SStream_concat0(O, ".4b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4B);
|
|
printVectorIndex(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// STLXPW, STLXPX, STXPW, STXPX
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 6 bits for 37 unique commands.
|
|
// printf("Fragment 6: %"PRIu64"\n", ((Bits >> 55) & 63));
|
|
switch ((Bits >> 55) & 63) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_...
|
|
printSVERegOp(MI, 3, O, 'b');
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR...
|
|
printSVERegOp(MI, 3, O, 'd');
|
|
break;
|
|
case 3:
|
|
// ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFDOT_ZZ...
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ...
|
|
printSVERegOp(MI, 3, O, 's');
|
|
break;
|
|
case 5:
|
|
// BCAX, EOR3, SM3SS1
|
|
printVRegOperand(MI, 3, O);
|
|
break;
|
|
case 6:
|
|
// BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv...
|
|
printVectorIndex(MI, 4, O);
|
|
break;
|
|
case 7:
|
|
// BFMWri, BFMXri
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16...
|
|
printComplexRotationOp(MI, 3, O, 180, 90);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr...
|
|
printCondCode(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 11:
|
|
// CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H
|
|
printComplexRotationOp(MI, 5, O, 90, 0);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16...
|
|
printComplexRotationOp(MI, 4, O, 90, 0);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H
|
|
printSVERegOp(MI, 3, O, 'h');
|
|
return;
|
|
break;
|
|
case 14:
|
|
// CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ...
|
|
printImm(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU...
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,...
|
|
printSVERegOp(MI, 4, O, 'd');
|
|
break;
|
|
case 17:
|
|
// FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,...
|
|
printSVERegOp(MI, 4, O, 's');
|
|
break;
|
|
case 18:
|
|
// FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,...
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32...
|
|
printVectorIndex(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// FMUL_ZPmI_D, FMUL_ZPmI_S
|
|
printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi
|
|
printImmScale(MI, 3, O, 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// LDNPQi, LDPQi, STGPi, STNPQi, STPQi
|
|
printImmScale(MI, 3, O, 16);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi
|
|
printImmScale(MI, 3, O, 4);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP...
|
|
printImmScale(MI, 4, O, 8);
|
|
break;
|
|
case 25:
|
|
// LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre
|
|
printImmScale(MI, 4, O, 16);
|
|
break;
|
|
case 26:
|
|
// LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S...
|
|
printImmScale(MI, 4, O, 4);
|
|
break;
|
|
case 27:
|
|
// LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW
|
|
printMemExtend(MI, 3, O, 'w', 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX
|
|
printMemExtend(MI, 3, O, 'x', 8);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW
|
|
printMemExtend(MI, 3, O, 'w', 64);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX
|
|
printMemExtend(MI, 3, O, 'x', 64);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW
|
|
printMemExtend(MI, 3, O, 'w', 16);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX
|
|
printMemExtend(MI, 3, O, 'x', 16);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// LDRQroW, STRQroW
|
|
printMemExtend(MI, 3, O, 'w', 128);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// LDRQroX, STRQroX
|
|
printMemExtend(MI, 3, O, 'x', 128);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW
|
|
printMemExtend(MI, 3, O, 'w', 32);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX
|
|
printMemExtend(MI, 3, O, 'x', 32);
|
|
SStream_concat0(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 7 encoded into 3 bits for 7 unique commands.
|
|
// printf("Fragment 7: %"PRIu64"\n", ((Bits >> 61) & 7));
|
|
switch ((Bits >> 61) & 7) {
|
|
default: // unreachable
|
|
case 0:
|
|
// ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// BCAX, EOR3
|
|
SStream_concat0(O, ".16b");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, SQRDCMLAH_ZZZI_...
|
|
printComplexRotationOp(MI, 5, O, 90, 0);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 4:
|
|
// FCADD_ZPmZ_H
|
|
printComplexRotationOp(MI, 4, O, 180, 90);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STGPpre, STPDpr...
|
|
SStream_concat0(O, "]!");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// SM3SS1
|
|
SStream_concat0(O, ".4s");
|
|
arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default:
|
|
case AArch64_FCADD_ZPmZ_D:
|
|
case AArch64_FCADD_ZPmZ_S:
|
|
case AArch64_FCMLA_ZPmZZ_D:
|
|
case AArch64_FCMLA_ZPmZZ_S:
|
|
case AArch64_FCMLAv4f16_indexed:
|
|
case AArch64_FCMLAv4f32_indexed:
|
|
case AArch64_FCMLAv8f16_indexed:
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default:
|
|
case AArch64_FCADD_ZPmZ_D:
|
|
case AArch64_FCADD_ZPmZ_S:
|
|
printComplexRotationOp(MI, 4, O, 180, 90);
|
|
break;
|
|
case AArch64_FCMLA_ZPmZZ_D:
|
|
case AArch64_FCMLA_ZPmZZ_S:
|
|
case AArch64_FCMLAv4f16_indexed:
|
|
case AArch64_FCMLAv4f32_indexed:
|
|
case AArch64_FCMLAv8f16_indexed:
|
|
printComplexRotationOp(MI, 5, O, 90, 0);
|
|
break;
|
|
}
|
|
return;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp,
|
|
unsigned PredicateIndex);
|
|
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
|
|
{
|
|
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
|
unsigned int I = 0, OpIdx, PrintMethodIdx;
|
|
char *tmpString;
|
|
static const PatternsForOpcode OpToPatterns[] = {
|
|
{AArch64_ADDSWri, 0, 1 },
|
|
{AArch64_ADDSWrs, 1, 3 },
|
|
{AArch64_ADDSWrx, 4, 3 },
|
|
{AArch64_ADDSXri, 7, 1 },
|
|
{AArch64_ADDSXrs, 8, 3 },
|
|
{AArch64_ADDSXrx, 11, 1 },
|
|
{AArch64_ADDSXrx64, 12, 3 },
|
|
{AArch64_ADDWri, 15, 2 },
|
|
{AArch64_ADDWrs, 17, 1 },
|
|
{AArch64_ADDWrx, 18, 2 },
|
|
{AArch64_ADDXri, 20, 2 },
|
|
{AArch64_ADDXrs, 22, 1 },
|
|
{AArch64_ADDXrx64, 23, 2 },
|
|
{AArch64_ANDSWri, 25, 1 },
|
|
{AArch64_ANDSWrs, 26, 3 },
|
|
{AArch64_ANDSXri, 29, 1 },
|
|
{AArch64_ANDSXrs, 30, 3 },
|
|
{AArch64_ANDS_PPzPP, 33, 1 },
|
|
{AArch64_ANDWrs, 34, 1 },
|
|
{AArch64_ANDXrs, 35, 1 },
|
|
{AArch64_AND_PPzPP, 36, 1 },
|
|
{AArch64_AND_ZI, 37, 3 },
|
|
{AArch64_AUTIA1716, 40, 1 },
|
|
{AArch64_AUTIASP, 41, 1 },
|
|
{AArch64_AUTIAZ, 42, 1 },
|
|
{AArch64_AUTIB1716, 43, 1 },
|
|
{AArch64_AUTIBSP, 44, 1 },
|
|
{AArch64_AUTIBZ, 45, 1 },
|
|
{AArch64_BICSWrs, 46, 1 },
|
|
{AArch64_BICSXrs, 47, 1 },
|
|
{AArch64_BICWrs, 48, 1 },
|
|
{AArch64_BICXrs, 49, 1 },
|
|
{AArch64_CLREX, 50, 1 },
|
|
{AArch64_CNTB_XPiI, 51, 2 },
|
|
{AArch64_CNTD_XPiI, 53, 2 },
|
|
{AArch64_CNTH_XPiI, 55, 2 },
|
|
{AArch64_CNTW_XPiI, 57, 2 },
|
|
{AArch64_CPY_ZPmI_B, 59, 1 },
|
|
{AArch64_CPY_ZPmI_D, 60, 1 },
|
|
{AArch64_CPY_ZPmI_H, 61, 1 },
|
|
{AArch64_CPY_ZPmI_S, 62, 1 },
|
|
{AArch64_CPY_ZPmR_B, 63, 1 },
|
|
{AArch64_CPY_ZPmR_D, 64, 1 },
|
|
{AArch64_CPY_ZPmR_H, 65, 1 },
|
|
{AArch64_CPY_ZPmR_S, 66, 1 },
|
|
{AArch64_CPY_ZPmV_B, 67, 1 },
|
|
{AArch64_CPY_ZPmV_D, 68, 1 },
|
|
{AArch64_CPY_ZPmV_H, 69, 1 },
|
|
{AArch64_CPY_ZPmV_S, 70, 1 },
|
|
{AArch64_CPY_ZPzI_B, 71, 1 },
|
|
{AArch64_CPY_ZPzI_D, 72, 1 },
|
|
{AArch64_CPY_ZPzI_H, 73, 1 },
|
|
{AArch64_CPY_ZPzI_S, 74, 1 },
|
|
{AArch64_CSINCWr, 75, 2 },
|
|
{AArch64_CSINCXr, 77, 2 },
|
|
{AArch64_CSINVWr, 79, 2 },
|
|
{AArch64_CSINVXr, 81, 2 },
|
|
{AArch64_CSNEGWr, 83, 1 },
|
|
{AArch64_CSNEGXr, 84, 1 },
|
|
{AArch64_DCPS1, 85, 1 },
|
|
{AArch64_DCPS2, 86, 1 },
|
|
{AArch64_DCPS3, 87, 1 },
|
|
{AArch64_DECB_XPiI, 88, 2 },
|
|
{AArch64_DECD_XPiI, 90, 2 },
|
|
{AArch64_DECD_ZPiI, 92, 2 },
|
|
{AArch64_DECH_XPiI, 94, 2 },
|
|
{AArch64_DECH_ZPiI, 96, 2 },
|
|
{AArch64_DECW_XPiI, 98, 2 },
|
|
{AArch64_DECW_ZPiI, 100, 2 },
|
|
{AArch64_DSB, 102, 3 },
|
|
{AArch64_DUPM_ZI, 105, 6 },
|
|
{AArch64_DUP_ZI_B, 111, 1 },
|
|
{AArch64_DUP_ZI_D, 112, 2 },
|
|
{AArch64_DUP_ZI_H, 114, 2 },
|
|
{AArch64_DUP_ZI_S, 116, 2 },
|
|
{AArch64_DUP_ZR_B, 118, 1 },
|
|
{AArch64_DUP_ZR_D, 119, 1 },
|
|
{AArch64_DUP_ZR_H, 120, 1 },
|
|
{AArch64_DUP_ZR_S, 121, 1 },
|
|
{AArch64_DUP_ZZI_B, 122, 2 },
|
|
{AArch64_DUP_ZZI_D, 124, 2 },
|
|
{AArch64_DUP_ZZI_H, 126, 2 },
|
|
{AArch64_DUP_ZZI_Q, 128, 2 },
|
|
{AArch64_DUP_ZZI_S, 130, 2 },
|
|
{AArch64_EONWrs, 132, 1 },
|
|
{AArch64_EONXrs, 133, 1 },
|
|
{AArch64_EORS_PPzPP, 134, 1 },
|
|
{AArch64_EORWrs, 135, 1 },
|
|
{AArch64_EORXrs, 136, 1 },
|
|
{AArch64_EOR_PPzPP, 137, 1 },
|
|
{AArch64_EOR_ZI, 138, 3 },
|
|
{AArch64_EXTRACT_ZPMXI_H_B, 141, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_D, 142, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_H, 143, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_Q, 144, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_H_S, 145, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_B, 146, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_D, 147, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_H, 148, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_Q, 149, 1 },
|
|
{AArch64_EXTRACT_ZPMXI_V_S, 150, 1 },
|
|
{AArch64_EXTRWrri, 151, 1 },
|
|
{AArch64_EXTRXrri, 152, 1 },
|
|
{AArch64_FCPY_ZPmI_D, 153, 1 },
|
|
{AArch64_FCPY_ZPmI_H, 154, 1 },
|
|
{AArch64_FCPY_ZPmI_S, 155, 1 },
|
|
{AArch64_FDUP_ZI_D, 156, 1 },
|
|
{AArch64_FDUP_ZI_H, 157, 1 },
|
|
{AArch64_FDUP_ZI_S, 158, 1 },
|
|
{AArch64_GLD1B_D_IMM_REAL, 159, 1 },
|
|
{AArch64_GLD1B_S_IMM_REAL, 160, 1 },
|
|
{AArch64_GLD1D_IMM_REAL, 161, 1 },
|
|
{AArch64_GLD1H_D_IMM_REAL, 162, 1 },
|
|
{AArch64_GLD1H_S_IMM_REAL, 163, 1 },
|
|
{AArch64_GLD1SB_D_IMM_REAL, 164, 1 },
|
|
{AArch64_GLD1SB_S_IMM_REAL, 165, 1 },
|
|
{AArch64_GLD1SH_D_IMM_REAL, 166, 1 },
|
|
{AArch64_GLD1SH_S_IMM_REAL, 167, 1 },
|
|
{AArch64_GLD1SW_D_IMM_REAL, 168, 1 },
|
|
{AArch64_GLD1W_D_IMM_REAL, 169, 1 },
|
|
{AArch64_GLD1W_IMM_REAL, 170, 1 },
|
|
{AArch64_GLDFF1B_D_IMM_REAL, 171, 1 },
|
|
{AArch64_GLDFF1B_S_IMM_REAL, 172, 1 },
|
|
{AArch64_GLDFF1D_IMM_REAL, 173, 1 },
|
|
{AArch64_GLDFF1H_D_IMM_REAL, 174, 1 },
|
|
{AArch64_GLDFF1H_S_IMM_REAL, 175, 1 },
|
|
{AArch64_GLDFF1SB_D_IMM_REAL, 176, 1 },
|
|
{AArch64_GLDFF1SB_S_IMM_REAL, 177, 1 },
|
|
{AArch64_GLDFF1SH_D_IMM_REAL, 178, 1 },
|
|
{AArch64_GLDFF1SH_S_IMM_REAL, 179, 1 },
|
|
{AArch64_GLDFF1SW_D_IMM_REAL, 180, 1 },
|
|
{AArch64_GLDFF1W_D_IMM_REAL, 181, 1 },
|
|
{AArch64_GLDFF1W_IMM_REAL, 182, 1 },
|
|
{AArch64_HINT, 183, 12 },
|
|
{AArch64_INCB_XPiI, 195, 2 },
|
|
{AArch64_INCD_XPiI, 197, 2 },
|
|
{AArch64_INCD_ZPiI, 199, 2 },
|
|
{AArch64_INCH_XPiI, 201, 2 },
|
|
{AArch64_INCH_ZPiI, 203, 2 },
|
|
{AArch64_INCW_XPiI, 205, 2 },
|
|
{AArch64_INCW_ZPiI, 207, 2 },
|
|
{AArch64_INSERT_MXIPZ_H_B, 209, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_D, 210, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_H, 211, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_Q, 212, 1 },
|
|
{AArch64_INSERT_MXIPZ_H_S, 213, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_B, 214, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_D, 215, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_H, 216, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_Q, 217, 1 },
|
|
{AArch64_INSERT_MXIPZ_V_S, 218, 1 },
|
|
{AArch64_INSvi16gpr, 219, 1 },
|
|
{AArch64_INSvi16lane, 220, 1 },
|
|
{AArch64_INSvi32gpr, 221, 1 },
|
|
{AArch64_INSvi32lane, 222, 1 },
|
|
{AArch64_INSvi64gpr, 223, 1 },
|
|
{AArch64_INSvi64lane, 224, 1 },
|
|
{AArch64_INSvi8gpr, 225, 1 },
|
|
{AArch64_INSvi8lane, 226, 1 },
|
|
{AArch64_IRG, 227, 1 },
|
|
{AArch64_ISB, 228, 1 },
|
|
{AArch64_LD1B_D_IMM_REAL, 229, 1 },
|
|
{AArch64_LD1B_H_IMM_REAL, 230, 1 },
|
|
{AArch64_LD1B_IMM_REAL, 231, 1 },
|
|
{AArch64_LD1B_S_IMM_REAL, 232, 1 },
|
|
{AArch64_LD1D_IMM_REAL, 233, 1 },
|
|
{AArch64_LD1Fourv16b_POST, 234, 1 },
|
|
{AArch64_LD1Fourv1d_POST, 235, 1 },
|
|
{AArch64_LD1Fourv2d_POST, 236, 1 },
|
|
{AArch64_LD1Fourv2s_POST, 237, 1 },
|
|
{AArch64_LD1Fourv4h_POST, 238, 1 },
|
|
{AArch64_LD1Fourv4s_POST, 239, 1 },
|
|
{AArch64_LD1Fourv8b_POST, 240, 1 },
|
|
{AArch64_LD1Fourv8h_POST, 241, 1 },
|
|
{AArch64_LD1H_D_IMM_REAL, 242, 1 },
|
|
{AArch64_LD1H_IMM_REAL, 243, 1 },
|
|
{AArch64_LD1H_S_IMM_REAL, 244, 1 },
|
|
{AArch64_LD1Onev16b_POST, 245, 1 },
|
|
{AArch64_LD1Onev1d_POST, 246, 1 },
|
|
{AArch64_LD1Onev2d_POST, 247, 1 },
|
|
{AArch64_LD1Onev2s_POST, 248, 1 },
|
|
{AArch64_LD1Onev4h_POST, 249, 1 },
|
|
{AArch64_LD1Onev4s_POST, 250, 1 },
|
|
{AArch64_LD1Onev8b_POST, 251, 1 },
|
|
{AArch64_LD1Onev8h_POST, 252, 1 },
|
|
{AArch64_LD1RB_D_IMM, 253, 1 },
|
|
{AArch64_LD1RB_H_IMM, 254, 1 },
|
|
{AArch64_LD1RB_IMM, 255, 1 },
|
|
{AArch64_LD1RB_S_IMM, 256, 1 },
|
|
{AArch64_LD1RD_IMM, 257, 1 },
|
|
{AArch64_LD1RH_D_IMM, 258, 1 },
|
|
{AArch64_LD1RH_IMM, 259, 1 },
|
|
{AArch64_LD1RH_S_IMM, 260, 1 },
|
|
{AArch64_LD1RO_B_IMM, 261, 1 },
|
|
{AArch64_LD1RO_D_IMM, 262, 1 },
|
|
{AArch64_LD1RO_H_IMM, 263, 1 },
|
|
{AArch64_LD1RO_W_IMM, 264, 1 },
|
|
{AArch64_LD1RQ_B_IMM, 265, 1 },
|
|
{AArch64_LD1RQ_D_IMM, 266, 1 },
|
|
{AArch64_LD1RQ_H_IMM, 267, 1 },
|
|
{AArch64_LD1RQ_W_IMM, 268, 1 },
|
|
{AArch64_LD1RSB_D_IMM, 269, 1 },
|
|
{AArch64_LD1RSB_H_IMM, 270, 1 },
|
|
{AArch64_LD1RSB_S_IMM, 271, 1 },
|
|
{AArch64_LD1RSH_D_IMM, 272, 1 },
|
|
{AArch64_LD1RSH_S_IMM, 273, 1 },
|
|
{AArch64_LD1RSW_IMM, 274, 1 },
|
|
{AArch64_LD1RW_D_IMM, 275, 1 },
|
|
{AArch64_LD1RW_IMM, 276, 1 },
|
|
{AArch64_LD1Rv16b_POST, 277, 1 },
|
|
{AArch64_LD1Rv1d_POST, 278, 1 },
|
|
{AArch64_LD1Rv2d_POST, 279, 1 },
|
|
{AArch64_LD1Rv2s_POST, 280, 1 },
|
|
{AArch64_LD1Rv4h_POST, 281, 1 },
|
|
{AArch64_LD1Rv4s_POST, 282, 1 },
|
|
{AArch64_LD1Rv8b_POST, 283, 1 },
|
|
{AArch64_LD1Rv8h_POST, 284, 1 },
|
|
{AArch64_LD1SB_D_IMM_REAL, 285, 1 },
|
|
{AArch64_LD1SB_H_IMM_REAL, 286, 1 },
|
|
{AArch64_LD1SB_S_IMM_REAL, 287, 1 },
|
|
{AArch64_LD1SH_D_IMM_REAL, 288, 1 },
|
|
{AArch64_LD1SH_S_IMM_REAL, 289, 1 },
|
|
{AArch64_LD1SW_D_IMM_REAL, 290, 1 },
|
|
{AArch64_LD1Threev16b_POST, 291, 1 },
|
|
{AArch64_LD1Threev1d_POST, 292, 1 },
|
|
{AArch64_LD1Threev2d_POST, 293, 1 },
|
|
{AArch64_LD1Threev2s_POST, 294, 1 },
|
|
{AArch64_LD1Threev4h_POST, 295, 1 },
|
|
{AArch64_LD1Threev4s_POST, 296, 1 },
|
|
{AArch64_LD1Threev8b_POST, 297, 1 },
|
|
{AArch64_LD1Threev8h_POST, 298, 1 },
|
|
{AArch64_LD1Twov16b_POST, 299, 1 },
|
|
{AArch64_LD1Twov1d_POST, 300, 1 },
|
|
{AArch64_LD1Twov2d_POST, 301, 1 },
|
|
{AArch64_LD1Twov2s_POST, 302, 1 },
|
|
{AArch64_LD1Twov4h_POST, 303, 1 },
|
|
{AArch64_LD1Twov4s_POST, 304, 1 },
|
|
{AArch64_LD1Twov8b_POST, 305, 1 },
|
|
{AArch64_LD1Twov8h_POST, 306, 1 },
|
|
{AArch64_LD1W_D_IMM_REAL, 307, 1 },
|
|
{AArch64_LD1W_IMM_REAL, 308, 1 },
|
|
{AArch64_LD1_MXIPXX_H_B, 309, 1 },
|
|
{AArch64_LD1_MXIPXX_H_D, 310, 1 },
|
|
{AArch64_LD1_MXIPXX_H_H, 311, 1 },
|
|
{AArch64_LD1_MXIPXX_H_Q, 312, 1 },
|
|
{AArch64_LD1_MXIPXX_H_S, 313, 1 },
|
|
{AArch64_LD1_MXIPXX_V_B, 314, 1 },
|
|
{AArch64_LD1_MXIPXX_V_D, 315, 1 },
|
|
{AArch64_LD1_MXIPXX_V_H, 316, 1 },
|
|
{AArch64_LD1_MXIPXX_V_Q, 317, 1 },
|
|
{AArch64_LD1_MXIPXX_V_S, 318, 1 },
|
|
{AArch64_LD1i16_POST, 319, 1 },
|
|
{AArch64_LD1i32_POST, 320, 1 },
|
|
{AArch64_LD1i64_POST, 321, 1 },
|
|
{AArch64_LD1i8_POST, 322, 1 },
|
|
{AArch64_LD2B_IMM, 323, 1 },
|
|
{AArch64_LD2D_IMM, 324, 1 },
|
|
{AArch64_LD2H_IMM, 325, 1 },
|
|
{AArch64_LD2Rv16b_POST, 326, 1 },
|
|
{AArch64_LD2Rv1d_POST, 327, 1 },
|
|
{AArch64_LD2Rv2d_POST, 328, 1 },
|
|
{AArch64_LD2Rv2s_POST, 329, 1 },
|
|
{AArch64_LD2Rv4h_POST, 330, 1 },
|
|
{AArch64_LD2Rv4s_POST, 331, 1 },
|
|
{AArch64_LD2Rv8b_POST, 332, 1 },
|
|
{AArch64_LD2Rv8h_POST, 333, 1 },
|
|
{AArch64_LD2Twov16b_POST, 334, 1 },
|
|
{AArch64_LD2Twov2d_POST, 335, 1 },
|
|
{AArch64_LD2Twov2s_POST, 336, 1 },
|
|
{AArch64_LD2Twov4h_POST, 337, 1 },
|
|
{AArch64_LD2Twov4s_POST, 338, 1 },
|
|
{AArch64_LD2Twov8b_POST, 339, 1 },
|
|
{AArch64_LD2Twov8h_POST, 340, 1 },
|
|
{AArch64_LD2W_IMM, 341, 1 },
|
|
{AArch64_LD2i16_POST, 342, 1 },
|
|
{AArch64_LD2i32_POST, 343, 1 },
|
|
{AArch64_LD2i64_POST, 344, 1 },
|
|
{AArch64_LD2i8_POST, 345, 1 },
|
|
{AArch64_LD3B_IMM, 346, 1 },
|
|
{AArch64_LD3D_IMM, 347, 1 },
|
|
{AArch64_LD3H_IMM, 348, 1 },
|
|
{AArch64_LD3Rv16b_POST, 349, 1 },
|
|
{AArch64_LD3Rv1d_POST, 350, 1 },
|
|
{AArch64_LD3Rv2d_POST, 351, 1 },
|
|
{AArch64_LD3Rv2s_POST, 352, 1 },
|
|
{AArch64_LD3Rv4h_POST, 353, 1 },
|
|
{AArch64_LD3Rv4s_POST, 354, 1 },
|
|
{AArch64_LD3Rv8b_POST, 355, 1 },
|
|
{AArch64_LD3Rv8h_POST, 356, 1 },
|
|
{AArch64_LD3Threev16b_POST, 357, 1 },
|
|
{AArch64_LD3Threev2d_POST, 358, 1 },
|
|
{AArch64_LD3Threev2s_POST, 359, 1 },
|
|
{AArch64_LD3Threev4h_POST, 360, 1 },
|
|
{AArch64_LD3Threev4s_POST, 361, 1 },
|
|
{AArch64_LD3Threev8b_POST, 362, 1 },
|
|
{AArch64_LD3Threev8h_POST, 363, 1 },
|
|
{AArch64_LD3W_IMM, 364, 1 },
|
|
{AArch64_LD3i16_POST, 365, 1 },
|
|
{AArch64_LD3i32_POST, 366, 1 },
|
|
{AArch64_LD3i64_POST, 367, 1 },
|
|
{AArch64_LD3i8_POST, 368, 1 },
|
|
{AArch64_LD4B_IMM, 369, 1 },
|
|
{AArch64_LD4D_IMM, 370, 1 },
|
|
{AArch64_LD4Fourv16b_POST, 371, 1 },
|
|
{AArch64_LD4Fourv2d_POST, 372, 1 },
|
|
{AArch64_LD4Fourv2s_POST, 373, 1 },
|
|
{AArch64_LD4Fourv4h_POST, 374, 1 },
|
|
{AArch64_LD4Fourv4s_POST, 375, 1 },
|
|
{AArch64_LD4Fourv8b_POST, 376, 1 },
|
|
{AArch64_LD4Fourv8h_POST, 377, 1 },
|
|
{AArch64_LD4H_IMM, 378, 1 },
|
|
{AArch64_LD4Rv16b_POST, 379, 1 },
|
|
{AArch64_LD4Rv1d_POST, 380, 1 },
|
|
{AArch64_LD4Rv2d_POST, 381, 1 },
|
|
{AArch64_LD4Rv2s_POST, 382, 1 },
|
|
{AArch64_LD4Rv4h_POST, 383, 1 },
|
|
{AArch64_LD4Rv4s_POST, 384, 1 },
|
|
{AArch64_LD4Rv8b_POST, 385, 1 },
|
|
{AArch64_LD4Rv8h_POST, 386, 1 },
|
|
{AArch64_LD4W_IMM, 387, 1 },
|
|
{AArch64_LD4i16_POST, 388, 1 },
|
|
{AArch64_LD4i32_POST, 389, 1 },
|
|
{AArch64_LD4i64_POST, 390, 1 },
|
|
{AArch64_LD4i8_POST, 391, 1 },
|
|
{AArch64_LDADDB, 392, 1 },
|
|
{AArch64_LDADDH, 393, 1 },
|
|
{AArch64_LDADDLB, 394, 1 },
|
|
{AArch64_LDADDLH, 395, 1 },
|
|
{AArch64_LDADDLW, 396, 1 },
|
|
{AArch64_LDADDLX, 397, 1 },
|
|
{AArch64_LDADDW, 398, 1 },
|
|
{AArch64_LDADDX, 399, 1 },
|
|
{AArch64_LDAPURBi, 400, 1 },
|
|
{AArch64_LDAPURHi, 401, 1 },
|
|
{AArch64_LDAPURSBWi, 402, 1 },
|
|
{AArch64_LDAPURSBXi, 403, 1 },
|
|
{AArch64_LDAPURSHWi, 404, 1 },
|
|
{AArch64_LDAPURSHXi, 405, 1 },
|
|
{AArch64_LDAPURSWi, 406, 1 },
|
|
{AArch64_LDAPURXi, 407, 1 },
|
|
{AArch64_LDAPURi, 408, 1 },
|
|
{AArch64_LDCLRB, 409, 1 },
|
|
{AArch64_LDCLRH, 410, 1 },
|
|
{AArch64_LDCLRLB, 411, 1 },
|
|
{AArch64_LDCLRLH, 412, 1 },
|
|
{AArch64_LDCLRLW, 413, 1 },
|
|
{AArch64_LDCLRLX, 414, 1 },
|
|
{AArch64_LDCLRW, 415, 1 },
|
|
{AArch64_LDCLRX, 416, 1 },
|
|
{AArch64_LDEORB, 417, 1 },
|
|
{AArch64_LDEORH, 418, 1 },
|
|
{AArch64_LDEORLB, 419, 1 },
|
|
{AArch64_LDEORLH, 420, 1 },
|
|
{AArch64_LDEORLW, 421, 1 },
|
|
{AArch64_LDEORLX, 422, 1 },
|
|
{AArch64_LDEORW, 423, 1 },
|
|
{AArch64_LDEORX, 424, 1 },
|
|
{AArch64_LDFF1B_D_REAL, 425, 1 },
|
|
{AArch64_LDFF1B_H_REAL, 426, 1 },
|
|
{AArch64_LDFF1B_REAL, 427, 1 },
|
|
{AArch64_LDFF1B_S_REAL, 428, 1 },
|
|
{AArch64_LDFF1D_REAL, 429, 1 },
|
|
{AArch64_LDFF1H_D_REAL, 430, 1 },
|
|
{AArch64_LDFF1H_REAL, 431, 1 },
|
|
{AArch64_LDFF1H_S_REAL, 432, 1 },
|
|
{AArch64_LDFF1SB_D_REAL, 433, 1 },
|
|
{AArch64_LDFF1SB_H_REAL, 434, 1 },
|
|
{AArch64_LDFF1SB_S_REAL, 435, 1 },
|
|
{AArch64_LDFF1SH_D_REAL, 436, 1 },
|
|
{AArch64_LDFF1SH_S_REAL, 437, 1 },
|
|
{AArch64_LDFF1SW_D_REAL, 438, 1 },
|
|
{AArch64_LDFF1W_D_REAL, 439, 1 },
|
|
{AArch64_LDFF1W_REAL, 440, 1 },
|
|
{AArch64_LDG, 441, 1 },
|
|
{AArch64_LDNF1B_D_IMM_REAL, 442, 1 },
|
|
{AArch64_LDNF1B_H_IMM_REAL, 443, 1 },
|
|
{AArch64_LDNF1B_IMM_REAL, 444, 1 },
|
|
{AArch64_LDNF1B_S_IMM_REAL, 445, 1 },
|
|
{AArch64_LDNF1D_IMM_REAL, 446, 1 },
|
|
{AArch64_LDNF1H_D_IMM_REAL, 447, 1 },
|
|
{AArch64_LDNF1H_IMM_REAL, 448, 1 },
|
|
{AArch64_LDNF1H_S_IMM_REAL, 449, 1 },
|
|
{AArch64_LDNF1SB_D_IMM_REAL, 450, 1 },
|
|
{AArch64_LDNF1SB_H_IMM_REAL, 451, 1 },
|
|
{AArch64_LDNF1SB_S_IMM_REAL, 452, 1 },
|
|
{AArch64_LDNF1SH_D_IMM_REAL, 453, 1 },
|
|
{AArch64_LDNF1SH_S_IMM_REAL, 454, 1 },
|
|
{AArch64_LDNF1SW_D_IMM_REAL, 455, 1 },
|
|
{AArch64_LDNF1W_D_IMM_REAL, 456, 1 },
|
|
{AArch64_LDNF1W_IMM_REAL, 457, 1 },
|
|
{AArch64_LDNPDi, 458, 1 },
|
|
{AArch64_LDNPQi, 459, 1 },
|
|
{AArch64_LDNPSi, 460, 1 },
|
|
{AArch64_LDNPWi, 461, 1 },
|
|
{AArch64_LDNPXi, 462, 1 },
|
|
{AArch64_LDNT1B_ZRI, 463, 1 },
|
|
{AArch64_LDNT1B_ZZR_D_REAL, 464, 1 },
|
|
{AArch64_LDNT1B_ZZR_S_REAL, 465, 1 },
|
|
{AArch64_LDNT1D_ZRI, 466, 1 },
|
|
{AArch64_LDNT1D_ZZR_D_REAL, 467, 1 },
|
|
{AArch64_LDNT1H_ZRI, 468, 1 },
|
|
{AArch64_LDNT1H_ZZR_D_REAL, 469, 1 },
|
|
{AArch64_LDNT1H_ZZR_S_REAL, 470, 1 },
|
|
{AArch64_LDNT1SB_ZZR_D_REAL, 471, 1 },
|
|
{AArch64_LDNT1SB_ZZR_S_REAL, 472, 1 },
|
|
{AArch64_LDNT1SH_ZZR_D_REAL, 473, 1 },
|
|
{AArch64_LDNT1SH_ZZR_S_REAL, 474, 1 },
|
|
{AArch64_LDNT1SW_ZZR_D_REAL, 475, 1 },
|
|
{AArch64_LDNT1W_ZRI, 476, 1 },
|
|
{AArch64_LDNT1W_ZZR_D_REAL, 477, 1 },
|
|
{AArch64_LDNT1W_ZZR_S_REAL, 478, 1 },
|
|
{AArch64_LDPDi, 479, 1 },
|
|
{AArch64_LDPQi, 480, 1 },
|
|
{AArch64_LDPSWi, 481, 1 },
|
|
{AArch64_LDPSi, 482, 1 },
|
|
{AArch64_LDPWi, 483, 1 },
|
|
{AArch64_LDPXi, 484, 1 },
|
|
{AArch64_LDRAAindexed, 485, 1 },
|
|
{AArch64_LDRABindexed, 486, 1 },
|
|
{AArch64_LDRBBroX, 487, 1 },
|
|
{AArch64_LDRBBui, 488, 1 },
|
|
{AArch64_LDRBroX, 489, 1 },
|
|
{AArch64_LDRBui, 490, 1 },
|
|
{AArch64_LDRDroX, 491, 1 },
|
|
{AArch64_LDRDui, 492, 1 },
|
|
{AArch64_LDRHHroX, 493, 1 },
|
|
{AArch64_LDRHHui, 494, 1 },
|
|
{AArch64_LDRHroX, 495, 1 },
|
|
{AArch64_LDRHui, 496, 1 },
|
|
{AArch64_LDRQroX, 497, 1 },
|
|
{AArch64_LDRQui, 498, 1 },
|
|
{AArch64_LDRSBWroX, 499, 1 },
|
|
{AArch64_LDRSBWui, 500, 1 },
|
|
{AArch64_LDRSBXroX, 501, 1 },
|
|
{AArch64_LDRSBXui, 502, 1 },
|
|
{AArch64_LDRSHWroX, 503, 1 },
|
|
{AArch64_LDRSHWui, 504, 1 },
|
|
{AArch64_LDRSHXroX, 505, 1 },
|
|
{AArch64_LDRSHXui, 506, 1 },
|
|
{AArch64_LDRSWroX, 507, 1 },
|
|
{AArch64_LDRSWui, 508, 1 },
|
|
{AArch64_LDRSroX, 509, 1 },
|
|
{AArch64_LDRSui, 510, 1 },
|
|
{AArch64_LDRWroX, 511, 1 },
|
|
{AArch64_LDRWui, 512, 1 },
|
|
{AArch64_LDRXroX, 513, 1 },
|
|
{AArch64_LDRXui, 514, 1 },
|
|
{AArch64_LDR_PXI, 515, 1 },
|
|
{AArch64_LDR_ZA, 516, 1 },
|
|
{AArch64_LDR_ZXI, 517, 1 },
|
|
{AArch64_LDSETB, 518, 1 },
|
|
{AArch64_LDSETH, 519, 1 },
|
|
{AArch64_LDSETLB, 520, 1 },
|
|
{AArch64_LDSETLH, 521, 1 },
|
|
{AArch64_LDSETLW, 522, 1 },
|
|
{AArch64_LDSETLX, 523, 1 },
|
|
{AArch64_LDSETW, 524, 1 },
|
|
{AArch64_LDSETX, 525, 1 },
|
|
{AArch64_LDSMAXB, 526, 1 },
|
|
{AArch64_LDSMAXH, 527, 1 },
|
|
{AArch64_LDSMAXLB, 528, 1 },
|
|
{AArch64_LDSMAXLH, 529, 1 },
|
|
{AArch64_LDSMAXLW, 530, 1 },
|
|
{AArch64_LDSMAXLX, 531, 1 },
|
|
{AArch64_LDSMAXW, 532, 1 },
|
|
{AArch64_LDSMAXX, 533, 1 },
|
|
{AArch64_LDSMINB, 534, 1 },
|
|
{AArch64_LDSMINH, 535, 1 },
|
|
{AArch64_LDSMINLB, 536, 1 },
|
|
{AArch64_LDSMINLH, 537, 1 },
|
|
{AArch64_LDSMINLW, 538, 1 },
|
|
{AArch64_LDSMINLX, 539, 1 },
|
|
{AArch64_LDSMINW, 540, 1 },
|
|
{AArch64_LDSMINX, 541, 1 },
|
|
{AArch64_LDTRBi, 542, 1 },
|
|
{AArch64_LDTRHi, 543, 1 },
|
|
{AArch64_LDTRSBWi, 544, 1 },
|
|
{AArch64_LDTRSBXi, 545, 1 },
|
|
{AArch64_LDTRSHWi, 546, 1 },
|
|
{AArch64_LDTRSHXi, 547, 1 },
|
|
{AArch64_LDTRSWi, 548, 1 },
|
|
{AArch64_LDTRWi, 549, 1 },
|
|
{AArch64_LDTRXi, 550, 1 },
|
|
{AArch64_LDUMAXB, 551, 1 },
|
|
{AArch64_LDUMAXH, 552, 1 },
|
|
{AArch64_LDUMAXLB, 553, 1 },
|
|
{AArch64_LDUMAXLH, 554, 1 },
|
|
{AArch64_LDUMAXLW, 555, 1 },
|
|
{AArch64_LDUMAXLX, 556, 1 },
|
|
{AArch64_LDUMAXW, 557, 1 },
|
|
{AArch64_LDUMAXX, 558, 1 },
|
|
{AArch64_LDUMINB, 559, 1 },
|
|
{AArch64_LDUMINH, 560, 1 },
|
|
{AArch64_LDUMINLB, 561, 1 },
|
|
{AArch64_LDUMINLH, 562, 1 },
|
|
{AArch64_LDUMINLW, 563, 1 },
|
|
{AArch64_LDUMINLX, 564, 1 },
|
|
{AArch64_LDUMINW, 565, 1 },
|
|
{AArch64_LDUMINX, 566, 1 },
|
|
{AArch64_LDURBBi, 567, 1 },
|
|
{AArch64_LDURBi, 568, 1 },
|
|
{AArch64_LDURDi, 569, 1 },
|
|
{AArch64_LDURHHi, 570, 1 },
|
|
{AArch64_LDURHi, 571, 1 },
|
|
{AArch64_LDURQi, 572, 1 },
|
|
{AArch64_LDURSBWi, 573, 1 },
|
|
{AArch64_LDURSBXi, 574, 1 },
|
|
{AArch64_LDURSHWi, 575, 1 },
|
|
{AArch64_LDURSHXi, 576, 1 },
|
|
{AArch64_LDURSWi, 577, 1 },
|
|
{AArch64_LDURSi, 578, 1 },
|
|
{AArch64_LDURWi, 579, 1 },
|
|
{AArch64_LDURXi, 580, 1 },
|
|
{AArch64_MADDWrrr, 581, 1 },
|
|
{AArch64_MADDXrrr, 582, 1 },
|
|
{AArch64_MSRpstatesvcrImm1, 583, 6 },
|
|
{AArch64_MSUBWrrr, 589, 1 },
|
|
{AArch64_MSUBXrrr, 590, 1 },
|
|
{AArch64_NOTv16i8, 591, 1 },
|
|
{AArch64_NOTv8i8, 592, 1 },
|
|
{AArch64_ORNWrs, 593, 3 },
|
|
{AArch64_ORNXrs, 596, 3 },
|
|
{AArch64_ORRS_PPzPP, 599, 1 },
|
|
{AArch64_ORRWrs, 600, 2 },
|
|
{AArch64_ORRXrs, 602, 2 },
|
|
{AArch64_ORR_PPzPP, 604, 1 },
|
|
{AArch64_ORR_ZI, 605, 3 },
|
|
{AArch64_ORR_ZZZ, 608, 1 },
|
|
{AArch64_ORRv16i8, 609, 1 },
|
|
{AArch64_ORRv8i8, 610, 1 },
|
|
{AArch64_PACIA1716, 611, 1 },
|
|
{AArch64_PACIASP, 612, 1 },
|
|
{AArch64_PACIAZ, 613, 1 },
|
|
{AArch64_PACIB1716, 614, 1 },
|
|
{AArch64_PACIBSP, 615, 1 },
|
|
{AArch64_PACIBZ, 616, 1 },
|
|
{AArch64_PRFB_D_PZI, 617, 1 },
|
|
{AArch64_PRFB_PRI, 618, 1 },
|
|
{AArch64_PRFB_S_PZI, 619, 1 },
|
|
{AArch64_PRFD_D_PZI, 620, 1 },
|
|
{AArch64_PRFD_PRI, 621, 1 },
|
|
{AArch64_PRFD_S_PZI, 622, 1 },
|
|
{AArch64_PRFH_D_PZI, 623, 1 },
|
|
{AArch64_PRFH_PRI, 624, 1 },
|
|
{AArch64_PRFH_S_PZI, 625, 1 },
|
|
{AArch64_PRFMroX, 626, 1 },
|
|
{AArch64_PRFMui, 627, 1 },
|
|
{AArch64_PRFUMi, 628, 1 },
|
|
{AArch64_PRFW_D_PZI, 629, 1 },
|
|
{AArch64_PRFW_PRI, 630, 1 },
|
|
{AArch64_PRFW_S_PZI, 631, 1 },
|
|
{AArch64_PTRUES_B, 632, 1 },
|
|
{AArch64_PTRUES_D, 633, 1 },
|
|
{AArch64_PTRUES_H, 634, 1 },
|
|
{AArch64_PTRUES_S, 635, 1 },
|
|
{AArch64_PTRUE_B, 636, 1 },
|
|
{AArch64_PTRUE_D, 637, 1 },
|
|
{AArch64_PTRUE_H, 638, 1 },
|
|
{AArch64_PTRUE_S, 639, 1 },
|
|
{AArch64_RET, 640, 1 },
|
|
{AArch64_SBCSWr, 641, 1 },
|
|
{AArch64_SBCSXr, 642, 1 },
|
|
{AArch64_SBCWr, 643, 1 },
|
|
{AArch64_SBCXr, 644, 1 },
|
|
{AArch64_SBFMWri, 645, 3 },
|
|
{AArch64_SBFMXri, 648, 4 },
|
|
{AArch64_SEL_PPPP, 652, 1 },
|
|
{AArch64_SEL_ZPZZ_B, 653, 1 },
|
|
{AArch64_SEL_ZPZZ_D, 654, 1 },
|
|
{AArch64_SEL_ZPZZ_H, 655, 1 },
|
|
{AArch64_SEL_ZPZZ_S, 656, 1 },
|
|
{AArch64_SMADDLrrr, 657, 1 },
|
|
{AArch64_SMSUBLrrr, 658, 1 },
|
|
{AArch64_SQDECB_XPiI, 659, 2 },
|
|
{AArch64_SQDECB_XPiWdI, 661, 2 },
|
|
{AArch64_SQDECD_XPiI, 663, 2 },
|
|
{AArch64_SQDECD_XPiWdI, 665, 2 },
|
|
{AArch64_SQDECD_ZPiI, 667, 2 },
|
|
{AArch64_SQDECH_XPiI, 669, 2 },
|
|
{AArch64_SQDECH_XPiWdI, 671, 2 },
|
|
{AArch64_SQDECH_ZPiI, 673, 2 },
|
|
{AArch64_SQDECW_XPiI, 675, 2 },
|
|
{AArch64_SQDECW_XPiWdI, 677, 2 },
|
|
{AArch64_SQDECW_ZPiI, 679, 2 },
|
|
{AArch64_SQINCB_XPiI, 681, 2 },
|
|
{AArch64_SQINCB_XPiWdI, 683, 2 },
|
|
{AArch64_SQINCD_XPiI, 685, 2 },
|
|
{AArch64_SQINCD_XPiWdI, 687, 2 },
|
|
{AArch64_SQINCD_ZPiI, 689, 2 },
|
|
{AArch64_SQINCH_XPiI, 691, 2 },
|
|
{AArch64_SQINCH_XPiWdI, 693, 2 },
|
|
{AArch64_SQINCH_ZPiI, 695, 2 },
|
|
{AArch64_SQINCW_XPiI, 697, 2 },
|
|
{AArch64_SQINCW_XPiWdI, 699, 2 },
|
|
{AArch64_SQINCW_ZPiI, 701, 2 },
|
|
{AArch64_SST1B_D_IMM, 703, 1 },
|
|
{AArch64_SST1B_S_IMM, 704, 1 },
|
|
{AArch64_SST1D_IMM, 705, 1 },
|
|
{AArch64_SST1H_D_IMM, 706, 1 },
|
|
{AArch64_SST1H_S_IMM, 707, 1 },
|
|
{AArch64_SST1W_D_IMM, 708, 1 },
|
|
{AArch64_SST1W_IMM, 709, 1 },
|
|
{AArch64_ST1B_D_IMM, 710, 1 },
|
|
{AArch64_ST1B_H_IMM, 711, 1 },
|
|
{AArch64_ST1B_IMM, 712, 1 },
|
|
{AArch64_ST1B_S_IMM, 713, 1 },
|
|
{AArch64_ST1D_IMM, 714, 1 },
|
|
{AArch64_ST1Fourv16b_POST, 715, 1 },
|
|
{AArch64_ST1Fourv1d_POST, 716, 1 },
|
|
{AArch64_ST1Fourv2d_POST, 717, 1 },
|
|
{AArch64_ST1Fourv2s_POST, 718, 1 },
|
|
{AArch64_ST1Fourv4h_POST, 719, 1 },
|
|
{AArch64_ST1Fourv4s_POST, 720, 1 },
|
|
{AArch64_ST1Fourv8b_POST, 721, 1 },
|
|
{AArch64_ST1Fourv8h_POST, 722, 1 },
|
|
{AArch64_ST1H_D_IMM, 723, 1 },
|
|
{AArch64_ST1H_IMM, 724, 1 },
|
|
{AArch64_ST1H_S_IMM, 725, 1 },
|
|
{AArch64_ST1Onev16b_POST, 726, 1 },
|
|
{AArch64_ST1Onev1d_POST, 727, 1 },
|
|
{AArch64_ST1Onev2d_POST, 728, 1 },
|
|
{AArch64_ST1Onev2s_POST, 729, 1 },
|
|
{AArch64_ST1Onev4h_POST, 730, 1 },
|
|
{AArch64_ST1Onev4s_POST, 731, 1 },
|
|
{AArch64_ST1Onev8b_POST, 732, 1 },
|
|
{AArch64_ST1Onev8h_POST, 733, 1 },
|
|
{AArch64_ST1Threev16b_POST, 734, 1 },
|
|
{AArch64_ST1Threev1d_POST, 735, 1 },
|
|
{AArch64_ST1Threev2d_POST, 736, 1 },
|
|
{AArch64_ST1Threev2s_POST, 737, 1 },
|
|
{AArch64_ST1Threev4h_POST, 738, 1 },
|
|
{AArch64_ST1Threev4s_POST, 739, 1 },
|
|
{AArch64_ST1Threev8b_POST, 740, 1 },
|
|
{AArch64_ST1Threev8h_POST, 741, 1 },
|
|
{AArch64_ST1Twov16b_POST, 742, 1 },
|
|
{AArch64_ST1Twov1d_POST, 743, 1 },
|
|
{AArch64_ST1Twov2d_POST, 744, 1 },
|
|
{AArch64_ST1Twov2s_POST, 745, 1 },
|
|
{AArch64_ST1Twov4h_POST, 746, 1 },
|
|
{AArch64_ST1Twov4s_POST, 747, 1 },
|
|
{AArch64_ST1Twov8b_POST, 748, 1 },
|
|
{AArch64_ST1Twov8h_POST, 749, 1 },
|
|
{AArch64_ST1W_D_IMM, 750, 1 },
|
|
{AArch64_ST1W_IMM, 751, 1 },
|
|
{AArch64_ST1_MXIPXX_H_B, 752, 1 },
|
|
{AArch64_ST1_MXIPXX_H_D, 753, 1 },
|
|
{AArch64_ST1_MXIPXX_H_H, 754, 1 },
|
|
{AArch64_ST1_MXIPXX_H_Q, 755, 1 },
|
|
{AArch64_ST1_MXIPXX_H_S, 756, 1 },
|
|
{AArch64_ST1_MXIPXX_V_B, 757, 1 },
|
|
{AArch64_ST1_MXIPXX_V_D, 758, 1 },
|
|
{AArch64_ST1_MXIPXX_V_H, 759, 1 },
|
|
{AArch64_ST1_MXIPXX_V_Q, 760, 1 },
|
|
{AArch64_ST1_MXIPXX_V_S, 761, 1 },
|
|
{AArch64_ST1i16_POST, 762, 1 },
|
|
{AArch64_ST1i32_POST, 763, 1 },
|
|
{AArch64_ST1i64_POST, 764, 1 },
|
|
{AArch64_ST1i8_POST, 765, 1 },
|
|
{AArch64_ST2B_IMM, 766, 1 },
|
|
{AArch64_ST2D_IMM, 767, 1 },
|
|
{AArch64_ST2GOffset, 768, 1 },
|
|
{AArch64_ST2H_IMM, 769, 1 },
|
|
{AArch64_ST2Twov16b_POST, 770, 1 },
|
|
{AArch64_ST2Twov2d_POST, 771, 1 },
|
|
{AArch64_ST2Twov2s_POST, 772, 1 },
|
|
{AArch64_ST2Twov4h_POST, 773, 1 },
|
|
{AArch64_ST2Twov4s_POST, 774, 1 },
|
|
{AArch64_ST2Twov8b_POST, 775, 1 },
|
|
{AArch64_ST2Twov8h_POST, 776, 1 },
|
|
{AArch64_ST2W_IMM, 777, 1 },
|
|
{AArch64_ST2i16_POST, 778, 1 },
|
|
{AArch64_ST2i32_POST, 779, 1 },
|
|
{AArch64_ST2i64_POST, 780, 1 },
|
|
{AArch64_ST2i8_POST, 781, 1 },
|
|
{AArch64_ST3B_IMM, 782, 1 },
|
|
{AArch64_ST3D_IMM, 783, 1 },
|
|
{AArch64_ST3H_IMM, 784, 1 },
|
|
{AArch64_ST3Threev16b_POST, 785, 1 },
|
|
{AArch64_ST3Threev2d_POST, 786, 1 },
|
|
{AArch64_ST3Threev2s_POST, 787, 1 },
|
|
{AArch64_ST3Threev4h_POST, 788, 1 },
|
|
{AArch64_ST3Threev4s_POST, 789, 1 },
|
|
{AArch64_ST3Threev8b_POST, 790, 1 },
|
|
{AArch64_ST3Threev8h_POST, 791, 1 },
|
|
{AArch64_ST3W_IMM, 792, 1 },
|
|
{AArch64_ST3i16_POST, 793, 1 },
|
|
{AArch64_ST3i32_POST, 794, 1 },
|
|
{AArch64_ST3i64_POST, 795, 1 },
|
|
{AArch64_ST3i8_POST, 796, 1 },
|
|
{AArch64_ST4B_IMM, 797, 1 },
|
|
{AArch64_ST4D_IMM, 798, 1 },
|
|
{AArch64_ST4Fourv16b_POST, 799, 1 },
|
|
{AArch64_ST4Fourv2d_POST, 800, 1 },
|
|
{AArch64_ST4Fourv2s_POST, 801, 1 },
|
|
{AArch64_ST4Fourv4h_POST, 802, 1 },
|
|
{AArch64_ST4Fourv4s_POST, 803, 1 },
|
|
{AArch64_ST4Fourv8b_POST, 804, 1 },
|
|
{AArch64_ST4Fourv8h_POST, 805, 1 },
|
|
{AArch64_ST4H_IMM, 806, 1 },
|
|
{AArch64_ST4W_IMM, 807, 1 },
|
|
{AArch64_ST4i16_POST, 808, 1 },
|
|
{AArch64_ST4i32_POST, 809, 1 },
|
|
{AArch64_ST4i64_POST, 810, 1 },
|
|
{AArch64_ST4i8_POST, 811, 1 },
|
|
{AArch64_STGOffset, 812, 1 },
|
|
{AArch64_STGPi, 813, 1 },
|
|
{AArch64_STLURBi, 814, 1 },
|
|
{AArch64_STLURHi, 815, 1 },
|
|
{AArch64_STLURWi, 816, 1 },
|
|
{AArch64_STLURXi, 817, 1 },
|
|
{AArch64_STNPDi, 818, 1 },
|
|
{AArch64_STNPQi, 819, 1 },
|
|
{AArch64_STNPSi, 820, 1 },
|
|
{AArch64_STNPWi, 821, 1 },
|
|
{AArch64_STNPXi, 822, 1 },
|
|
{AArch64_STNT1B_ZRI, 823, 1 },
|
|
{AArch64_STNT1B_ZZR_D_REAL, 824, 1 },
|
|
{AArch64_STNT1B_ZZR_S_REAL, 825, 1 },
|
|
{AArch64_STNT1D_ZRI, 826, 1 },
|
|
{AArch64_STNT1D_ZZR_D_REAL, 827, 1 },
|
|
{AArch64_STNT1H_ZRI, 828, 1 },
|
|
{AArch64_STNT1H_ZZR_D_REAL, 829, 1 },
|
|
{AArch64_STNT1H_ZZR_S_REAL, 830, 1 },
|
|
{AArch64_STNT1W_ZRI, 831, 1 },
|
|
{AArch64_STNT1W_ZZR_D_REAL, 832, 1 },
|
|
{AArch64_STNT1W_ZZR_S_REAL, 833, 1 },
|
|
{AArch64_STPDi, 834, 1 },
|
|
{AArch64_STPQi, 835, 1 },
|
|
{AArch64_STPSi, 836, 1 },
|
|
{AArch64_STPWi, 837, 1 },
|
|
{AArch64_STPXi, 838, 1 },
|
|
{AArch64_STRBBroX, 839, 1 },
|
|
{AArch64_STRBBui, 840, 1 },
|
|
{AArch64_STRBroX, 841, 1 },
|
|
{AArch64_STRBui, 842, 1 },
|
|
{AArch64_STRDroX, 843, 1 },
|
|
{AArch64_STRDui, 844, 1 },
|
|
{AArch64_STRHHroX, 845, 1 },
|
|
{AArch64_STRHHui, 846, 1 },
|
|
{AArch64_STRHroX, 847, 1 },
|
|
{AArch64_STRHui, 848, 1 },
|
|
{AArch64_STRQroX, 849, 1 },
|
|
{AArch64_STRQui, 850, 1 },
|
|
{AArch64_STRSroX, 851, 1 },
|
|
{AArch64_STRSui, 852, 1 },
|
|
{AArch64_STRWroX, 853, 1 },
|
|
{AArch64_STRWui, 854, 1 },
|
|
{AArch64_STRXroX, 855, 1 },
|
|
{AArch64_STRXui, 856, 1 },
|
|
{AArch64_STR_PXI, 857, 1 },
|
|
{AArch64_STR_ZA, 858, 1 },
|
|
{AArch64_STR_ZXI, 859, 1 },
|
|
{AArch64_STTRBi, 860, 1 },
|
|
{AArch64_STTRHi, 861, 1 },
|
|
{AArch64_STTRWi, 862, 1 },
|
|
{AArch64_STTRXi, 863, 1 },
|
|
{AArch64_STURBBi, 864, 1 },
|
|
{AArch64_STURBi, 865, 1 },
|
|
{AArch64_STURDi, 866, 1 },
|
|
{AArch64_STURHHi, 867, 1 },
|
|
{AArch64_STURHi, 868, 1 },
|
|
{AArch64_STURQi, 869, 1 },
|
|
{AArch64_STURSi, 870, 1 },
|
|
{AArch64_STURWi, 871, 1 },
|
|
{AArch64_STURXi, 872, 1 },
|
|
{AArch64_STZ2GOffset, 873, 1 },
|
|
{AArch64_STZGOffset, 874, 1 },
|
|
{AArch64_SUBSWri, 875, 1 },
|
|
{AArch64_SUBSWrs, 876, 5 },
|
|
{AArch64_SUBSWrx, 881, 3 },
|
|
{AArch64_SUBSXri, 884, 1 },
|
|
{AArch64_SUBSXrs, 885, 5 },
|
|
{AArch64_SUBSXrx, 890, 1 },
|
|
{AArch64_SUBSXrx64, 891, 3 },
|
|
{AArch64_SUBWrs, 894, 3 },
|
|
{AArch64_SUBWrx, 897, 2 },
|
|
{AArch64_SUBXrs, 899, 3 },
|
|
{AArch64_SUBXrx64, 902, 2 },
|
|
{AArch64_SYSxt, 904, 1 },
|
|
{AArch64_UBFMWri, 905, 3 },
|
|
{AArch64_UBFMXri, 908, 4 },
|
|
{AArch64_UMADDLrrr, 912, 1 },
|
|
{AArch64_UMOVvi32, 913, 1 },
|
|
{AArch64_UMOVvi32_idx0, 914, 1 },
|
|
{AArch64_UMOVvi64, 915, 1 },
|
|
{AArch64_UMOVvi64_idx0, 916, 1 },
|
|
{AArch64_UMSUBLrrr, 917, 1 },
|
|
{AArch64_UQDECB_WPiI, 918, 2 },
|
|
{AArch64_UQDECB_XPiI, 920, 2 },
|
|
{AArch64_UQDECD_WPiI, 922, 2 },
|
|
{AArch64_UQDECD_XPiI, 924, 2 },
|
|
{AArch64_UQDECD_ZPiI, 926, 2 },
|
|
{AArch64_UQDECH_WPiI, 928, 2 },
|
|
{AArch64_UQDECH_XPiI, 930, 2 },
|
|
{AArch64_UQDECH_ZPiI, 932, 2 },
|
|
{AArch64_UQDECW_WPiI, 934, 2 },
|
|
{AArch64_UQDECW_XPiI, 936, 2 },
|
|
{AArch64_UQDECW_ZPiI, 938, 2 },
|
|
{AArch64_UQINCB_WPiI, 940, 2 },
|
|
{AArch64_UQINCB_XPiI, 942, 2 },
|
|
{AArch64_UQINCD_WPiI, 944, 2 },
|
|
{AArch64_UQINCD_XPiI, 946, 2 },
|
|
{AArch64_UQINCD_ZPiI, 948, 2 },
|
|
{AArch64_UQINCH_WPiI, 950, 2 },
|
|
{AArch64_UQINCH_XPiI, 952, 2 },
|
|
{AArch64_UQINCH_ZPiI, 954, 2 },
|
|
{AArch64_UQINCW_WPiI, 956, 2 },
|
|
{AArch64_UQINCW_XPiI, 958, 2 },
|
|
{AArch64_UQINCW_ZPiI, 960, 2 },
|
|
{AArch64_XPACLRI, 962, 1 },
|
|
{AArch64_ZERO_M, 963, 15 },
|
|
};
|
|
|
|
static const AliasPattern Patterns[] = {
|
|
// AArch64_ADDSWri - 0
|
|
{0, 0, 4, 2 },
|
|
// AArch64_ADDSWrs - 1
|
|
{13, 2, 4, 4 },
|
|
{24, 6, 4, 3 },
|
|
{39, 9, 4, 4 },
|
|
// AArch64_ADDSWrx - 4
|
|
{13, 13, 4, 4 },
|
|
{55, 17, 4, 3 },
|
|
{39, 20, 4, 4 },
|
|
// AArch64_ADDSXri - 7
|
|
{0, 24, 4, 2 },
|
|
// AArch64_ADDSXrs - 8
|
|
{13, 26, 4, 4 },
|
|
{24, 30, 4, 3 },
|
|
{39, 33, 4, 4 },
|
|
// AArch64_ADDSXrx - 11
|
|
{55, 37, 4, 3 },
|
|
// AArch64_ADDSXrx64 - 12
|
|
{13, 40, 4, 4 },
|
|
{55, 44, 4, 3 },
|
|
{39, 47, 4, 4 },
|
|
// AArch64_ADDWri - 15
|
|
{70, 51, 4, 4 },
|
|
{70, 55, 4, 4 },
|
|
// AArch64_ADDWrs - 17
|
|
{81, 59, 4, 4 },
|
|
// AArch64_ADDWrx - 18
|
|
{81, 63, 4, 4 },
|
|
{81, 67, 4, 4 },
|
|
// AArch64_ADDXri - 20
|
|
{70, 71, 4, 4 },
|
|
{70, 75, 4, 4 },
|
|
// AArch64_ADDXrs - 22
|
|
{81, 79, 4, 4 },
|
|
// AArch64_ADDXrx64 - 23
|
|
{81, 83, 4, 4 },
|
|
{81, 87, 4, 4 },
|
|
// AArch64_ANDSWri - 25
|
|
{96, 91, 3, 2 },
|
|
// AArch64_ANDSWrs - 26
|
|
{109, 93, 4, 4 },
|
|
{120, 97, 4, 3 },
|
|
{135, 100, 4, 4 },
|
|
// AArch64_ANDSXri - 29
|
|
{151, 104, 3, 2 },
|
|
// AArch64_ANDSXrs - 30
|
|
{109, 106, 4, 4 },
|
|
{120, 110, 4, 3 },
|
|
{135, 113, 4, 4 },
|
|
// AArch64_ANDS_PPzPP - 33
|
|
{164, 117, 4, 7 },
|
|
// AArch64_ANDWrs - 34
|
|
{188, 124, 4, 4 },
|
|
// AArch64_ANDXrs - 35
|
|
{188, 128, 4, 4 },
|
|
// AArch64_AND_PPzPP - 36
|
|
{203, 132, 4, 7 },
|
|
// AArch64_AND_ZI - 37
|
|
{226, 139, 3, 6 },
|
|
{247, 145, 3, 6 },
|
|
{268, 151, 3, 6 },
|
|
// AArch64_AUTIA1716 - 40
|
|
{289, 157, 0, 1 },
|
|
// AArch64_AUTIASP - 41
|
|
{299, 158, 0, 1 },
|
|
// AArch64_AUTIAZ - 42
|
|
{307, 159, 0, 1 },
|
|
// AArch64_AUTIB1716 - 43
|
|
{314, 160, 0, 1 },
|
|
// AArch64_AUTIBSP - 44
|
|
{324, 161, 0, 1 },
|
|
// AArch64_AUTIBZ - 45
|
|
{332, 162, 0, 1 },
|
|
// AArch64_BICSWrs - 46
|
|
{339, 163, 4, 4 },
|
|
// AArch64_BICSXrs - 47
|
|
{339, 167, 4, 4 },
|
|
// AArch64_BICWrs - 48
|
|
{355, 171, 4, 4 },
|
|
// AArch64_BICXrs - 49
|
|
{355, 175, 4, 4 },
|
|
// AArch64_CLREX - 50
|
|
{370, 179, 1, 1 },
|
|
// AArch64_CNTB_XPiI - 51
|
|
{376, 180, 3, 6 },
|
|
{384, 186, 3, 6 },
|
|
// AArch64_CNTD_XPiI - 53
|
|
{398, 192, 3, 6 },
|
|
{406, 198, 3, 6 },
|
|
// AArch64_CNTH_XPiI - 55
|
|
{420, 204, 3, 6 },
|
|
{428, 210, 3, 6 },
|
|
// AArch64_CNTW_XPiI - 57
|
|
{442, 216, 3, 6 },
|
|
{450, 222, 3, 6 },
|
|
// AArch64_CPY_ZPmI_B - 59
|
|
{464, 228, 5, 6 },
|
|
// AArch64_CPY_ZPmI_D - 60
|
|
{487, 234, 5, 6 },
|
|
// AArch64_CPY_ZPmI_H - 61
|
|
{510, 240, 5, 6 },
|
|
// AArch64_CPY_ZPmI_S - 62
|
|
{533, 246, 5, 6 },
|
|
// AArch64_CPY_ZPmR_B - 63
|
|
{556, 252, 4, 7 },
|
|
// AArch64_CPY_ZPmR_D - 64
|
|
{577, 259, 4, 7 },
|
|
// AArch64_CPY_ZPmR_H - 65
|
|
{598, 266, 4, 7 },
|
|
// AArch64_CPY_ZPmR_S - 66
|
|
{619, 273, 4, 7 },
|
|
// AArch64_CPY_ZPmV_B - 67
|
|
{556, 280, 4, 7 },
|
|
// AArch64_CPY_ZPmV_D - 68
|
|
{577, 287, 4, 7 },
|
|
// AArch64_CPY_ZPmV_H - 69
|
|
{598, 294, 4, 7 },
|
|
// AArch64_CPY_ZPmV_S - 70
|
|
{619, 301, 4, 7 },
|
|
// AArch64_CPY_ZPzI_B - 71
|
|
{640, 308, 4, 5 },
|
|
// AArch64_CPY_ZPzI_D - 72
|
|
{663, 313, 4, 5 },
|
|
// AArch64_CPY_ZPzI_H - 73
|
|
{686, 318, 4, 5 },
|
|
// AArch64_CPY_ZPzI_S - 74
|
|
{709, 323, 4, 5 },
|
|
// AArch64_CSINCWr - 75
|
|
{732, 328, 4, 4 },
|
|
{746, 332, 4, 4 },
|
|
// AArch64_CSINCXr - 77
|
|
{732, 336, 4, 4 },
|
|
{746, 340, 4, 4 },
|
|
// AArch64_CSINVWr - 79
|
|
{764, 344, 4, 4 },
|
|
{779, 348, 4, 4 },
|
|
// AArch64_CSINVXr - 81
|
|
{764, 352, 4, 4 },
|
|
{779, 356, 4, 4 },
|
|
// AArch64_CSNEGWr - 83
|
|
{797, 360, 4, 4 },
|
|
// AArch64_CSNEGXr - 84
|
|
{797, 364, 4, 4 },
|
|
// AArch64_DCPS1 - 85
|
|
{815, 368, 1, 1 },
|
|
// AArch64_DCPS2 - 86
|
|
{821, 369, 1, 1 },
|
|
// AArch64_DCPS3 - 87
|
|
{827, 370, 1, 2 },
|
|
// AArch64_DECB_XPiI - 88
|
|
{833, 372, 4, 7 },
|
|
{841, 379, 4, 7 },
|
|
// AArch64_DECD_XPiI - 90
|
|
{855, 386, 4, 7 },
|
|
{863, 393, 4, 7 },
|
|
// AArch64_DECD_ZPiI - 92
|
|
{877, 400, 4, 7 },
|
|
{887, 407, 4, 7 },
|
|
// AArch64_DECH_XPiI - 94
|
|
{903, 414, 4, 7 },
|
|
{911, 421, 4, 7 },
|
|
// AArch64_DECH_ZPiI - 96
|
|
{925, 428, 4, 7 },
|
|
{935, 435, 4, 7 },
|
|
// AArch64_DECW_XPiI - 98
|
|
{951, 442, 4, 7 },
|
|
{959, 449, 4, 7 },
|
|
// AArch64_DECW_ZPiI - 100
|
|
{973, 456, 4, 7 },
|
|
{983, 463, 4, 7 },
|
|
// AArch64_DSB - 102
|
|
{999, 470, 1, 1 },
|
|
{1004, 471, 1, 1 },
|
|
{1010, 472, 1, 2 },
|
|
// AArch64_DUPM_ZI - 105
|
|
{1014, 474, 2, 5 },
|
|
{1029, 479, 2, 5 },
|
|
{1044, 484, 2, 5 },
|
|
{1059, 489, 2, 5 },
|
|
{1075, 494, 2, 5 },
|
|
{1091, 499, 2, 5 },
|
|
// AArch64_DUP_ZI_B - 111
|
|
{1107, 504, 3, 4 },
|
|
// AArch64_DUP_ZI_D - 112
|
|
{1122, 508, 3, 4 },
|
|
{1137, 512, 3, 6 },
|
|
// AArch64_DUP_ZI_H - 114
|
|
{1153, 518, 3, 4 },
|
|
{1168, 522, 3, 6 },
|
|
// AArch64_DUP_ZI_S - 116
|
|
{1184, 528, 3, 4 },
|
|
{1199, 532, 3, 6 },
|
|
// AArch64_DUP_ZR_B - 118
|
|
{1215, 538, 2, 5 },
|
|
// AArch64_DUP_ZR_D - 119
|
|
{1228, 543, 2, 5 },
|
|
// AArch64_DUP_ZR_H - 120
|
|
{1241, 548, 2, 5 },
|
|
// AArch64_DUP_ZR_S - 121
|
|
{1254, 553, 2, 5 },
|
|
// AArch64_DUP_ZZI_B - 122
|
|
{1267, 558, 3, 6 },
|
|
{1282, 564, 3, 5 },
|
|
// AArch64_DUP_ZZI_D - 124
|
|
{1301, 569, 3, 6 },
|
|
{1316, 575, 3, 5 },
|
|
// AArch64_DUP_ZZI_H - 126
|
|
{1335, 580, 3, 6 },
|
|
{1350, 586, 3, 5 },
|
|
// AArch64_DUP_ZZI_Q - 128
|
|
{1369, 591, 3, 6 },
|
|
{1384, 597, 3, 5 },
|
|
// AArch64_DUP_ZZI_S - 130
|
|
{1403, 602, 3, 6 },
|
|
{1418, 608, 3, 5 },
|
|
// AArch64_EONWrs - 132
|
|
{1437, 613, 4, 4 },
|
|
// AArch64_EONXrs - 133
|
|
{1437, 617, 4, 4 },
|
|
// AArch64_EORS_PPzPP - 134
|
|
{1452, 621, 4, 7 },
|
|
// AArch64_EORWrs - 135
|
|
{1476, 628, 4, 4 },
|
|
// AArch64_EORXrs - 136
|
|
{1476, 632, 4, 4 },
|
|
// AArch64_EOR_PPzPP - 137
|
|
{1491, 636, 4, 7 },
|
|
// AArch64_EOR_ZI - 138
|
|
{1514, 643, 3, 6 },
|
|
{1535, 649, 3, 6 },
|
|
{1556, 655, 3, 6 },
|
|
// AArch64_EXTRACT_ZPMXI_H_B - 141
|
|
{1577, 661, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_H_D - 142
|
|
{1610, 666, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_H_H - 143
|
|
{1643, 671, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_H_Q - 144
|
|
{1676, 676, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_H_S - 145
|
|
{1709, 681, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_V_B - 146
|
|
{1742, 686, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_V_D - 147
|
|
{1775, 691, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_V_H - 148
|
|
{1808, 696, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_V_Q - 149
|
|
{1841, 701, 5, 5 },
|
|
// AArch64_EXTRACT_ZPMXI_V_S - 150
|
|
{1874, 706, 5, 5 },
|
|
// AArch64_EXTRWrri - 151
|
|
{1907, 711, 4, 3 },
|
|
// AArch64_EXTRXrri - 152
|
|
{1907, 714, 4, 3 },
|
|
// AArch64_FCPY_ZPmI_D - 153
|
|
{1922, 717, 4, 6 },
|
|
// AArch64_FCPY_ZPmI_H - 154
|
|
{1946, 723, 4, 6 },
|
|
// AArch64_FCPY_ZPmI_S - 155
|
|
{1970, 729, 4, 6 },
|
|
// AArch64_FDUP_ZI_D - 156
|
|
{1994, 735, 2, 4 },
|
|
// AArch64_FDUP_ZI_H - 157
|
|
{2010, 739, 2, 4 },
|
|
// AArch64_FDUP_ZI_S - 158
|
|
{2026, 743, 2, 4 },
|
|
// AArch64_GLD1B_D_IMM_REAL - 159
|
|
{2042, 747, 4, 5 },
|
|
// AArch64_GLD1B_S_IMM_REAL - 160
|
|
{2068, 752, 4, 5 },
|
|
// AArch64_GLD1D_IMM_REAL - 161
|
|
{2094, 757, 4, 5 },
|
|
// AArch64_GLD1H_D_IMM_REAL - 162
|
|
{2120, 762, 4, 5 },
|
|
// AArch64_GLD1H_S_IMM_REAL - 163
|
|
{2146, 767, 4, 5 },
|
|
// AArch64_GLD1SB_D_IMM_REAL - 164
|
|
{2172, 772, 4, 5 },
|
|
// AArch64_GLD1SB_S_IMM_REAL - 165
|
|
{2199, 777, 4, 5 },
|
|
// AArch64_GLD1SH_D_IMM_REAL - 166
|
|
{2226, 782, 4, 5 },
|
|
// AArch64_GLD1SH_S_IMM_REAL - 167
|
|
{2253, 787, 4, 5 },
|
|
// AArch64_GLD1SW_D_IMM_REAL - 168
|
|
{2280, 792, 4, 5 },
|
|
// AArch64_GLD1W_D_IMM_REAL - 169
|
|
{2307, 797, 4, 5 },
|
|
// AArch64_GLD1W_IMM_REAL - 170
|
|
{2333, 802, 4, 5 },
|
|
// AArch64_GLDFF1B_D_IMM_REAL - 171
|
|
{2359, 807, 4, 5 },
|
|
// AArch64_GLDFF1B_S_IMM_REAL - 172
|
|
{2387, 812, 4, 5 },
|
|
// AArch64_GLDFF1D_IMM_REAL - 173
|
|
{2415, 817, 4, 5 },
|
|
// AArch64_GLDFF1H_D_IMM_REAL - 174
|
|
{2443, 822, 4, 5 },
|
|
// AArch64_GLDFF1H_S_IMM_REAL - 175
|
|
{2471, 827, 4, 5 },
|
|
// AArch64_GLDFF1SB_D_IMM_REAL - 176
|
|
{2499, 832, 4, 5 },
|
|
// AArch64_GLDFF1SB_S_IMM_REAL - 177
|
|
{2528, 837, 4, 5 },
|
|
// AArch64_GLDFF1SH_D_IMM_REAL - 178
|
|
{2557, 842, 4, 5 },
|
|
// AArch64_GLDFF1SH_S_IMM_REAL - 179
|
|
{2586, 847, 4, 5 },
|
|
// AArch64_GLDFF1SW_D_IMM_REAL - 180
|
|
{2615, 852, 4, 5 },
|
|
// AArch64_GLDFF1W_D_IMM_REAL - 181
|
|
{2644, 857, 4, 5 },
|
|
// AArch64_GLDFF1W_IMM_REAL - 182
|
|
{2672, 862, 4, 5 },
|
|
// AArch64_HINT - 183
|
|
{2700, 867, 1, 1 },
|
|
{2704, 868, 1, 1 },
|
|
{2710, 869, 1, 1 },
|
|
{2714, 870, 1, 1 },
|
|
{2718, 871, 1, 1 },
|
|
{2722, 872, 1, 1 },
|
|
{2727, 873, 1, 1 },
|
|
{2731, 874, 1, 2 },
|
|
{2735, 876, 1, 1 },
|
|
{2740, 877, 1, 2 },
|
|
{2744, 879, 1, 2 },
|
|
{2753, 881, 1, 2 },
|
|
// AArch64_INCB_XPiI - 195
|
|
{2762, 883, 4, 7 },
|
|
{2770, 890, 4, 7 },
|
|
// AArch64_INCD_XPiI - 197
|
|
{2784, 897, 4, 7 },
|
|
{2792, 904, 4, 7 },
|
|
// AArch64_INCD_ZPiI - 199
|
|
{2806, 911, 4, 7 },
|
|
{2816, 918, 4, 7 },
|
|
// AArch64_INCH_XPiI - 201
|
|
{2832, 925, 4, 7 },
|
|
{2840, 932, 4, 7 },
|
|
// AArch64_INCH_ZPiI - 203
|
|
{2854, 939, 4, 7 },
|
|
{2864, 946, 4, 7 },
|
|
// AArch64_INCW_XPiI - 205
|
|
{2880, 953, 4, 7 },
|
|
{2888, 960, 4, 7 },
|
|
// AArch64_INCW_ZPiI - 207
|
|
{2902, 967, 4, 7 },
|
|
{2912, 974, 4, 7 },
|
|
// AArch64_INSERT_MXIPZ_H_B - 209
|
|
{2928, 981, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_H_D - 210
|
|
{2961, 987, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_H_H - 211
|
|
{2994, 993, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_H_Q - 212
|
|
{3027, 999, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_H_S - 213
|
|
{3060, 1005, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_V_B - 214
|
|
{3093, 1011, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_V_D - 215
|
|
{3126, 1017, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_V_H - 216
|
|
{3159, 1023, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_V_Q - 217
|
|
{3192, 1029, 5, 6 },
|
|
// AArch64_INSERT_MXIPZ_V_S - 218
|
|
{3225, 1035, 5, 6 },
|
|
// AArch64_INSvi16gpr - 219
|
|
{3258, 1041, 4, 5 },
|
|
// AArch64_INSvi16lane - 220
|
|
{3277, 1046, 5, 5 },
|
|
// AArch64_INSvi32gpr - 221
|
|
{3304, 1051, 4, 5 },
|
|
// AArch64_INSvi32lane - 222
|
|
{3323, 1056, 5, 5 },
|
|
// AArch64_INSvi64gpr - 223
|
|
{3350, 1061, 4, 5 },
|
|
// AArch64_INSvi64lane - 224
|
|
{3369, 1066, 5, 5 },
|
|
// AArch64_INSvi8gpr - 225
|
|
{3396, 1071, 4, 5 },
|
|
// AArch64_INSvi8lane - 226
|
|
{3415, 1076, 5, 5 },
|
|
// AArch64_IRG - 227
|
|
{3442, 1081, 3, 4 },
|
|
// AArch64_ISB - 228
|
|
{3453, 1085, 1, 1 },
|
|
// AArch64_LD1B_D_IMM_REAL - 229
|
|
{3457, 1086, 4, 7 },
|
|
// AArch64_LD1B_H_IMM_REAL - 230
|
|
{3481, 1093, 4, 7 },
|
|
// AArch64_LD1B_IMM_REAL - 231
|
|
{3505, 1100, 4, 7 },
|
|
// AArch64_LD1B_S_IMM_REAL - 232
|
|
{3529, 1107, 4, 7 },
|
|
// AArch64_LD1D_IMM_REAL - 233
|
|
{3553, 1114, 4, 7 },
|
|
// AArch64_LD1Fourv16b_POST - 234
|
|
{3577, 1121, 4, 5 },
|
|
// AArch64_LD1Fourv1d_POST - 235
|
|
{3597, 1126, 4, 5 },
|
|
// AArch64_LD1Fourv2d_POST - 236
|
|
{3617, 1131, 4, 5 },
|
|
// AArch64_LD1Fourv2s_POST - 237
|
|
{3637, 1136, 4, 5 },
|
|
// AArch64_LD1Fourv4h_POST - 238
|
|
{3657, 1141, 4, 5 },
|
|
// AArch64_LD1Fourv4s_POST - 239
|
|
{3677, 1146, 4, 5 },
|
|
// AArch64_LD1Fourv8b_POST - 240
|
|
{3697, 1151, 4, 5 },
|
|
// AArch64_LD1Fourv8h_POST - 241
|
|
{3717, 1156, 4, 5 },
|
|
// AArch64_LD1H_D_IMM_REAL - 242
|
|
{3737, 1161, 4, 7 },
|
|
// AArch64_LD1H_IMM_REAL - 243
|
|
{3761, 1168, 4, 7 },
|
|
// AArch64_LD1H_S_IMM_REAL - 244
|
|
{3785, 1175, 4, 7 },
|
|
// AArch64_LD1Onev16b_POST - 245
|
|
{3809, 1182, 4, 5 },
|
|
// AArch64_LD1Onev1d_POST - 246
|
|
{3829, 1187, 4, 5 },
|
|
// AArch64_LD1Onev2d_POST - 247
|
|
{3848, 1192, 4, 5 },
|
|
// AArch64_LD1Onev2s_POST - 248
|
|
{3868, 1197, 4, 5 },
|
|
// AArch64_LD1Onev4h_POST - 249
|
|
{3887, 1202, 4, 5 },
|
|
// AArch64_LD1Onev4s_POST - 250
|
|
{3906, 1207, 4, 5 },
|
|
// AArch64_LD1Onev8b_POST - 251
|
|
{3926, 1212, 4, 5 },
|
|
// AArch64_LD1Onev8h_POST - 252
|
|
{3945, 1217, 4, 5 },
|
|
// AArch64_LD1RB_D_IMM - 253
|
|
{3965, 1222, 4, 7 },
|
|
// AArch64_LD1RB_H_IMM - 254
|
|
{3990, 1229, 4, 7 },
|
|
// AArch64_LD1RB_IMM - 255
|
|
{4015, 1236, 4, 7 },
|
|
// AArch64_LD1RB_S_IMM - 256
|
|
{4040, 1243, 4, 7 },
|
|
// AArch64_LD1RD_IMM - 257
|
|
{4065, 1250, 4, 7 },
|
|
// AArch64_LD1RH_D_IMM - 258
|
|
{4090, 1257, 4, 7 },
|
|
// AArch64_LD1RH_IMM - 259
|
|
{4115, 1264, 4, 7 },
|
|
// AArch64_LD1RH_S_IMM - 260
|
|
{4140, 1271, 4, 7 },
|
|
// AArch64_LD1RO_B_IMM - 261
|
|
{4165, 1278, 4, 6 },
|
|
// AArch64_LD1RO_D_IMM - 262
|
|
{4191, 1284, 4, 6 },
|
|
// AArch64_LD1RO_H_IMM - 263
|
|
{4217, 1290, 4, 6 },
|
|
// AArch64_LD1RO_W_IMM - 264
|
|
{4243, 1296, 4, 6 },
|
|
// AArch64_LD1RQ_B_IMM - 265
|
|
{4269, 1302, 4, 7 },
|
|
// AArch64_LD1RQ_D_IMM - 266
|
|
{4295, 1309, 4, 7 },
|
|
// AArch64_LD1RQ_H_IMM - 267
|
|
{4321, 1316, 4, 7 },
|
|
// AArch64_LD1RQ_W_IMM - 268
|
|
{4347, 1323, 4, 7 },
|
|
// AArch64_LD1RSB_D_IMM - 269
|
|
{4373, 1330, 4, 7 },
|
|
// AArch64_LD1RSB_H_IMM - 270
|
|
{4399, 1337, 4, 7 },
|
|
// AArch64_LD1RSB_S_IMM - 271
|
|
{4425, 1344, 4, 7 },
|
|
// AArch64_LD1RSH_D_IMM - 272
|
|
{4451, 1351, 4, 7 },
|
|
// AArch64_LD1RSH_S_IMM - 273
|
|
{4477, 1358, 4, 7 },
|
|
// AArch64_LD1RSW_IMM - 274
|
|
{4503, 1365, 4, 7 },
|
|
// AArch64_LD1RW_D_IMM - 275
|
|
{4529, 1372, 4, 7 },
|
|
// AArch64_LD1RW_IMM - 276
|
|
{4554, 1379, 4, 7 },
|
|
// AArch64_LD1Rv16b_POST - 277
|
|
{4579, 1386, 4, 5 },
|
|
// AArch64_LD1Rv1d_POST - 278
|
|
{4599, 1391, 4, 5 },
|
|
// AArch64_LD1Rv2d_POST - 279
|
|
{4619, 1396, 4, 5 },
|
|
// AArch64_LD1Rv2s_POST - 280
|
|
{4639, 1401, 4, 5 },
|
|
// AArch64_LD1Rv4h_POST - 281
|
|
{4659, 1406, 4, 5 },
|
|
// AArch64_LD1Rv4s_POST - 282
|
|
{4679, 1411, 4, 5 },
|
|
// AArch64_LD1Rv8b_POST - 283
|
|
{4699, 1416, 4, 5 },
|
|
// AArch64_LD1Rv8h_POST - 284
|
|
{4719, 1421, 4, 5 },
|
|
// AArch64_LD1SB_D_IMM_REAL - 285
|
|
{4739, 1426, 4, 7 },
|
|
// AArch64_LD1SB_H_IMM_REAL - 286
|
|
{4764, 1433, 4, 7 },
|
|
// AArch64_LD1SB_S_IMM_REAL - 287
|
|
{4789, 1440, 4, 7 },
|
|
// AArch64_LD1SH_D_IMM_REAL - 288
|
|
{4814, 1447, 4, 7 },
|
|
// AArch64_LD1SH_S_IMM_REAL - 289
|
|
{4839, 1454, 4, 7 },
|
|
// AArch64_LD1SW_D_IMM_REAL - 290
|
|
{4864, 1461, 4, 7 },
|
|
// AArch64_LD1Threev16b_POST - 291
|
|
{4889, 1468, 4, 5 },
|
|
// AArch64_LD1Threev1d_POST - 292
|
|
{4909, 1473, 4, 5 },
|
|
// AArch64_LD1Threev2d_POST - 293
|
|
{4929, 1478, 4, 5 },
|
|
// AArch64_LD1Threev2s_POST - 294
|
|
{4949, 1483, 4, 5 },
|
|
// AArch64_LD1Threev4h_POST - 295
|
|
{4969, 1488, 4, 5 },
|
|
// AArch64_LD1Threev4s_POST - 296
|
|
{4989, 1493, 4, 5 },
|
|
// AArch64_LD1Threev8b_POST - 297
|
|
{5009, 1498, 4, 5 },
|
|
// AArch64_LD1Threev8h_POST - 298
|
|
{5029, 1503, 4, 5 },
|
|
// AArch64_LD1Twov16b_POST - 299
|
|
{5049, 1508, 4, 5 },
|
|
// AArch64_LD1Twov1d_POST - 300
|
|
{5069, 1513, 4, 5 },
|
|
// AArch64_LD1Twov2d_POST - 301
|
|
{5089, 1518, 4, 5 },
|
|
// AArch64_LD1Twov2s_POST - 302
|
|
{5109, 1523, 4, 5 },
|
|
// AArch64_LD1Twov4h_POST - 303
|
|
{5129, 1528, 4, 5 },
|
|
// AArch64_LD1Twov4s_POST - 304
|
|
{5149, 1533, 4, 5 },
|
|
// AArch64_LD1Twov8b_POST - 305
|
|
{5169, 1538, 4, 5 },
|
|
// AArch64_LD1Twov8h_POST - 306
|
|
{5189, 1543, 4, 5 },
|
|
// AArch64_LD1W_D_IMM_REAL - 307
|
|
{5209, 1548, 4, 7 },
|
|
// AArch64_LD1W_IMM_REAL - 308
|
|
{5233, 1555, 4, 7 },
|
|
// AArch64_LD1_MXIPXX_H_B - 309
|
|
{5257, 1562, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_H_D - 310
|
|
{5293, 1569, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_H_H - 311
|
|
{5329, 1576, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_H_Q - 312
|
|
{5365, 1583, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_H_S - 313
|
|
{5401, 1590, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_V_B - 314
|
|
{5437, 1597, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_V_D - 315
|
|
{5473, 1604, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_V_H - 316
|
|
{5509, 1611, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_V_Q - 317
|
|
{5545, 1618, 6, 7 },
|
|
// AArch64_LD1_MXIPXX_V_S - 318
|
|
{5581, 1625, 6, 7 },
|
|
// AArch64_LD1i16_POST - 319
|
|
{5617, 1632, 6, 7 },
|
|
// AArch64_LD1i32_POST - 320
|
|
{5640, 1639, 6, 7 },
|
|
// AArch64_LD1i64_POST - 321
|
|
{5663, 1646, 6, 7 },
|
|
// AArch64_LD1i8_POST - 322
|
|
{5686, 1653, 6, 7 },
|
|
// AArch64_LD2B_IMM - 323
|
|
{5709, 1660, 4, 7 },
|
|
// AArch64_LD2D_IMM - 324
|
|
{5733, 1667, 4, 7 },
|
|
// AArch64_LD2H_IMM - 325
|
|
{5757, 1674, 4, 7 },
|
|
// AArch64_LD2Rv16b_POST - 326
|
|
{5781, 1681, 4, 5 },
|
|
// AArch64_LD2Rv1d_POST - 327
|
|
{5801, 1686, 4, 5 },
|
|
// AArch64_LD2Rv2d_POST - 328
|
|
{5822, 1691, 4, 5 },
|
|
// AArch64_LD2Rv2s_POST - 329
|
|
{5843, 1696, 4, 5 },
|
|
// AArch64_LD2Rv4h_POST - 330
|
|
{5863, 1701, 4, 5 },
|
|
// AArch64_LD2Rv4s_POST - 331
|
|
{5883, 1706, 4, 5 },
|
|
// AArch64_LD2Rv8b_POST - 332
|
|
{5903, 1711, 4, 5 },
|
|
// AArch64_LD2Rv8h_POST - 333
|
|
{5923, 1716, 4, 5 },
|
|
// AArch64_LD2Twov16b_POST - 334
|
|
{5943, 1721, 4, 5 },
|
|
// AArch64_LD2Twov2d_POST - 335
|
|
{5963, 1726, 4, 5 },
|
|
// AArch64_LD2Twov2s_POST - 336
|
|
{5983, 1731, 4, 5 },
|
|
// AArch64_LD2Twov4h_POST - 337
|
|
{6003, 1736, 4, 5 },
|
|
// AArch64_LD2Twov4s_POST - 338
|
|
{6023, 1741, 4, 5 },
|
|
// AArch64_LD2Twov8b_POST - 339
|
|
{6043, 1746, 4, 5 },
|
|
// AArch64_LD2Twov8h_POST - 340
|
|
{6063, 1751, 4, 5 },
|
|
// AArch64_LD2W_IMM - 341
|
|
{6083, 1756, 4, 7 },
|
|
// AArch64_LD2i16_POST - 342
|
|
{6107, 1763, 6, 7 },
|
|
// AArch64_LD2i32_POST - 343
|
|
{6130, 1770, 6, 7 },
|
|
// AArch64_LD2i64_POST - 344
|
|
{6153, 1777, 6, 7 },
|
|
// AArch64_LD2i8_POST - 345
|
|
{6177, 1784, 6, 7 },
|
|
// AArch64_LD3B_IMM - 346
|
|
{6200, 1791, 4, 7 },
|
|
// AArch64_LD3D_IMM - 347
|
|
{6224, 1798, 4, 7 },
|
|
// AArch64_LD3H_IMM - 348
|
|
{6248, 1805, 4, 7 },
|
|
// AArch64_LD3Rv16b_POST - 349
|
|
{6272, 1812, 4, 5 },
|
|
// AArch64_LD3Rv1d_POST - 350
|
|
{6292, 1817, 4, 5 },
|
|
// AArch64_LD3Rv2d_POST - 351
|
|
{6313, 1822, 4, 5 },
|
|
// AArch64_LD3Rv2s_POST - 352
|
|
{6334, 1827, 4, 5 },
|
|
// AArch64_LD3Rv4h_POST - 353
|
|
{6355, 1832, 4, 5 },
|
|
// AArch64_LD3Rv4s_POST - 354
|
|
{6375, 1837, 4, 5 },
|
|
// AArch64_LD3Rv8b_POST - 355
|
|
{6396, 1842, 4, 5 },
|
|
// AArch64_LD3Rv8h_POST - 356
|
|
{6416, 1847, 4, 5 },
|
|
// AArch64_LD3Threev16b_POST - 357
|
|
{6436, 1852, 4, 5 },
|
|
// AArch64_LD3Threev2d_POST - 358
|
|
{6456, 1857, 4, 5 },
|
|
// AArch64_LD3Threev2s_POST - 359
|
|
{6476, 1862, 4, 5 },
|
|
// AArch64_LD3Threev4h_POST - 360
|
|
{6496, 1867, 4, 5 },
|
|
// AArch64_LD3Threev4s_POST - 361
|
|
{6516, 1872, 4, 5 },
|
|
// AArch64_LD3Threev8b_POST - 362
|
|
{6536, 1877, 4, 5 },
|
|
// AArch64_LD3Threev8h_POST - 363
|
|
{6556, 1882, 4, 5 },
|
|
// AArch64_LD3W_IMM - 364
|
|
{6576, 1887, 4, 7 },
|
|
// AArch64_LD3i16_POST - 365
|
|
{6600, 1894, 6, 7 },
|
|
// AArch64_LD3i32_POST - 366
|
|
{6623, 1901, 6, 7 },
|
|
// AArch64_LD3i64_POST - 367
|
|
{6647, 1908, 6, 7 },
|
|
// AArch64_LD3i8_POST - 368
|
|
{6671, 1915, 6, 7 },
|
|
// AArch64_LD4B_IMM - 369
|
|
{6694, 1922, 4, 7 },
|
|
// AArch64_LD4D_IMM - 370
|
|
{6718, 1929, 4, 7 },
|
|
// AArch64_LD4Fourv16b_POST - 371
|
|
{6742, 1936, 4, 5 },
|
|
// AArch64_LD4Fourv2d_POST - 372
|
|
{6762, 1941, 4, 5 },
|
|
// AArch64_LD4Fourv2s_POST - 373
|
|
{6782, 1946, 4, 5 },
|
|
// AArch64_LD4Fourv4h_POST - 374
|
|
{6802, 1951, 4, 5 },
|
|
// AArch64_LD4Fourv4s_POST - 375
|
|
{6822, 1956, 4, 5 },
|
|
// AArch64_LD4Fourv8b_POST - 376
|
|
{6842, 1961, 4, 5 },
|
|
// AArch64_LD4Fourv8h_POST - 377
|
|
{6862, 1966, 4, 5 },
|
|
// AArch64_LD4H_IMM - 378
|
|
{6882, 1971, 4, 7 },
|
|
// AArch64_LD4Rv16b_POST - 379
|
|
{6906, 1978, 4, 5 },
|
|
// AArch64_LD4Rv1d_POST - 380
|
|
{6926, 1983, 4, 5 },
|
|
// AArch64_LD4Rv2d_POST - 381
|
|
{6947, 1988, 4, 5 },
|
|
// AArch64_LD4Rv2s_POST - 382
|
|
{6968, 1993, 4, 5 },
|
|
// AArch64_LD4Rv4h_POST - 383
|
|
{6989, 1998, 4, 5 },
|
|
// AArch64_LD4Rv4s_POST - 384
|
|
{7009, 2003, 4, 5 },
|
|
// AArch64_LD4Rv8b_POST - 385
|
|
{7030, 2008, 4, 5 },
|
|
// AArch64_LD4Rv8h_POST - 386
|
|
{7050, 2013, 4, 5 },
|
|
// AArch64_LD4W_IMM - 387
|
|
{7070, 2018, 4, 7 },
|
|
// AArch64_LD4i16_POST - 388
|
|
{7094, 2025, 6, 7 },
|
|
// AArch64_LD4i32_POST - 389
|
|
{7117, 2032, 6, 7 },
|
|
// AArch64_LD4i64_POST - 390
|
|
{7141, 2039, 6, 7 },
|
|
// AArch64_LD4i8_POST - 391
|
|
{7165, 2046, 6, 7 },
|
|
// AArch64_LDADDB - 392
|
|
{7188, 2053, 3, 4 },
|
|
// AArch64_LDADDH - 393
|
|
{7204, 2057, 3, 4 },
|
|
// AArch64_LDADDLB - 394
|
|
{7220, 2061, 3, 4 },
|
|
// AArch64_LDADDLH - 395
|
|
{7237, 2065, 3, 4 },
|
|
// AArch64_LDADDLW - 396
|
|
{7254, 2069, 3, 4 },
|
|
// AArch64_LDADDLX - 397
|
|
{7254, 2073, 3, 4 },
|
|
// AArch64_LDADDW - 398
|
|
{7270, 2077, 3, 4 },
|
|
// AArch64_LDADDX - 399
|
|
{7270, 2081, 3, 4 },
|
|
// AArch64_LDAPURBi - 400
|
|
{7285, 2085, 3, 4 },
|
|
// AArch64_LDAPURHi - 401
|
|
{7302, 2089, 3, 4 },
|
|
// AArch64_LDAPURSBWi - 402
|
|
{7319, 2093, 3, 4 },
|
|
// AArch64_LDAPURSBXi - 403
|
|
{7319, 2097, 3, 4 },
|
|
// AArch64_LDAPURSHWi - 404
|
|
{7337, 2101, 3, 4 },
|
|
// AArch64_LDAPURSHXi - 405
|
|
{7337, 2105, 3, 4 },
|
|
// AArch64_LDAPURSWi - 406
|
|
{7355, 2109, 3, 4 },
|
|
// AArch64_LDAPURXi - 407
|
|
{7373, 2113, 3, 4 },
|
|
// AArch64_LDAPURi - 408
|
|
{7373, 2117, 3, 4 },
|
|
// AArch64_LDCLRB - 409
|
|
{7389, 2121, 3, 4 },
|
|
// AArch64_LDCLRH - 410
|
|
{7405, 2125, 3, 4 },
|
|
// AArch64_LDCLRLB - 411
|
|
{7421, 2129, 3, 4 },
|
|
// AArch64_LDCLRLH - 412
|
|
{7438, 2133, 3, 4 },
|
|
// AArch64_LDCLRLW - 413
|
|
{7455, 2137, 3, 4 },
|
|
// AArch64_LDCLRLX - 414
|
|
{7455, 2141, 3, 4 },
|
|
// AArch64_LDCLRW - 415
|
|
{7471, 2145, 3, 4 },
|
|
// AArch64_LDCLRX - 416
|
|
{7471, 2149, 3, 4 },
|
|
// AArch64_LDEORB - 417
|
|
{7486, 2153, 3, 4 },
|
|
// AArch64_LDEORH - 418
|
|
{7502, 2157, 3, 4 },
|
|
// AArch64_LDEORLB - 419
|
|
{7518, 2161, 3, 4 },
|
|
// AArch64_LDEORLH - 420
|
|
{7535, 2165, 3, 4 },
|
|
// AArch64_LDEORLW - 421
|
|
{7552, 2169, 3, 4 },
|
|
// AArch64_LDEORLX - 422
|
|
{7552, 2173, 3, 4 },
|
|
// AArch64_LDEORW - 423
|
|
{7568, 2177, 3, 4 },
|
|
// AArch64_LDEORX - 424
|
|
{7568, 2181, 3, 4 },
|
|
// AArch64_LDFF1B_D_REAL - 425
|
|
{7583, 2185, 4, 5 },
|
|
// AArch64_LDFF1B_H_REAL - 426
|
|
{7609, 2190, 4, 5 },
|
|
// AArch64_LDFF1B_REAL - 427
|
|
{7635, 2195, 4, 5 },
|
|
// AArch64_LDFF1B_S_REAL - 428
|
|
{7661, 2200, 4, 5 },
|
|
// AArch64_LDFF1D_REAL - 429
|
|
{7687, 2205, 4, 5 },
|
|
// AArch64_LDFF1H_D_REAL - 430
|
|
{7713, 2210, 4, 5 },
|
|
// AArch64_LDFF1H_REAL - 431
|
|
{7739, 2215, 4, 5 },
|
|
// AArch64_LDFF1H_S_REAL - 432
|
|
{7765, 2220, 4, 5 },
|
|
// AArch64_LDFF1SB_D_REAL - 433
|
|
{7791, 2225, 4, 5 },
|
|
// AArch64_LDFF1SB_H_REAL - 434
|
|
{7818, 2230, 4, 5 },
|
|
// AArch64_LDFF1SB_S_REAL - 435
|
|
{7845, 2235, 4, 5 },
|
|
// AArch64_LDFF1SH_D_REAL - 436
|
|
{7872, 2240, 4, 5 },
|
|
// AArch64_LDFF1SH_S_REAL - 437
|
|
{7899, 2245, 4, 5 },
|
|
// AArch64_LDFF1SW_D_REAL - 438
|
|
{7926, 2250, 4, 5 },
|
|
// AArch64_LDFF1W_D_REAL - 439
|
|
{7953, 2255, 4, 5 },
|
|
// AArch64_LDFF1W_REAL - 440
|
|
{7979, 2260, 4, 5 },
|
|
// AArch64_LDG - 441
|
|
{8005, 2265, 4, 5 },
|
|
// AArch64_LDNF1B_D_IMM_REAL - 442
|
|
{8018, 2270, 4, 5 },
|
|
// AArch64_LDNF1B_H_IMM_REAL - 443
|
|
{8044, 2275, 4, 5 },
|
|
// AArch64_LDNF1B_IMM_REAL - 444
|
|
{8070, 2280, 4, 5 },
|
|
// AArch64_LDNF1B_S_IMM_REAL - 445
|
|
{8096, 2285, 4, 5 },
|
|
// AArch64_LDNF1D_IMM_REAL - 446
|
|
{8122, 2290, 4, 5 },
|
|
// AArch64_LDNF1H_D_IMM_REAL - 447
|
|
{8148, 2295, 4, 5 },
|
|
// AArch64_LDNF1H_IMM_REAL - 448
|
|
{8174, 2300, 4, 5 },
|
|
// AArch64_LDNF1H_S_IMM_REAL - 449
|
|
{8200, 2305, 4, 5 },
|
|
// AArch64_LDNF1SB_D_IMM_REAL - 450
|
|
{8226, 2310, 4, 5 },
|
|
// AArch64_LDNF1SB_H_IMM_REAL - 451
|
|
{8253, 2315, 4, 5 },
|
|
// AArch64_LDNF1SB_S_IMM_REAL - 452
|
|
{8280, 2320, 4, 5 },
|
|
// AArch64_LDNF1SH_D_IMM_REAL - 453
|
|
{8307, 2325, 4, 5 },
|
|
// AArch64_LDNF1SH_S_IMM_REAL - 454
|
|
{8334, 2330, 4, 5 },
|
|
// AArch64_LDNF1SW_D_IMM_REAL - 455
|
|
{8361, 2335, 4, 5 },
|
|
// AArch64_LDNF1W_D_IMM_REAL - 456
|
|
{8388, 2340, 4, 5 },
|
|
// AArch64_LDNF1W_IMM_REAL - 457
|
|
{8414, 2345, 4, 5 },
|
|
// AArch64_LDNPDi - 458
|
|
{8440, 2350, 4, 4 },
|
|
// AArch64_LDNPQi - 459
|
|
{8440, 2354, 4, 4 },
|
|
// AArch64_LDNPSi - 460
|
|
{8440, 2358, 4, 4 },
|
|
// AArch64_LDNPWi - 461
|
|
{8440, 2362, 4, 4 },
|
|
// AArch64_LDNPXi - 462
|
|
{8440, 2366, 4, 4 },
|
|
// AArch64_LDNT1B_ZRI - 463
|
|
{8458, 2370, 4, 7 },
|
|
// AArch64_LDNT1B_ZZR_D_REAL - 464
|
|
{8484, 2377, 4, 5 },
|
|
// AArch64_LDNT1B_ZZR_S_REAL - 465
|
|
{8512, 2382, 4, 5 },
|
|
// AArch64_LDNT1D_ZRI - 466
|
|
{8540, 2387, 4, 7 },
|
|
// AArch64_LDNT1D_ZZR_D_REAL - 467
|
|
{8566, 2394, 4, 5 },
|
|
// AArch64_LDNT1H_ZRI - 468
|
|
{8594, 2399, 4, 7 },
|
|
// AArch64_LDNT1H_ZZR_D_REAL - 469
|
|
{8620, 2406, 4, 5 },
|
|
// AArch64_LDNT1H_ZZR_S_REAL - 470
|
|
{8648, 2411, 4, 5 },
|
|
// AArch64_LDNT1SB_ZZR_D_REAL - 471
|
|
{8676, 2416, 4, 5 },
|
|
// AArch64_LDNT1SB_ZZR_S_REAL - 472
|
|
{8705, 2421, 4, 5 },
|
|
// AArch64_LDNT1SH_ZZR_D_REAL - 473
|
|
{8734, 2426, 4, 5 },
|
|
// AArch64_LDNT1SH_ZZR_S_REAL - 474
|
|
{8763, 2431, 4, 5 },
|
|
// AArch64_LDNT1SW_ZZR_D_REAL - 475
|
|
{8792, 2436, 4, 5 },
|
|
// AArch64_LDNT1W_ZRI - 476
|
|
{8821, 2441, 4, 7 },
|
|
// AArch64_LDNT1W_ZZR_D_REAL - 477
|
|
{8847, 2448, 4, 5 },
|
|
// AArch64_LDNT1W_ZZR_S_REAL - 478
|
|
{8875, 2453, 4, 5 },
|
|
// AArch64_LDPDi - 479
|
|
{8903, 2458, 4, 4 },
|
|
// AArch64_LDPQi - 480
|
|
{8903, 2462, 4, 4 },
|
|
// AArch64_LDPSWi - 481
|
|
{8920, 2466, 4, 4 },
|
|
// AArch64_LDPSi - 482
|
|
{8903, 2470, 4, 4 },
|
|
// AArch64_LDPWi - 483
|
|
{8903, 2474, 4, 4 },
|
|
// AArch64_LDPXi - 484
|
|
{8903, 2478, 4, 4 },
|
|
// AArch64_LDRAAindexed - 485
|
|
{8939, 2482, 3, 4 },
|
|
// AArch64_LDRABindexed - 486
|
|
{8954, 2486, 3, 4 },
|
|
// AArch64_LDRBBroX - 487
|
|
{8969, 2490, 5, 5 },
|
|
// AArch64_LDRBBui - 488
|
|
{8987, 2495, 3, 3 },
|
|
// AArch64_LDRBroX - 489
|
|
{9001, 2498, 5, 5 },
|
|
// AArch64_LDRBui - 490
|
|
{9018, 2503, 3, 3 },
|
|
// AArch64_LDRDroX - 491
|
|
{9001, 2506, 5, 5 },
|
|
// AArch64_LDRDui - 492
|
|
{9018, 2511, 3, 3 },
|
|
// AArch64_LDRHHroX - 493
|
|
{9031, 2514, 5, 5 },
|
|
// AArch64_LDRHHui - 494
|
|
{9049, 2519, 3, 3 },
|
|
// AArch64_LDRHroX - 495
|
|
{9001, 2522, 5, 5 },
|
|
// AArch64_LDRHui - 496
|
|
{9018, 2527, 3, 3 },
|
|
// AArch64_LDRQroX - 497
|
|
{9001, 2530, 5, 5 },
|
|
// AArch64_LDRQui - 498
|
|
{9018, 2535, 3, 3 },
|
|
// AArch64_LDRSBWroX - 499
|
|
{9063, 2538, 5, 5 },
|
|
// AArch64_LDRSBWui - 500
|
|
{9082, 2543, 3, 3 },
|
|
// AArch64_LDRSBXroX - 501
|
|
{9063, 2546, 5, 5 },
|
|
// AArch64_LDRSBXui - 502
|
|
{9082, 2551, 3, 3 },
|
|
// AArch64_LDRSHWroX - 503
|
|
{9097, 2554, 5, 5 },
|
|
// AArch64_LDRSHWui - 504
|
|
{9116, 2559, 3, 3 },
|
|
// AArch64_LDRSHXroX - 505
|
|
{9097, 2562, 5, 5 },
|
|
// AArch64_LDRSHXui - 506
|
|
{9116, 2567, 3, 3 },
|
|
// AArch64_LDRSWroX - 507
|
|
{9131, 2570, 5, 5 },
|
|
// AArch64_LDRSWui - 508
|
|
{9150, 2575, 3, 3 },
|
|
// AArch64_LDRSroX - 509
|
|
{9001, 2578, 5, 5 },
|
|
// AArch64_LDRSui - 510
|
|
{9018, 2583, 3, 3 },
|
|
// AArch64_LDRWroX - 511
|
|
{9001, 2586, 5, 5 },
|
|
// AArch64_LDRWui - 512
|
|
{9018, 2591, 3, 3 },
|
|
// AArch64_LDRXroX - 513
|
|
{9001, 2594, 5, 5 },
|
|
// AArch64_LDRXui - 514
|
|
{9018, 2599, 3, 3 },
|
|
// AArch64_LDR_PXI - 515
|
|
{9165, 2602, 3, 6 },
|
|
// AArch64_LDR_ZA - 516
|
|
{9180, 2608, 5, 6 },
|
|
// AArch64_LDR_ZXI - 517
|
|
{9165, 2614, 3, 6 },
|
|
// AArch64_LDSETB - 518
|
|
{9205, 2620, 3, 4 },
|
|
// AArch64_LDSETH - 519
|
|
{9221, 2624, 3, 4 },
|
|
// AArch64_LDSETLB - 520
|
|
{9237, 2628, 3, 4 },
|
|
// AArch64_LDSETLH - 521
|
|
{9254, 2632, 3, 4 },
|
|
// AArch64_LDSETLW - 522
|
|
{9271, 2636, 3, 4 },
|
|
// AArch64_LDSETLX - 523
|
|
{9271, 2640, 3, 4 },
|
|
// AArch64_LDSETW - 524
|
|
{9287, 2644, 3, 4 },
|
|
// AArch64_LDSETX - 525
|
|
{9287, 2648, 3, 4 },
|
|
// AArch64_LDSMAXB - 526
|
|
{9302, 2652, 3, 4 },
|
|
// AArch64_LDSMAXH - 527
|
|
{9319, 2656, 3, 4 },
|
|
// AArch64_LDSMAXLB - 528
|
|
{9336, 2660, 3, 4 },
|
|
// AArch64_LDSMAXLH - 529
|
|
{9354, 2664, 3, 4 },
|
|
// AArch64_LDSMAXLW - 530
|
|
{9372, 2668, 3, 4 },
|
|
// AArch64_LDSMAXLX - 531
|
|
{9372, 2672, 3, 4 },
|
|
// AArch64_LDSMAXW - 532
|
|
{9389, 2676, 3, 4 },
|
|
// AArch64_LDSMAXX - 533
|
|
{9389, 2680, 3, 4 },
|
|
// AArch64_LDSMINB - 534
|
|
{9405, 2684, 3, 4 },
|
|
// AArch64_LDSMINH - 535
|
|
{9422, 2688, 3, 4 },
|
|
// AArch64_LDSMINLB - 536
|
|
{9439, 2692, 3, 4 },
|
|
// AArch64_LDSMINLH - 537
|
|
{9457, 2696, 3, 4 },
|
|
// AArch64_LDSMINLW - 538
|
|
{9475, 2700, 3, 4 },
|
|
// AArch64_LDSMINLX - 539
|
|
{9475, 2704, 3, 4 },
|
|
// AArch64_LDSMINW - 540
|
|
{9492, 2708, 3, 4 },
|
|
// AArch64_LDSMINX - 541
|
|
{9492, 2712, 3, 4 },
|
|
// AArch64_LDTRBi - 542
|
|
{9508, 2716, 3, 3 },
|
|
// AArch64_LDTRHi - 543
|
|
{9523, 2719, 3, 3 },
|
|
// AArch64_LDTRSBWi - 544
|
|
{9538, 2722, 3, 3 },
|
|
// AArch64_LDTRSBXi - 545
|
|
{9538, 2725, 3, 3 },
|
|
// AArch64_LDTRSHWi - 546
|
|
{9554, 2728, 3, 3 },
|
|
// AArch64_LDTRSHXi - 547
|
|
{9554, 2731, 3, 3 },
|
|
// AArch64_LDTRSWi - 548
|
|
{9570, 2734, 3, 3 },
|
|
// AArch64_LDTRWi - 549
|
|
{9586, 2737, 3, 3 },
|
|
// AArch64_LDTRXi - 550
|
|
{9586, 2740, 3, 3 },
|
|
// AArch64_LDUMAXB - 551
|
|
{9600, 2743, 3, 4 },
|
|
// AArch64_LDUMAXH - 552
|
|
{9617, 2747, 3, 4 },
|
|
// AArch64_LDUMAXLB - 553
|
|
{9634, 2751, 3, 4 },
|
|
// AArch64_LDUMAXLH - 554
|
|
{9652, 2755, 3, 4 },
|
|
// AArch64_LDUMAXLW - 555
|
|
{9670, 2759, 3, 4 },
|
|
// AArch64_LDUMAXLX - 556
|
|
{9670, 2763, 3, 4 },
|
|
// AArch64_LDUMAXW - 557
|
|
{9687, 2767, 3, 4 },
|
|
// AArch64_LDUMAXX - 558
|
|
{9687, 2771, 3, 4 },
|
|
// AArch64_LDUMINB - 559
|
|
{9703, 2775, 3, 4 },
|
|
// AArch64_LDUMINH - 560
|
|
{9720, 2779, 3, 4 },
|
|
// AArch64_LDUMINLB - 561
|
|
{9737, 2783, 3, 4 },
|
|
// AArch64_LDUMINLH - 562
|
|
{9755, 2787, 3, 4 },
|
|
// AArch64_LDUMINLW - 563
|
|
{9773, 2791, 3, 4 },
|
|
// AArch64_LDUMINLX - 564
|
|
{9773, 2795, 3, 4 },
|
|
// AArch64_LDUMINW - 565
|
|
{9790, 2799, 3, 4 },
|
|
// AArch64_LDUMINX - 566
|
|
{9790, 2803, 3, 4 },
|
|
// AArch64_LDURBBi - 567
|
|
{9806, 2807, 3, 3 },
|
|
// AArch64_LDURBi - 568
|
|
{9821, 2810, 3, 3 },
|
|
// AArch64_LDURDi - 569
|
|
{9821, 2813, 3, 3 },
|
|
// AArch64_LDURHHi - 570
|
|
{9835, 2816, 3, 3 },
|
|
// AArch64_LDURHi - 571
|
|
{9821, 2819, 3, 3 },
|
|
// AArch64_LDURQi - 572
|
|
{9821, 2822, 3, 3 },
|
|
// AArch64_LDURSBWi - 573
|
|
{9850, 2825, 3, 3 },
|
|
// AArch64_LDURSBXi - 574
|
|
{9850, 2828, 3, 3 },
|
|
// AArch64_LDURSHWi - 575
|
|
{9866, 2831, 3, 3 },
|
|
// AArch64_LDURSHXi - 576
|
|
{9866, 2834, 3, 3 },
|
|
// AArch64_LDURSWi - 577
|
|
{9882, 2837, 3, 3 },
|
|
// AArch64_LDURSi - 578
|
|
{9821, 2840, 3, 3 },
|
|
// AArch64_LDURWi - 579
|
|
{9821, 2843, 3, 3 },
|
|
// AArch64_LDURXi - 580
|
|
{9821, 2846, 3, 3 },
|
|
// AArch64_MADDWrrr - 581
|
|
{9898, 2849, 4, 4 },
|
|
// AArch64_MADDXrrr - 582
|
|
{9898, 2853, 4, 4 },
|
|
// AArch64_MSRpstatesvcrImm1 - 583
|
|
{9913, 2857, 2, 3 },
|
|
{9921, 2860, 2, 3 },
|
|
{9932, 2863, 2, 3 },
|
|
{9943, 2866, 2, 3 },
|
|
{9950, 2869, 2, 3 },
|
|
{9960, 2872, 2, 3 },
|
|
// AArch64_MSUBWrrr - 589
|
|
{9970, 2875, 4, 4 },
|
|
// AArch64_MSUBXrrr - 590
|
|
{9970, 2879, 4, 4 },
|
|
// AArch64_NOTv16i8 - 591
|
|
{9986, 2883, 2, 2 },
|
|
// AArch64_NOTv8i8 - 592
|
|
{10009, 2885, 2, 2 },
|
|
// AArch64_ORNWrs - 593
|
|
{10030, 2887, 4, 4 },
|
|
{10041, 2891, 4, 3 },
|
|
{10056, 2894, 4, 4 },
|
|
// AArch64_ORNXrs - 596
|
|
{10030, 2898, 4, 4 },
|
|
{10041, 2902, 4, 3 },
|
|
{10056, 2905, 4, 4 },
|
|
// AArch64_ORRS_PPzPP - 599
|
|
{10071, 2909, 4, 7 },
|
|
// AArch64_ORRWrs - 600
|
|
{10087, 2916, 4, 4 },
|
|
{10098, 2920, 4, 4 },
|
|
// AArch64_ORRXrs - 602
|
|
{10087, 2924, 4, 4 },
|
|
{10098, 2928, 4, 4 },
|
|
// AArch64_ORR_PPzPP - 604
|
|
{10113, 2932, 4, 7 },
|
|
// AArch64_ORR_ZI - 605
|
|
{10128, 2939, 3, 6 },
|
|
{10149, 2945, 3, 6 },
|
|
{10170, 2951, 3, 6 },
|
|
// AArch64_ORR_ZZZ - 608
|
|
{10191, 2957, 3, 6 },
|
|
// AArch64_ORRv16i8 - 609
|
|
{10206, 2963, 3, 3 },
|
|
// AArch64_ORRv8i8 - 610
|
|
{10229, 2966, 3, 3 },
|
|
// AArch64_PACIA1716 - 611
|
|
{10250, 2969, 0, 1 },
|
|
// AArch64_PACIASP - 612
|
|
{10260, 2970, 0, 1 },
|
|
// AArch64_PACIAZ - 613
|
|
{10268, 2971, 0, 1 },
|
|
// AArch64_PACIB1716 - 614
|
|
{10275, 2972, 0, 1 },
|
|
// AArch64_PACIBSP - 615
|
|
{10285, 2973, 0, 1 },
|
|
// AArch64_PACIBZ - 616
|
|
{10293, 2974, 0, 1 },
|
|
// AArch64_PRFB_D_PZI - 617
|
|
{10300, 2975, 4, 5 },
|
|
// AArch64_PRFB_PRI - 618
|
|
{10324, 2980, 4, 7 },
|
|
// AArch64_PRFB_S_PZI - 619
|
|
{10346, 2987, 4, 5 },
|
|
// AArch64_PRFD_D_PZI - 620
|
|
{10370, 2992, 4, 5 },
|
|
// AArch64_PRFD_PRI - 621
|
|
{10394, 2997, 4, 7 },
|
|
// AArch64_PRFD_S_PZI - 622
|
|
{10416, 3004, 4, 5 },
|
|
// AArch64_PRFH_D_PZI - 623
|
|
{10440, 3009, 4, 5 },
|
|
// AArch64_PRFH_PRI - 624
|
|
{10464, 3014, 4, 7 },
|
|
// AArch64_PRFH_S_PZI - 625
|
|
{10486, 3021, 4, 5 },
|
|
// AArch64_PRFMroX - 626
|
|
{10510, 3026, 5, 5 },
|
|
// AArch64_PRFMui - 627
|
|
{10530, 3031, 3, 3 },
|
|
// AArch64_PRFUMi - 628
|
|
{10546, 3034, 3, 3 },
|
|
// AArch64_PRFW_D_PZI - 629
|
|
{10563, 3037, 4, 5 },
|
|
// AArch64_PRFW_PRI - 630
|
|
{10587, 3042, 4, 7 },
|
|
// AArch64_PRFW_S_PZI - 631
|
|
{10609, 3049, 4, 5 },
|
|
// AArch64_PTRUES_B - 632
|
|
{10633, 3054, 2, 5 },
|
|
// AArch64_PTRUES_D - 633
|
|
{10645, 3059, 2, 5 },
|
|
// AArch64_PTRUES_H - 634
|
|
{10657, 3064, 2, 5 },
|
|
// AArch64_PTRUES_S - 635
|
|
{10669, 3069, 2, 5 },
|
|
// AArch64_PTRUE_B - 636
|
|
{10681, 3074, 2, 5 },
|
|
// AArch64_PTRUE_D - 637
|
|
{10692, 3079, 2, 5 },
|
|
// AArch64_PTRUE_H - 638
|
|
{10703, 3084, 2, 5 },
|
|
// AArch64_PTRUE_S - 639
|
|
{10714, 3089, 2, 5 },
|
|
// AArch64_RET - 640
|
|
{10725, 3094, 1, 1 },
|
|
// AArch64_SBCSWr - 641
|
|
{10729, 3095, 3, 3 },
|
|
// AArch64_SBCSXr - 642
|
|
{10729, 3098, 3, 3 },
|
|
// AArch64_SBCWr - 643
|
|
{10741, 3101, 3, 3 },
|
|
// AArch64_SBCXr - 644
|
|
{10741, 3104, 3, 3 },
|
|
// AArch64_SBFMWri - 645
|
|
{10752, 3107, 4, 4 },
|
|
{10767, 3111, 4, 4 },
|
|
{10779, 3115, 4, 4 },
|
|
// AArch64_SBFMXri - 648
|
|
{10752, 3119, 4, 4 },
|
|
{10767, 3123, 4, 4 },
|
|
{10779, 3127, 4, 4 },
|
|
{10791, 3131, 4, 4 },
|
|
// AArch64_SEL_PPPP - 652
|
|
{10803, 3135, 4, 7 },
|
|
// AArch64_SEL_ZPZZ_B - 653
|
|
{10803, 3142, 4, 7 },
|
|
// AArch64_SEL_ZPZZ_D - 654
|
|
{10826, 3149, 4, 7 },
|
|
// AArch64_SEL_ZPZZ_H - 655
|
|
{10849, 3156, 4, 7 },
|
|
// AArch64_SEL_ZPZZ_S - 656
|
|
{10872, 3163, 4, 7 },
|
|
// AArch64_SMADDLrrr - 657
|
|
{10895, 3170, 4, 4 },
|
|
// AArch64_SMSUBLrrr - 658
|
|
{10912, 3174, 4, 4 },
|
|
// AArch64_SQDECB_XPiI - 659
|
|
{10930, 3178, 4, 7 },
|
|
{10940, 3185, 4, 7 },
|
|
// AArch64_SQDECB_XPiWdI - 661
|
|
{10956, 3192, 4, 7 },
|
|
{10972, 3199, 4, 7 },
|
|
// AArch64_SQDECD_XPiI - 663
|
|
{10994, 3206, 4, 7 },
|
|
{11004, 3213, 4, 7 },
|
|
// AArch64_SQDECD_XPiWdI - 665
|
|
{11020, 3220, 4, 7 },
|
|
{11036, 3227, 4, 7 },
|
|
// AArch64_SQDECD_ZPiI - 667
|
|
{11058, 3234, 4, 7 },
|
|
{11070, 3241, 4, 7 },
|
|
// AArch64_SQDECH_XPiI - 669
|
|
{11088, 3248, 4, 7 },
|
|
{11098, 3255, 4, 7 },
|
|
// AArch64_SQDECH_XPiWdI - 671
|
|
{11114, 3262, 4, 7 },
|
|
{11130, 3269, 4, 7 },
|
|
// AArch64_SQDECH_ZPiI - 673
|
|
{11152, 3276, 4, 7 },
|
|
{11164, 3283, 4, 7 },
|
|
// AArch64_SQDECW_XPiI - 675
|
|
{11182, 3290, 4, 7 },
|
|
{11192, 3297, 4, 7 },
|
|
// AArch64_SQDECW_XPiWdI - 677
|
|
{11208, 3304, 4, 7 },
|
|
{11224, 3311, 4, 7 },
|
|
// AArch64_SQDECW_ZPiI - 679
|
|
{11246, 3318, 4, 7 },
|
|
{11258, 3325, 4, 7 },
|
|
// AArch64_SQINCB_XPiI - 681
|
|
{11276, 3332, 4, 7 },
|
|
{11286, 3339, 4, 7 },
|
|
// AArch64_SQINCB_XPiWdI - 683
|
|
{11302, 3346, 4, 7 },
|
|
{11318, 3353, 4, 7 },
|
|
// AArch64_SQINCD_XPiI - 685
|
|
{11340, 3360, 4, 7 },
|
|
{11350, 3367, 4, 7 },
|
|
// AArch64_SQINCD_XPiWdI - 687
|
|
{11366, 3374, 4, 7 },
|
|
{11382, 3381, 4, 7 },
|
|
// AArch64_SQINCD_ZPiI - 689
|
|
{11404, 3388, 4, 7 },
|
|
{11416, 3395, 4, 7 },
|
|
// AArch64_SQINCH_XPiI - 691
|
|
{11434, 3402, 4, 7 },
|
|
{11444, 3409, 4, 7 },
|
|
// AArch64_SQINCH_XPiWdI - 693
|
|
{11460, 3416, 4, 7 },
|
|
{11476, 3423, 4, 7 },
|
|
// AArch64_SQINCH_ZPiI - 695
|
|
{11498, 3430, 4, 7 },
|
|
{11510, 3437, 4, 7 },
|
|
// AArch64_SQINCW_XPiI - 697
|
|
{11528, 3444, 4, 7 },
|
|
{11538, 3451, 4, 7 },
|
|
// AArch64_SQINCW_XPiWdI - 699
|
|
{11554, 3458, 4, 7 },
|
|
{11570, 3465, 4, 7 },
|
|
// AArch64_SQINCW_ZPiI - 701
|
|
{11592, 3472, 4, 7 },
|
|
{11604, 3479, 4, 7 },
|
|
// AArch64_SST1B_D_IMM - 703
|
|
{11622, 3486, 4, 5 },
|
|
// AArch64_SST1B_S_IMM - 704
|
|
{11646, 3491, 4, 5 },
|
|
// AArch64_SST1D_IMM - 705
|
|
{11670, 3496, 4, 5 },
|
|
// AArch64_SST1H_D_IMM - 706
|
|
{11694, 3501, 4, 5 },
|
|
// AArch64_SST1H_S_IMM - 707
|
|
{11718, 3506, 4, 5 },
|
|
// AArch64_SST1W_D_IMM - 708
|
|
{11742, 3511, 4, 5 },
|
|
// AArch64_SST1W_IMM - 709
|
|
{11766, 3516, 4, 5 },
|
|
// AArch64_ST1B_D_IMM - 710
|
|
{11790, 3521, 4, 7 },
|
|
// AArch64_ST1B_H_IMM - 711
|
|
{11812, 3528, 4, 7 },
|
|
// AArch64_ST1B_IMM - 712
|
|
{11834, 3535, 4, 7 },
|
|
// AArch64_ST1B_S_IMM - 713
|
|
{11856, 3542, 4, 7 },
|
|
// AArch64_ST1D_IMM - 714
|
|
{11878, 3549, 4, 7 },
|
|
// AArch64_ST1Fourv16b_POST - 715
|
|
{11900, 3556, 4, 5 },
|
|
// AArch64_ST1Fourv1d_POST - 716
|
|
{11920, 3561, 4, 5 },
|
|
// AArch64_ST1Fourv2d_POST - 717
|
|
{11940, 3566, 4, 5 },
|
|
// AArch64_ST1Fourv2s_POST - 718
|
|
{11960, 3571, 4, 5 },
|
|
// AArch64_ST1Fourv4h_POST - 719
|
|
{11980, 3576, 4, 5 },
|
|
// AArch64_ST1Fourv4s_POST - 720
|
|
{12000, 3581, 4, 5 },
|
|
// AArch64_ST1Fourv8b_POST - 721
|
|
{12020, 3586, 4, 5 },
|
|
// AArch64_ST1Fourv8h_POST - 722
|
|
{12040, 3591, 4, 5 },
|
|
// AArch64_ST1H_D_IMM - 723
|
|
{12060, 3596, 4, 7 },
|
|
// AArch64_ST1H_IMM - 724
|
|
{12082, 3603, 4, 7 },
|
|
// AArch64_ST1H_S_IMM - 725
|
|
{12104, 3610, 4, 7 },
|
|
// AArch64_ST1Onev16b_POST - 726
|
|
{12126, 3617, 4, 5 },
|
|
// AArch64_ST1Onev1d_POST - 727
|
|
{12146, 3622, 4, 5 },
|
|
// AArch64_ST1Onev2d_POST - 728
|
|
{12165, 3627, 4, 5 },
|
|
// AArch64_ST1Onev2s_POST - 729
|
|
{12185, 3632, 4, 5 },
|
|
// AArch64_ST1Onev4h_POST - 730
|
|
{12204, 3637, 4, 5 },
|
|
// AArch64_ST1Onev4s_POST - 731
|
|
{12223, 3642, 4, 5 },
|
|
// AArch64_ST1Onev8b_POST - 732
|
|
{12243, 3647, 4, 5 },
|
|
// AArch64_ST1Onev8h_POST - 733
|
|
{12262, 3652, 4, 5 },
|
|
// AArch64_ST1Threev16b_POST - 734
|
|
{12282, 3657, 4, 5 },
|
|
// AArch64_ST1Threev1d_POST - 735
|
|
{12302, 3662, 4, 5 },
|
|
// AArch64_ST1Threev2d_POST - 736
|
|
{12322, 3667, 4, 5 },
|
|
// AArch64_ST1Threev2s_POST - 737
|
|
{12342, 3672, 4, 5 },
|
|
// AArch64_ST1Threev4h_POST - 738
|
|
{12362, 3677, 4, 5 },
|
|
// AArch64_ST1Threev4s_POST - 739
|
|
{12382, 3682, 4, 5 },
|
|
// AArch64_ST1Threev8b_POST - 740
|
|
{12402, 3687, 4, 5 },
|
|
// AArch64_ST1Threev8h_POST - 741
|
|
{12422, 3692, 4, 5 },
|
|
// AArch64_ST1Twov16b_POST - 742
|
|
{12442, 3697, 4, 5 },
|
|
// AArch64_ST1Twov1d_POST - 743
|
|
{12462, 3702, 4, 5 },
|
|
// AArch64_ST1Twov2d_POST - 744
|
|
{12482, 3707, 4, 5 },
|
|
// AArch64_ST1Twov2s_POST - 745
|
|
{12502, 3712, 4, 5 },
|
|
// AArch64_ST1Twov4h_POST - 746
|
|
{12522, 3717, 4, 5 },
|
|
// AArch64_ST1Twov4s_POST - 747
|
|
{12542, 3722, 4, 5 },
|
|
// AArch64_ST1Twov8b_POST - 748
|
|
{12562, 3727, 4, 5 },
|
|
// AArch64_ST1Twov8h_POST - 749
|
|
{12582, 3732, 4, 5 },
|
|
// AArch64_ST1W_D_IMM - 750
|
|
{12602, 3737, 4, 7 },
|
|
// AArch64_ST1W_IMM - 751
|
|
{12624, 3744, 4, 7 },
|
|
// AArch64_ST1_MXIPXX_H_B - 752
|
|
{12646, 3751, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_H_D - 753
|
|
{12680, 3758, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_H_H - 754
|
|
{12714, 3765, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_H_Q - 755
|
|
{12748, 3772, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_H_S - 756
|
|
{12782, 3779, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_V_B - 757
|
|
{12816, 3786, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_V_D - 758
|
|
{12850, 3793, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_V_H - 759
|
|
{12884, 3800, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_V_Q - 760
|
|
{12918, 3807, 6, 7 },
|
|
// AArch64_ST1_MXIPXX_V_S - 761
|
|
{12952, 3814, 6, 7 },
|
|
// AArch64_ST1i16_POST - 762
|
|
{12986, 3821, 5, 6 },
|
|
// AArch64_ST1i32_POST - 763
|
|
{13009, 3827, 5, 6 },
|
|
// AArch64_ST1i64_POST - 764
|
|
{13032, 3833, 5, 6 },
|
|
// AArch64_ST1i8_POST - 765
|
|
{13055, 3839, 5, 6 },
|
|
// AArch64_ST2B_IMM - 766
|
|
{13078, 3845, 4, 7 },
|
|
// AArch64_ST2D_IMM - 767
|
|
{13100, 3852, 4, 7 },
|
|
// AArch64_ST2GOffset - 768
|
|
{13122, 3859, 3, 4 },
|
|
// AArch64_ST2H_IMM - 769
|
|
{13136, 3863, 4, 7 },
|
|
// AArch64_ST2Twov16b_POST - 770
|
|
{13158, 3870, 4, 5 },
|
|
// AArch64_ST2Twov2d_POST - 771
|
|
{13178, 3875, 4, 5 },
|
|
// AArch64_ST2Twov2s_POST - 772
|
|
{13198, 3880, 4, 5 },
|
|
// AArch64_ST2Twov4h_POST - 773
|
|
{13218, 3885, 4, 5 },
|
|
// AArch64_ST2Twov4s_POST - 774
|
|
{13238, 3890, 4, 5 },
|
|
// AArch64_ST2Twov8b_POST - 775
|
|
{13258, 3895, 4, 5 },
|
|
// AArch64_ST2Twov8h_POST - 776
|
|
{13278, 3900, 4, 5 },
|
|
// AArch64_ST2W_IMM - 777
|
|
{13298, 3905, 4, 7 },
|
|
// AArch64_ST2i16_POST - 778
|
|
{13320, 3912, 5, 6 },
|
|
// AArch64_ST2i32_POST - 779
|
|
{13343, 3918, 5, 6 },
|
|
// AArch64_ST2i64_POST - 780
|
|
{13366, 3924, 5, 6 },
|
|
// AArch64_ST2i8_POST - 781
|
|
{13390, 3930, 5, 6 },
|
|
// AArch64_ST3B_IMM - 782
|
|
{13413, 3936, 4, 7 },
|
|
// AArch64_ST3D_IMM - 783
|
|
{13435, 3943, 4, 7 },
|
|
// AArch64_ST3H_IMM - 784
|
|
{13457, 3950, 4, 7 },
|
|
// AArch64_ST3Threev16b_POST - 785
|
|
{13479, 3957, 4, 5 },
|
|
// AArch64_ST3Threev2d_POST - 786
|
|
{13499, 3962, 4, 5 },
|
|
// AArch64_ST3Threev2s_POST - 787
|
|
{13519, 3967, 4, 5 },
|
|
// AArch64_ST3Threev4h_POST - 788
|
|
{13539, 3972, 4, 5 },
|
|
// AArch64_ST3Threev4s_POST - 789
|
|
{13559, 3977, 4, 5 },
|
|
// AArch64_ST3Threev8b_POST - 790
|
|
{13579, 3982, 4, 5 },
|
|
// AArch64_ST3Threev8h_POST - 791
|
|
{13599, 3987, 4, 5 },
|
|
// AArch64_ST3W_IMM - 792
|
|
{13619, 3992, 4, 7 },
|
|
// AArch64_ST3i16_POST - 793
|
|
{13641, 3999, 5, 6 },
|
|
// AArch64_ST3i32_POST - 794
|
|
{13664, 4005, 5, 6 },
|
|
// AArch64_ST3i64_POST - 795
|
|
{13688, 4011, 5, 6 },
|
|
// AArch64_ST3i8_POST - 796
|
|
{13712, 4017, 5, 6 },
|
|
// AArch64_ST4B_IMM - 797
|
|
{13735, 4023, 4, 7 },
|
|
// AArch64_ST4D_IMM - 798
|
|
{13757, 4030, 4, 7 },
|
|
// AArch64_ST4Fourv16b_POST - 799
|
|
{13779, 4037, 4, 5 },
|
|
// AArch64_ST4Fourv2d_POST - 800
|
|
{13799, 4042, 4, 5 },
|
|
// AArch64_ST4Fourv2s_POST - 801
|
|
{13819, 4047, 4, 5 },
|
|
// AArch64_ST4Fourv4h_POST - 802
|
|
{13839, 4052, 4, 5 },
|
|
// AArch64_ST4Fourv4s_POST - 803
|
|
{13859, 4057, 4, 5 },
|
|
// AArch64_ST4Fourv8b_POST - 804
|
|
{13879, 4062, 4, 5 },
|
|
// AArch64_ST4Fourv8h_POST - 805
|
|
{13899, 4067, 4, 5 },
|
|
// AArch64_ST4H_IMM - 806
|
|
{13919, 4072, 4, 7 },
|
|
// AArch64_ST4W_IMM - 807
|
|
{13941, 4079, 4, 7 },
|
|
// AArch64_ST4i16_POST - 808
|
|
{13963, 4086, 5, 6 },
|
|
// AArch64_ST4i32_POST - 809
|
|
{13986, 4092, 5, 6 },
|
|
// AArch64_ST4i64_POST - 810
|
|
{14010, 4098, 5, 6 },
|
|
// AArch64_ST4i8_POST - 811
|
|
{14034, 4104, 5, 6 },
|
|
// AArch64_STGOffset - 812
|
|
{14057, 4110, 3, 4 },
|
|
// AArch64_STGPi - 813
|
|
{14070, 4114, 4, 5 },
|
|
// AArch64_STLURBi - 814
|
|
{14088, 4119, 3, 4 },
|
|
// AArch64_STLURHi - 815
|
|
{14104, 4123, 3, 4 },
|
|
// AArch64_STLURWi - 816
|
|
{14120, 4127, 3, 4 },
|
|
// AArch64_STLURXi - 817
|
|
{14120, 4131, 3, 4 },
|
|
// AArch64_STNPDi - 818
|
|
{14135, 4135, 4, 4 },
|
|
// AArch64_STNPQi - 819
|
|
{14135, 4139, 4, 4 },
|
|
// AArch64_STNPSi - 820
|
|
{14135, 4143, 4, 4 },
|
|
// AArch64_STNPWi - 821
|
|
{14135, 4147, 4, 4 },
|
|
// AArch64_STNPXi - 822
|
|
{14135, 4151, 4, 4 },
|
|
// AArch64_STNT1B_ZRI - 823
|
|
{14153, 4155, 4, 7 },
|
|
// AArch64_STNT1B_ZZR_D_REAL - 824
|
|
{14177, 4162, 4, 5 },
|
|
// AArch64_STNT1B_ZZR_S_REAL - 825
|
|
{14203, 4167, 4, 5 },
|
|
// AArch64_STNT1D_ZRI - 826
|
|
{14229, 4172, 4, 7 },
|
|
// AArch64_STNT1D_ZZR_D_REAL - 827
|
|
{14253, 4179, 4, 5 },
|
|
// AArch64_STNT1H_ZRI - 828
|
|
{14279, 4184, 4, 7 },
|
|
// AArch64_STNT1H_ZZR_D_REAL - 829
|
|
{14303, 4191, 4, 5 },
|
|
// AArch64_STNT1H_ZZR_S_REAL - 830
|
|
{14329, 4196, 4, 5 },
|
|
// AArch64_STNT1W_ZRI - 831
|
|
{14355, 4201, 4, 7 },
|
|
// AArch64_STNT1W_ZZR_D_REAL - 832
|
|
{14379, 4208, 4, 5 },
|
|
// AArch64_STNT1W_ZZR_S_REAL - 833
|
|
{14405, 4213, 4, 5 },
|
|
// AArch64_STPDi - 834
|
|
{14431, 4218, 4, 4 },
|
|
// AArch64_STPQi - 835
|
|
{14431, 4222, 4, 4 },
|
|
// AArch64_STPSi - 836
|
|
{14431, 4226, 4, 4 },
|
|
// AArch64_STPWi - 837
|
|
{14431, 4230, 4, 4 },
|
|
// AArch64_STPXi - 838
|
|
{14431, 4234, 4, 4 },
|
|
// AArch64_STRBBroX - 839
|
|
{14448, 4238, 5, 5 },
|
|
// AArch64_STRBBui - 840
|
|
{14466, 4243, 3, 3 },
|
|
// AArch64_STRBroX - 841
|
|
{14480, 4246, 5, 5 },
|
|
// AArch64_STRBui - 842
|
|
{14497, 4251, 3, 3 },
|
|
// AArch64_STRDroX - 843
|
|
{14480, 4254, 5, 5 },
|
|
// AArch64_STRDui - 844
|
|
{14497, 4259, 3, 3 },
|
|
// AArch64_STRHHroX - 845
|
|
{14510, 4262, 5, 5 },
|
|
// AArch64_STRHHui - 846
|
|
{14528, 4267, 3, 3 },
|
|
// AArch64_STRHroX - 847
|
|
{14480, 4270, 5, 5 },
|
|
// AArch64_STRHui - 848
|
|
{14497, 4275, 3, 3 },
|
|
// AArch64_STRQroX - 849
|
|
{14480, 4278, 5, 5 },
|
|
// AArch64_STRQui - 850
|
|
{14497, 4283, 3, 3 },
|
|
// AArch64_STRSroX - 851
|
|
{14480, 4286, 5, 5 },
|
|
// AArch64_STRSui - 852
|
|
{14497, 4291, 3, 3 },
|
|
// AArch64_STRWroX - 853
|
|
{14480, 4294, 5, 5 },
|
|
// AArch64_STRWui - 854
|
|
{14497, 4299, 3, 3 },
|
|
// AArch64_STRXroX - 855
|
|
{14480, 4302, 5, 5 },
|
|
// AArch64_STRXui - 856
|
|
{14497, 4307, 3, 3 },
|
|
// AArch64_STR_PXI - 857
|
|
{14542, 4310, 3, 6 },
|
|
// AArch64_STR_ZA - 858
|
|
{14557, 4316, 5, 6 },
|
|
// AArch64_STR_ZXI - 859
|
|
{14542, 4322, 3, 6 },
|
|
// AArch64_STTRBi - 860
|
|
{14582, 4328, 3, 3 },
|
|
// AArch64_STTRHi - 861
|
|
{14597, 4331, 3, 3 },
|
|
// AArch64_STTRWi - 862
|
|
{14612, 4334, 3, 3 },
|
|
// AArch64_STTRXi - 863
|
|
{14612, 4337, 3, 3 },
|
|
// AArch64_STURBBi - 864
|
|
{14626, 4340, 3, 3 },
|
|
// AArch64_STURBi - 865
|
|
{14641, 4343, 3, 3 },
|
|
// AArch64_STURDi - 866
|
|
{14641, 4346, 3, 3 },
|
|
// AArch64_STURHHi - 867
|
|
{14655, 4349, 3, 3 },
|
|
// AArch64_STURHi - 868
|
|
{14641, 4352, 3, 3 },
|
|
// AArch64_STURQi - 869
|
|
{14641, 4355, 3, 3 },
|
|
// AArch64_STURSi - 870
|
|
{14641, 4358, 3, 3 },
|
|
// AArch64_STURWi - 871
|
|
{14641, 4361, 3, 3 },
|
|
// AArch64_STURXi - 872
|
|
{14641, 4364, 3, 3 },
|
|
// AArch64_STZ2GOffset - 873
|
|
{14670, 4367, 3, 4 },
|
|
// AArch64_STZGOffset - 874
|
|
{14685, 4371, 3, 4 },
|
|
// AArch64_SUBSWri - 875
|
|
{14699, 4375, 4, 2 },
|
|
// AArch64_SUBSWrs - 876
|
|
{14712, 4377, 4, 4 },
|
|
{14723, 4381, 4, 3 },
|
|
{14738, 4384, 4, 4 },
|
|
{14750, 4388, 4, 3 },
|
|
{14766, 4391, 4, 4 },
|
|
// AArch64_SUBSWrx - 881
|
|
{14712, 4395, 4, 4 },
|
|
{14782, 4399, 4, 3 },
|
|
{14766, 4402, 4, 4 },
|
|
// AArch64_SUBSXri - 884
|
|
{14699, 4406, 4, 2 },
|
|
// AArch64_SUBSXrs - 885
|
|
{14712, 4408, 4, 4 },
|
|
{14723, 4412, 4, 3 },
|
|
{14738, 4415, 4, 4 },
|
|
{14750, 4419, 4, 3 },
|
|
{14766, 4422, 4, 4 },
|
|
// AArch64_SUBSXrx - 890
|
|
{14782, 4426, 4, 3 },
|
|
// AArch64_SUBSXrx64 - 891
|
|
{14712, 4429, 4, 4 },
|
|
{14782, 4433, 4, 3 },
|
|
{14766, 4436, 4, 4 },
|
|
// AArch64_SUBWrs - 894
|
|
{14797, 4440, 4, 4 },
|
|
{14808, 4444, 4, 3 },
|
|
{14823, 4447, 4, 4 },
|
|
// AArch64_SUBWrx - 897
|
|
{14823, 4451, 4, 4 },
|
|
{14823, 4455, 4, 4 },
|
|
// AArch64_SUBXrs - 899
|
|
{14797, 4459, 4, 4 },
|
|
{14808, 4463, 4, 3 },
|
|
{14823, 4466, 4, 4 },
|
|
// AArch64_SUBXrx64 - 902
|
|
{14823, 4470, 4, 4 },
|
|
{14823, 4474, 4, 4 },
|
|
// AArch64_SYSxt - 904
|
|
{14838, 4478, 5, 5 },
|
|
// AArch64_UBFMWri - 905
|
|
{14861, 4483, 4, 4 },
|
|
{14876, 4487, 4, 4 },
|
|
{14888, 4491, 4, 4 },
|
|
// AArch64_UBFMXri - 908
|
|
{14861, 4495, 4, 4 },
|
|
{14876, 4499, 4, 4 },
|
|
{14888, 4503, 4, 4 },
|
|
{14900, 4507, 4, 4 },
|
|
// AArch64_UMADDLrrr - 912
|
|
{14912, 4511, 4, 4 },
|
|
// AArch64_UMOVvi32 - 913
|
|
{14929, 4515, 3, 3 },
|
|
// AArch64_UMOVvi32_idx0 - 914
|
|
{14929, 4518, 3, 5 },
|
|
// AArch64_UMOVvi64 - 915
|
|
{14948, 4523, 3, 3 },
|
|
// AArch64_UMOVvi64_idx0 - 916
|
|
{14948, 4526, 3, 5 },
|
|
// AArch64_UMSUBLrrr - 917
|
|
{14967, 4531, 4, 4 },
|
|
// AArch64_UQDECB_WPiI - 918
|
|
{14985, 4535, 4, 7 },
|
|
{14995, 4542, 4, 7 },
|
|
// AArch64_UQDECB_XPiI - 920
|
|
{14985, 4549, 4, 7 },
|
|
{14995, 4556, 4, 7 },
|
|
// AArch64_UQDECD_WPiI - 922
|
|
{15011, 4563, 4, 7 },
|
|
{15021, 4570, 4, 7 },
|
|
// AArch64_UQDECD_XPiI - 924
|
|
{15011, 4577, 4, 7 },
|
|
{15021, 4584, 4, 7 },
|
|
// AArch64_UQDECD_ZPiI - 926
|
|
{15037, 4591, 4, 7 },
|
|
{15049, 4598, 4, 7 },
|
|
// AArch64_UQDECH_WPiI - 928
|
|
{15067, 4605, 4, 7 },
|
|
{15077, 4612, 4, 7 },
|
|
// AArch64_UQDECH_XPiI - 930
|
|
{15067, 4619, 4, 7 },
|
|
{15077, 4626, 4, 7 },
|
|
// AArch64_UQDECH_ZPiI - 932
|
|
{15093, 4633, 4, 7 },
|
|
{15105, 4640, 4, 7 },
|
|
// AArch64_UQDECW_WPiI - 934
|
|
{15123, 4647, 4, 7 },
|
|
{15133, 4654, 4, 7 },
|
|
// AArch64_UQDECW_XPiI - 936
|
|
{15123, 4661, 4, 7 },
|
|
{15133, 4668, 4, 7 },
|
|
// AArch64_UQDECW_ZPiI - 938
|
|
{15149, 4675, 4, 7 },
|
|
{15161, 4682, 4, 7 },
|
|
// AArch64_UQINCB_WPiI - 940
|
|
{15179, 4689, 4, 7 },
|
|
{15189, 4696, 4, 7 },
|
|
// AArch64_UQINCB_XPiI - 942
|
|
{15179, 4703, 4, 7 },
|
|
{15189, 4710, 4, 7 },
|
|
// AArch64_UQINCD_WPiI - 944
|
|
{15205, 4717, 4, 7 },
|
|
{15215, 4724, 4, 7 },
|
|
// AArch64_UQINCD_XPiI - 946
|
|
{15205, 4731, 4, 7 },
|
|
{15215, 4738, 4, 7 },
|
|
// AArch64_UQINCD_ZPiI - 948
|
|
{15231, 4745, 4, 7 },
|
|
{15243, 4752, 4, 7 },
|
|
// AArch64_UQINCH_WPiI - 950
|
|
{15261, 4759, 4, 7 },
|
|
{15271, 4766, 4, 7 },
|
|
// AArch64_UQINCH_XPiI - 952
|
|
{15261, 4773, 4, 7 },
|
|
{15271, 4780, 4, 7 },
|
|
// AArch64_UQINCH_ZPiI - 954
|
|
{15287, 4787, 4, 7 },
|
|
{15299, 4794, 4, 7 },
|
|
// AArch64_UQINCW_WPiI - 956
|
|
{15317, 4801, 4, 7 },
|
|
{15327, 4808, 4, 7 },
|
|
// AArch64_UQINCW_XPiI - 958
|
|
{15317, 4815, 4, 7 },
|
|
{15327, 4822, 4, 7 },
|
|
// AArch64_UQINCW_ZPiI - 960
|
|
{15343, 4829, 4, 7 },
|
|
{15355, 4836, 4, 7 },
|
|
// AArch64_XPACLRI - 962
|
|
{15373, 4843, 0, 1 },
|
|
// AArch64_ZERO_M - 963
|
|
{15381, 4844, 1, 2 },
|
|
{15391, 4846, 1, 2 },
|
|
{15404, 4848, 1, 2 },
|
|
{15417, 4850, 1, 2 },
|
|
{15430, 4852, 1, 2 },
|
|
{15443, 4854, 1, 2 },
|
|
{15456, 4856, 1, 2 },
|
|
{15469, 4858, 1, 2 },
|
|
{15488, 4860, 1, 2 },
|
|
{15507, 4862, 1, 2 },
|
|
{15526, 4864, 1, 2 },
|
|
{15545, 4866, 1, 2 },
|
|
{15570, 4868, 1, 2 },
|
|
{15595, 4870, 1, 2 },
|
|
{15620, 4872, 1, 2 },
|
|
};
|
|
|
|
static const AliasPatternCond Conds[] = {
|
|
// (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
// (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
// (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 124
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 128
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 132
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 139
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 145
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 151
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (AUTIA1716) - 157
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (AUTIASP) - 158
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (AUTIAZ) - 159
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (AUTIB1716) - 160
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (AUTIBSP) - 161
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (AUTIBZ) - 162
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 163
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 167
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 171
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 175
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (CLREX 15) - 179
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 180
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 186
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 192
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 198
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 204
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 210
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 216
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 222
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 228
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 234
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 240
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 246
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 252
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 259
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 266
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 273
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 280
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 287
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 294
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 301
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 308
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 313
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 318
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 323
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 328
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 332
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 336
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 340
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 344
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 348
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 352
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 356
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 360
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 364
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_Custom, 4},
|
|
// (DCPS1 0) - 368
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (DCPS2 0) - 369
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (DCPS3 0) - 370
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureEL3},
|
|
// (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 372
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 379
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 386
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 393
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 400
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 407
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 414
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 421
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 428
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 435
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 442
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 456
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 463
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DSB 0) - 470
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (DSB 4) - 471
|
|
{AliasPatternCond_K_Imm, 4},
|
|
// (DSB { 1, 1, 0, 0 }) - 472
|
|
{AliasPatternCond_K_Imm, 12},
|
|
{AliasPatternCond_K_Feature, AArch64_HasV8_0rOps},
|
|
// (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 474
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 5},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 479
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 6},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 484
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 7},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 489
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 494
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 499
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 504
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 508
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_D ZPR64:$Zd, 0, 0) - 512
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 518
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_H ZPR16:$Zd, 0, 0) - 522
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 528
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZI_S ZPR32:$Zd, 0, 0) - 532
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 538
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 543
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 548
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 553
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 558
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 564
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 569
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 575
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 580
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 586
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 591
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 597
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 602
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 608
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 613
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 617
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 621
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 628
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 636
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 643
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 649
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 655
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 661
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 666
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 671
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 676
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 681
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 686
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 691
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 696
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 701
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 706
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 711
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 714
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 717
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 723
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 729
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 735
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 739
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 743
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 747
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 752
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 757
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 762
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 767
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 772
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 777
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 782
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 787
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 792
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 797
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 802
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 807
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 812
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 817
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 822
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 827
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 832
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 837
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 842
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 847
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 852
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 857
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 862
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (HINT { 0, 0, 0 }) - 867
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (HINT { 0, 0, 1 }) - 868
|
|
{AliasPatternCond_K_Imm, 1},
|
|
// (HINT { 0, 1, 0 }) - 869
|
|
{AliasPatternCond_K_Imm, 2},
|
|
// (HINT { 0, 1, 1 }) - 870
|
|
{AliasPatternCond_K_Imm, 3},
|
|
// (HINT { 1, 0, 0 }) - 871
|
|
{AliasPatternCond_K_Imm, 4},
|
|
// (HINT { 1, 0, 1 }) - 872
|
|
{AliasPatternCond_K_Imm, 5},
|
|
// (HINT { 1, 1, 0 }) - 873
|
|
{AliasPatternCond_K_Imm, 6},
|
|
// (HINT { 1, 0, 0, 0, 0 }) - 874
|
|
{AliasPatternCond_K_Imm, 16},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRAS},
|
|
// (HINT 20) - 876
|
|
{AliasPatternCond_K_Imm, 20},
|
|
// (HINT 32) - 877
|
|
{AliasPatternCond_K_Imm, 32},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureBranchTargetId},
|
|
// (HINT btihint_op:$op) - 879
|
|
{AliasPatternCond_K_Custom, 8},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureBranchTargetId},
|
|
// (HINT psbhint_op:$op) - 881
|
|
{AliasPatternCond_K_Custom, 9},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSPE},
|
|
// (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 883
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 890
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 897
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 904
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 911
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 918
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 925
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 932
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 939
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 946
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 953
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 960
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 967
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 974
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 981
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 987
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 993
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 999
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1005
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1011
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1017
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1023
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1029
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1035
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1041
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1046
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1051
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1056
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1061
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1066
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1071
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1076
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1081
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (ISB 15) - 1085
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1086
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1093
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1100
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1107
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1114
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1121
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1126
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1131
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1136
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1141
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1146
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1151
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1156
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1161
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1168
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1175
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1182
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1187
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1192
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1197
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1202
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1207
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1212
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1217
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1222
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1229
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1236
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1243
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1250
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1257
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1264
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1271
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1278
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64},
|
|
// (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1284
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64},
|
|
// (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1290
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64},
|
|
// (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1296
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64},
|
|
// (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1302
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1309
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1316
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1323
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1330
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1337
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1344
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1351
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1358
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1365
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1372
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1379
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1386
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1391
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1396
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1401
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1406
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1411
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1416
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1421
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1426
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1433
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1440
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1447
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1454
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1461
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1468
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1473
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1478
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1483
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1488
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1493
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1498
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1503
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1508
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1513
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1518
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1523
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1528
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1533
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1538
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1543
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1548
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1555
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1562
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1569
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1576
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1583
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1590
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1597
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1604
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1611
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1618
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1625
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 1632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 1639
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 1646
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 1653
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1660
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1667
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1674
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1681
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1686
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1691
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1696
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1701
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1706
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1711
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1716
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1721
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1726
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1731
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1736
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1741
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1746
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1751
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1756
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 1763
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 1770
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 1777
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 1784
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1791
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1798
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1805
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1812
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1817
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1822
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1827
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1832
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1837
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1842
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1847
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1852
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1857
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1862
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1867
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1872
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1877
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1882
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1887
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 1894
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 1901
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 1908
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 1915
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1922
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1929
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1936
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1941
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1946
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1951
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1956
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1961
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1966
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1971
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1978
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1983
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1988
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1993
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1998
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2003
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2008
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2013
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2018
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2025
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2032
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2039
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2046
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2053
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2057
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2061
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2065
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2069
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2073
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2077
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2081
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2085
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2089
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2093
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2097
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2101
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2105
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2109
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2113
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2117
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2121
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2125
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2129
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2133
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2137
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2141
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2145
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2149
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2153
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2157
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2161
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2165
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2169
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2173
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2177
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2181
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2185
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2190
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2195
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2200
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2205
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2210
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2215
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2220
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2225
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2230
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2235
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2240
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2245
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2250
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2255
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2260
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 2265
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2270
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2275
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2280
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2285
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2290
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2295
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2300
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2305
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2310
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2315
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2320
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2325
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2330
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2335
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2340
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2345
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 2350
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 2354
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 2358
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 2362
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2366
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2370
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2377
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2382
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2387
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2394
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2399
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2406
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2411
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2416
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2421
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2426
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2431
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2436
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2441
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2448
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2453
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 2458
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 2462
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2466
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 2470
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 2474
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2478
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2482
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2486
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2490
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 2495
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2498
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2503
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2506
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2511
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2514
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 2519
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2522
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2527
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2530
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2535
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2538
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2543
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2546
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2551
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2554
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2559
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2562
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2567
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2570
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 2575
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2578
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2583
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2586
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 2591
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2594
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 2599
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 2602
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 2608
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 2614
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2620
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2624
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2628
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2632
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2636
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2640
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2644
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2648
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2652
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2656
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2660
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2664
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2668
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2672
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2676
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2680
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2684
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2688
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2692
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2696
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2700
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2704
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2708
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2712
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2716
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2719
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2722
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2725
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2728
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2731
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2734
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2737
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2740
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2743
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2747
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2751
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2755
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2759
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2763
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2767
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2771
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2775
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2779
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2783
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2787
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2791
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2795
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2799
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2803
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureLSE},
|
|
// (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2807
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2810
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2813
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2816
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2819
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2822
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2825
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2828
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2831
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2834
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2837
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2840
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 2843
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 2846
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2849
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
// (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2853
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 2857
|
|
{AliasPatternCond_K_Imm, 3},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 2860
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 2863
|
|
{AliasPatternCond_K_Imm, 2},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 2866
|
|
{AliasPatternCond_K_Imm, 3},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 2869
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 2872
|
|
{AliasPatternCond_K_Imm, 2},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2875
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
// (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2879
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (NOTv16i8 V128:$Vd, V128:$Vn) - 2883
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
// (NOTv8i8 V64:$Vd, V64:$Vn) - 2885
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
// (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 2887
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 2891
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2894
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 2898
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 2902
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2905
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2909
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 2916
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2920
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 2924
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2928
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2932
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 2939
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 2945
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 2},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 2951
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Custom, 3},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 2957
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2963
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 2966
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_TiedReg, 1},
|
|
// (PACIA1716) - 2969
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PACIASP) - 2970
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PACIAZ) - 2971
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PACIB1716) - 2972
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PACIBSP) - 2973
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PACIBZ) - 2974
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2975
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2980
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2987
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2992
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2997
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3004
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3009
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3014
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3021
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3026
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 3031
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 3034
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3037
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3042
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3049
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 3054
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 3059
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 3064
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 3069
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 3074
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 3079
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 3084
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 3089
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (RET LR) - 3094
|
|
{AliasPatternCond_K_Reg, AArch64_LR},
|
|
// (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 3095
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 3098
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SBCWr GPR32:$dst, WZR, GPR32:$src) - 3101
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SBCXr GPR64:$dst, XZR, GPR64:$src) - 3104
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 3107
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 3111
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 7},
|
|
// (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 3115
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 3119
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 63},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 3123
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 7},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 3127
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 3131
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
// (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 3135
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 3142
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 3149
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 3156
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 3163
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_TiedReg, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3170
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3174
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3178
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3185
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3192
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3199
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3206
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3213
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3220
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3227
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3234
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3241
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3248
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3255
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3262
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3269
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3276
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3283
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3290
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3297
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3304
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3311
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3318
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3325
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3332
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3339
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3346
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3353
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3360
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3367
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3374
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3381
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3388
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3395
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3402
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3409
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3416
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3423
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3430
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3437
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3444
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3451
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3458
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 3465
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3472
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3479
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3486
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3491
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3496
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3501
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3506
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3511
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3516
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE},
|
|
// (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3521
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3528
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3535
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3542
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3549
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 3556
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 3561
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 3566
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 3571
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 3576
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 3581
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 3586
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 3591
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3596
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3603
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3610
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 3617
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 3622
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 3627
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 3632
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 3637
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 3642
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 3647
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 3652
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3657
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 3662
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3667
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3672
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3677
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3682
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3687
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3692
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3697
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 3702
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3707
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3712
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3717
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3722
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3727
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3732
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3737
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3744
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3751
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3758
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3765
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3772
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3779
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3786
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3793
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3800
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3807
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3814
|
|
{AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 3821
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 3827
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 3833
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 3839
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3845
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3852
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3859
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3863
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3870
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3875
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3880
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3885
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3890
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3895
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3900
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3905
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 3912
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 3918
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 3924
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 3930
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3936
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3943
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3950
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3957
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3962
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3967
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3972
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3977
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3982
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3987
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3992
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 3999
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 4005
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 4011
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 4017
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4023
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4030
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 4037
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 4042
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 4047
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 4052
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 4057
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 4062
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 4067
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4072
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4079
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 4086
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 4092
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 4098
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 4104
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4110
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4114
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4119
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4123
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4127
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4131
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO},
|
|
// (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 4135
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 4139
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 4143
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 4147
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4151
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4155
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4162
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4167
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4172
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4179
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4184
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4191
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4196
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4201
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4208
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4213
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSVE2},
|
|
// (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 4218
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 4222
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 4226
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 4230
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4234
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4238
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4243
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4246
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4251
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4254
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4259
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4262
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4267
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4270
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4275
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4278
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4283
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4286
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4291
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4294
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4299
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4302
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 4307
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 4310
|
|
{AliasPatternCond_K_RegClass, AArch64_PPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 4316
|
|
{AliasPatternCond_K_RegClass, AArch64_MPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 4322
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4328
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4331
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4334
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4337
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4340
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4343
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4346
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4349
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4352
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4355
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4358
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4361
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4364
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4367
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4371
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureMTE},
|
|
// (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 4375
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
// (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 4377
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 4381
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4384
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 4388
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4391
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 4395
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 4399
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 4402
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 4406
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
// (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 4408
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 4412
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4415
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 4419
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4422
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 4426
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 4429
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 4433
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 4436
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4440
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 4444
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_WZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
// (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4447
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 4451
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 4455
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 16},
|
|
// (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4459
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 4463
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
// (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4466
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
// (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 4470
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 4474
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 24},
|
|
// (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 4478
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4483
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4487
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 7},
|
|
// (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4491
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4495
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 63},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4499
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 7},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4503
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 15},
|
|
// (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4507
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Imm, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
// (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4511
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 4515
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 4518
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 4523
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureNEON},
|
|
// (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 4526
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureNEON},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4531
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Reg, AArch64_XZR},
|
|
// (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4535
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4542
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4549
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4556
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4563
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4570
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4577
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4584
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4591
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4598
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4605
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4612
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4619
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4626
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4633
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4640
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4647
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4654
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4661
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4668
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4675
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4682
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4689
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4696
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4703
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4710
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4717
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4724
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4731
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4738
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4745
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4752
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4759
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4766
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4773
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4780
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4787
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4794
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4801
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4808
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4815
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4822
|
|
{AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4829
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 31},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4836
|
|
{AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Ignore, 0},
|
|
{AliasPatternCond_K_Imm, 1},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureSVE},
|
|
{AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE},
|
|
{AliasPatternCond_K_EndOrFeatures, 0},
|
|
// (XPACLRI) - 4843
|
|
{AliasPatternCond_K_Feature, AArch64_FeaturePAuth},
|
|
// (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 4844
|
|
{AliasPatternCond_K_Imm, 255},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 4846
|
|
{AliasPatternCond_K_Imm, 85},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 4848
|
|
{AliasPatternCond_K_Imm, 170},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 4850
|
|
{AliasPatternCond_K_Imm, 17},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 4852
|
|
{AliasPatternCond_K_Imm, 34},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 4854
|
|
{AliasPatternCond_K_Imm, 68},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 4856
|
|
{AliasPatternCond_K_Imm, 136},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 4858
|
|
{AliasPatternCond_K_Imm, 51},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 4860
|
|
{AliasPatternCond_K_Imm, 153},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 4862
|
|
{AliasPatternCond_K_Imm, 102},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 4864
|
|
{AliasPatternCond_K_Imm, 204},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 4866
|
|
{AliasPatternCond_K_Imm, 119},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 4868
|
|
{AliasPatternCond_K_Imm, 187},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 4870
|
|
{AliasPatternCond_K_Imm, 221},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
// (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 4872
|
|
{AliasPatternCond_K_Imm, 238},
|
|
{AliasPatternCond_K_Feature, AArch64_FeatureSME},
|
|
};
|
|
|
|
static const char AsmStrings[] =
|
|
/* 0 */ "cmn $\x02, $\xFF\x03\x01\0"
|
|
/* 13 */ "cmn $\x02, $\x03\0"
|
|
/* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 39 */ "adds $\x01, $\x02, $\x03\0"
|
|
/* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0"
|
|
/* 70 */ "mov $\x01, $\x02\0"
|
|
/* 81 */ "add $\x01, $\x02, $\x03\0"
|
|
/* 96 */ "tst $\x02, $\xFF\x03\x04\0"
|
|
/* 109 */ "tst $\x02, $\x03\0"
|
|
/* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 135 */ "ands $\x01, $\x02, $\x03\0"
|
|
/* 151 */ "tst $\x02, $\xFF\x03\x05\0"
|
|
/* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 188 */ "and $\x01, $\x02, $\x03\0"
|
|
/* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 289 */ "autia1716\0"
|
|
/* 299 */ "autiasp\0"
|
|
/* 307 */ "autiaz\0"
|
|
/* 314 */ "autib1716\0"
|
|
/* 324 */ "autibsp\0"
|
|
/* 332 */ "autibz\0"
|
|
/* 339 */ "bics $\x01, $\x02, $\x03\0"
|
|
/* 355 */ "bic $\x01, $\x02, $\x03\0"
|
|
/* 370 */ "clrex\0"
|
|
/* 376 */ "cntb $\x01\0"
|
|
/* 384 */ "cntb $\x01, $\xFF\x02\x0E\0"
|
|
/* 398 */ "cntd $\x01\0"
|
|
/* 406 */ "cntd $\x01, $\xFF\x02\x0E\0"
|
|
/* 420 */ "cnth $\x01\0"
|
|
/* 428 */ "cnth $\x01, $\xFF\x02\x0E\0"
|
|
/* 442 */ "cntw $\x01\0"
|
|
/* 450 */ "cntw $\x01, $\xFF\x02\x0E\0"
|
|
/* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0"
|
|
/* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0"
|
|
/* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0"
|
|
/* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0"
|
|
/* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0"
|
|
/* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0"
|
|
/* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0"
|
|
/* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0"
|
|
/* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0"
|
|
/* 732 */ "cset $\x01, $\xFF\x04\x14\0"
|
|
/* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 764 */ "csetm $\x01, $\xFF\x04\x14\0"
|
|
/* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0"
|
|
/* 815 */ "dcps1\0"
|
|
/* 821 */ "dcps2\0"
|
|
/* 827 */ "dcps3\0"
|
|
/* 833 */ "decb $\x01\0"
|
|
/* 841 */ "decb $\x01, $\xFF\x03\x0E\0"
|
|
/* 855 */ "decd $\x01\0"
|
|
/* 863 */ "decd $\x01, $\xFF\x03\x0E\0"
|
|
/* 877 */ "decd $\xFF\x01\x10\0"
|
|
/* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 903 */ "dech $\x01\0"
|
|
/* 911 */ "dech $\x01, $\xFF\x03\x0E\0"
|
|
/* 925 */ "dech $\xFF\x01\x09\0"
|
|
/* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 951 */ "decw $\x01\0"
|
|
/* 959 */ "decw $\x01, $\xFF\x03\x0E\0"
|
|
/* 973 */ "decw $\xFF\x01\x0B\0"
|
|
/* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 999 */ "ssbb\0"
|
|
/* 1004 */ "pssbb\0"
|
|
/* 1010 */ "dfb\0"
|
|
/* 1014 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0"
|
|
/* 1029 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0"
|
|
/* 1044 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0"
|
|
/* 1059 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
|
|
/* 1075 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
|
|
/* 1091 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
|
|
/* 1107 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0"
|
|
/* 1122 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0"
|
|
/* 1137 */ "fmov $\xFF\x01\x10, #0.0\0"
|
|
/* 1153 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0"
|
|
/* 1168 */ "fmov $\xFF\x01\x09, #0.0\0"
|
|
/* 1184 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0"
|
|
/* 1199 */ "fmov $\xFF\x01\x0B, #0.0\0"
|
|
/* 1215 */ "mov $\xFF\x01\x06, $\x02\0"
|
|
/* 1228 */ "mov $\xFF\x01\x10, $\x02\0"
|
|
/* 1241 */ "mov $\xFF\x01\x09, $\x02\0"
|
|
/* 1254 */ "mov $\xFF\x01\x0B, $\x02\0"
|
|
/* 1267 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0"
|
|
/* 1282 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0"
|
|
/* 1301 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0"
|
|
/* 1316 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0"
|
|
/* 1335 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0"
|
|
/* 1350 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0"
|
|
/* 1369 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0"
|
|
/* 1384 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0"
|
|
/* 1403 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0"
|
|
/* 1418 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0"
|
|
/* 1437 */ "eon $\x01, $\x02, $\x03\0"
|
|
/* 1452 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 1476 */ "eor $\x01, $\x02, $\x03\0"
|
|
/* 1491 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
|
|
/* 1514 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 1535 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 1556 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 1577 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1610 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1643 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1676 */ "mov $\xFF\x01\x1C, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1742 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1775 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1808 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1841 */ "mov $\xFF\x01\x1C, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1874 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, $\xFF\x05\x20]\0"
|
|
/* 1907 */ "ror $\x01, $\x02, $\x04\0"
|
|
/* 1922 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 1946 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 1970 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0"
|
|
/* 1994 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0"
|
|
/* 2010 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0"
|
|
/* 2026 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0"
|
|
/* 2042 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2068 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2094 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2120 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2146 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2172 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2199 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2226 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2253 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2280 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2307 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2333 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2359 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2387 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2415 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2443 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2471 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2499 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2528 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2557 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2586 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2615 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2644 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 2672 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 2700 */ "nop\0"
|
|
/* 2704 */ "yield\0"
|
|
/* 2710 */ "wfe\0"
|
|
/* 2714 */ "wfi\0"
|
|
/* 2718 */ "sev\0"
|
|
/* 2722 */ "sevl\0"
|
|
/* 2727 */ "dgh\0"
|
|
/* 2731 */ "esb\0"
|
|
/* 2735 */ "csdb\0"
|
|
/* 2740 */ "bti\0"
|
|
/* 2744 */ "bti $\xFF\x01\x25\0"
|
|
/* 2753 */ "psb $\xFF\x01\x26\0"
|
|
/* 2762 */ "incb $\x01\0"
|
|
/* 2770 */ "incb $\x01, $\xFF\x03\x0E\0"
|
|
/* 2784 */ "incd $\x01\0"
|
|
/* 2792 */ "incd $\x01, $\xFF\x03\x0E\0"
|
|
/* 2806 */ "incd $\xFF\x01\x10\0"
|
|
/* 2816 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 2832 */ "inch $\x01\0"
|
|
/* 2840 */ "inch $\x01, $\xFF\x03\x0E\0"
|
|
/* 2854 */ "inch $\xFF\x01\x09\0"
|
|
/* 2864 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 2880 */ "incw $\x01\0"
|
|
/* 2888 */ "incw $\x01, $\xFF\x03\x0E\0"
|
|
/* 2902 */ "incw $\xFF\x01\x0B\0"
|
|
/* 2912 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 2928 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x06\0"
|
|
/* 2961 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x10\0"
|
|
/* 2994 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x09\0"
|
|
/* 3027 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x1C\0"
|
|
/* 3060 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x0B\0"
|
|
/* 3093 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x06\0"
|
|
/* 3126 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x10\0"
|
|
/* 3159 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x09\0"
|
|
/* 3192 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x1C\0"
|
|
/* 3225 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, $\xFF\x05\x0B\0"
|
|
/* 3258 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0"
|
|
/* 3277 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0"
|
|
/* 3304 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0"
|
|
/* 3323 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0"
|
|
/* 3350 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0"
|
|
/* 3369 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0"
|
|
/* 3396 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0"
|
|
/* 3415 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0"
|
|
/* 3442 */ "irg $\x01, $\x02\0"
|
|
/* 3453 */ "isb\0"
|
|
/* 3457 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3481 */ "ld1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3505 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3529 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3553 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3577 */ "ld1 $\xFF\x02\x29, [$\x01], #64\0"
|
|
/* 3597 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0"
|
|
/* 3617 */ "ld1 $\xFF\x02\x2B, [$\x01], #64\0"
|
|
/* 3637 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 3657 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 3677 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 3697 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 3717 */ "ld1 $\xFF\x02\x30, [$\x01], #64\0"
|
|
/* 3737 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3761 */ "ld1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3785 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3809 */ "ld1 $\xFF\x02\x29, [$\x01], #16\0"
|
|
/* 3829 */ "ld1 $\xFF\x02\x2A, [$\x01], #8\0"
|
|
/* 3848 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0"
|
|
/* 3868 */ "ld1 $\xFF\x02\x2C, [$\x01], #8\0"
|
|
/* 3887 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 3906 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 3926 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0"
|
|
/* 3945 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 3965 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 3990 */ "ld1rb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4015 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4040 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4065 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4090 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4115 */ "ld1rh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4140 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4165 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4191 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4217 */ "ld1roh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4243 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4269 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4295 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4321 */ "ld1rqh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4347 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4373 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4399 */ "ld1rsb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4425 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4451 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4477 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4503 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4529 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4554 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4579 */ "ld1r $\xFF\x02\x29, [$\x01], #1\0"
|
|
/* 4599 */ "ld1r $\xFF\x02\x2A, [$\x01], #8\0"
|
|
/* 4619 */ "ld1r $\xFF\x02\x2B, [$\x01], #8\0"
|
|
/* 4639 */ "ld1r $\xFF\x02\x2C, [$\x01], #4\0"
|
|
/* 4659 */ "ld1r $\xFF\x02\x2D, [$\x01], #2\0"
|
|
/* 4679 */ "ld1r $\xFF\x02\x2E, [$\x01], #4\0"
|
|
/* 4699 */ "ld1r $\xFF\x02\x2F, [$\x01], #1\0"
|
|
/* 4719 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0"
|
|
/* 4739 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4764 */ "ld1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4789 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4814 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4839 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4864 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 4889 */ "ld1 $\xFF\x02\x29, [$\x01], #48\0"
|
|
/* 4909 */ "ld1 $\xFF\x02\x2A, [$\x01], #24\0"
|
|
/* 4929 */ "ld1 $\xFF\x02\x2B, [$\x01], #48\0"
|
|
/* 4949 */ "ld1 $\xFF\x02\x2C, [$\x01], #24\0"
|
|
/* 4969 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 4989 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 5009 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 5029 */ "ld1 $\xFF\x02\x30, [$\x01], #48\0"
|
|
/* 5049 */ "ld1 $\xFF\x02\x29, [$\x01], #32\0"
|
|
/* 5069 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0"
|
|
/* 5089 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0"
|
|
/* 5109 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 5129 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 5149 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 5169 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 5189 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 5209 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5233 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5257 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5293 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5329 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5365 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5401 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5437 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5473 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5509 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5545 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5581 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0"
|
|
/* 5617 */ "ld1 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #2\0"
|
|
/* 5640 */ "ld1 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 5663 */ "ld1 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 5686 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #1\0"
|
|
/* 5709 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5733 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5757 */ "ld2h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 5781 */ "ld2r $\xFF\x02\x29, [$\x01], #2\0"
|
|
/* 5801 */ "ld2r $\xFF\x02\x2A, [$\x01], #16\0"
|
|
/* 5822 */ "ld2r $\xFF\x02\x2B, [$\x01], #16\0"
|
|
/* 5843 */ "ld2r $\xFF\x02\x2C, [$\x01], #8\0"
|
|
/* 5863 */ "ld2r $\xFF\x02\x2D, [$\x01], #4\0"
|
|
/* 5883 */ "ld2r $\xFF\x02\x2E, [$\x01], #8\0"
|
|
/* 5903 */ "ld2r $\xFF\x02\x2F, [$\x01], #2\0"
|
|
/* 5923 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0"
|
|
/* 5943 */ "ld2 $\xFF\x02\x29, [$\x01], #32\0"
|
|
/* 5963 */ "ld2 $\xFF\x02\x2B, [$\x01], #32\0"
|
|
/* 5983 */ "ld2 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 6003 */ "ld2 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 6023 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 6043 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 6063 */ "ld2 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 6083 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6107 */ "ld2 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 6130 */ "ld2 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 6153 */ "ld2 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #16\0"
|
|
/* 6177 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0"
|
|
/* 6200 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6224 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6248 */ "ld3h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6272 */ "ld3r $\xFF\x02\x29, [$\x01], #3\0"
|
|
/* 6292 */ "ld3r $\xFF\x02\x2A, [$\x01], #24\0"
|
|
/* 6313 */ "ld3r $\xFF\x02\x2B, [$\x01], #24\0"
|
|
/* 6334 */ "ld3r $\xFF\x02\x2C, [$\x01], #12\0"
|
|
/* 6355 */ "ld3r $\xFF\x02\x2D, [$\x01], #6\0"
|
|
/* 6375 */ "ld3r $\xFF\x02\x2E, [$\x01], #12\0"
|
|
/* 6396 */ "ld3r $\xFF\x02\x2F, [$\x01], #3\0"
|
|
/* 6416 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0"
|
|
/* 6436 */ "ld3 $\xFF\x02\x29, [$\x01], #48\0"
|
|
/* 6456 */ "ld3 $\xFF\x02\x2B, [$\x01], #48\0"
|
|
/* 6476 */ "ld3 $\xFF\x02\x2C, [$\x01], #24\0"
|
|
/* 6496 */ "ld3 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 6516 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 6536 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 6556 */ "ld3 $\xFF\x02\x30, [$\x01], #48\0"
|
|
/* 6576 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6600 */ "ld3 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #6\0"
|
|
/* 6623 */ "ld3 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #12\0"
|
|
/* 6647 */ "ld3 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #24\0"
|
|
/* 6671 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #3\0"
|
|
/* 6694 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6718 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6742 */ "ld4 $\xFF\x02\x29, [$\x01], #64\0"
|
|
/* 6762 */ "ld4 $\xFF\x02\x2B, [$\x01], #64\0"
|
|
/* 6782 */ "ld4 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 6802 */ "ld4 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 6822 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 6842 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 6862 */ "ld4 $\xFF\x02\x30, [$\x01], #64\0"
|
|
/* 6882 */ "ld4h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 6906 */ "ld4r $\xFF\x02\x29, [$\x01], #4\0"
|
|
/* 6926 */ "ld4r $\xFF\x02\x2A, [$\x01], #32\0"
|
|
/* 6947 */ "ld4r $\xFF\x02\x2B, [$\x01], #32\0"
|
|
/* 6968 */ "ld4r $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 6989 */ "ld4r $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 7009 */ "ld4r $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 7030 */ "ld4r $\xFF\x02\x2F, [$\x01], #4\0"
|
|
/* 7050 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0"
|
|
/* 7070 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7094 */ "ld4 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #8\0"
|
|
/* 7117 */ "ld4 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #16\0"
|
|
/* 7141 */ "ld4 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #32\0"
|
|
/* 7165 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0"
|
|
/* 7188 */ "staddb $\x02, [$\x03]\0"
|
|
/* 7204 */ "staddh $\x02, [$\x03]\0"
|
|
/* 7220 */ "staddlb $\x02, [$\x03]\0"
|
|
/* 7237 */ "staddlh $\x02, [$\x03]\0"
|
|
/* 7254 */ "staddl $\x02, [$\x03]\0"
|
|
/* 7270 */ "stadd $\x02, [$\x03]\0"
|
|
/* 7285 */ "ldapurb $\x01, [$\x02]\0"
|
|
/* 7302 */ "ldapurh $\x01, [$\x02]\0"
|
|
/* 7319 */ "ldapursb $\x01, [$\x02]\0"
|
|
/* 7337 */ "ldapursh $\x01, [$\x02]\0"
|
|
/* 7355 */ "ldapursw $\x01, [$\x02]\0"
|
|
/* 7373 */ "ldapur $\x01, [$\x02]\0"
|
|
/* 7389 */ "stclrb $\x02, [$\x03]\0"
|
|
/* 7405 */ "stclrh $\x02, [$\x03]\0"
|
|
/* 7421 */ "stclrlb $\x02, [$\x03]\0"
|
|
/* 7438 */ "stclrlh $\x02, [$\x03]\0"
|
|
/* 7455 */ "stclrl $\x02, [$\x03]\0"
|
|
/* 7471 */ "stclr $\x02, [$\x03]\0"
|
|
/* 7486 */ "steorb $\x02, [$\x03]\0"
|
|
/* 7502 */ "steorh $\x02, [$\x03]\0"
|
|
/* 7518 */ "steorlb $\x02, [$\x03]\0"
|
|
/* 7535 */ "steorlh $\x02, [$\x03]\0"
|
|
/* 7552 */ "steorl $\x02, [$\x03]\0"
|
|
/* 7568 */ "steor $\x02, [$\x03]\0"
|
|
/* 7583 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7609 */ "ldff1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7635 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7661 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7687 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7713 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7739 */ "ldff1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7765 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7791 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7818 */ "ldff1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7845 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7872 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7899 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7926 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7953 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 7979 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8005 */ "ldg $\x01, [$\x03]\0"
|
|
/* 8018 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8044 */ "ldnf1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8070 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8096 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8122 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8148 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8174 */ "ldnf1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8200 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8226 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8253 */ "ldnf1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8280 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8307 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8334 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8361 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8388 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8414 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8440 */ "ldnp $\x01, $\x02, [$\x03]\0"
|
|
/* 8458 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8484 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8512 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 8540 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8566 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8594 */ "ldnt1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8620 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8648 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 8676 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8705 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 8734 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8763 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 8792 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8821 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
|
|
/* 8847 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
|
|
/* 8875 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
|
|
/* 8903 */ "ldp $\x01, $\x02, [$\x03]\0"
|
|
/* 8920 */ "ldpsw $\x01, $\x02, [$\x03]\0"
|
|
/* 8939 */ "ldraa $\x01, [$\x02]\0"
|
|
/* 8954 */ "ldrab $\x01, [$\x02]\0"
|
|
/* 8969 */ "ldrb $\x01, [$\x02, $\x03]\0"
|
|
/* 8987 */ "ldrb $\x01, [$\x02]\0"
|
|
/* 9001 */ "ldr $\x01, [$\x02, $\x03]\0"
|
|
/* 9018 */ "ldr $\x01, [$\x02]\0"
|
|
/* 9031 */ "ldrh $\x01, [$\x02, $\x03]\0"
|
|
/* 9049 */ "ldrh $\x01, [$\x02]\0"
|
|
/* 9063 */ "ldrsb $\x01, [$\x02, $\x03]\0"
|
|
/* 9082 */ "ldrsb $\x01, [$\x02]\0"
|
|
/* 9097 */ "ldrsh $\x01, [$\x02, $\x03]\0"
|
|
/* 9116 */ "ldrsh $\x01, [$\x02]\0"
|
|
/* 9131 */ "ldrsw $\x01, [$\x02, $\x03]\0"
|
|
/* 9150 */ "ldrsw $\x01, [$\x02]\0"
|
|
/* 9165 */ "ldr $\xFF\x01\x07, [$\x02]\0"
|
|
/* 9180 */ "ldr $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0"
|
|
/* 9205 */ "stsetb $\x02, [$\x03]\0"
|
|
/* 9221 */ "stseth $\x02, [$\x03]\0"
|
|
/* 9237 */ "stsetlb $\x02, [$\x03]\0"
|
|
/* 9254 */ "stsetlh $\x02, [$\x03]\0"
|
|
/* 9271 */ "stsetl $\x02, [$\x03]\0"
|
|
/* 9287 */ "stset $\x02, [$\x03]\0"
|
|
/* 9302 */ "stsmaxb $\x02, [$\x03]\0"
|
|
/* 9319 */ "stsmaxh $\x02, [$\x03]\0"
|
|
/* 9336 */ "stsmaxlb $\x02, [$\x03]\0"
|
|
/* 9354 */ "stsmaxlh $\x02, [$\x03]\0"
|
|
/* 9372 */ "stsmaxl $\x02, [$\x03]\0"
|
|
/* 9389 */ "stsmax $\x02, [$\x03]\0"
|
|
/* 9405 */ "stsminb $\x02, [$\x03]\0"
|
|
/* 9422 */ "stsminh $\x02, [$\x03]\0"
|
|
/* 9439 */ "stsminlb $\x02, [$\x03]\0"
|
|
/* 9457 */ "stsminlh $\x02, [$\x03]\0"
|
|
/* 9475 */ "stsminl $\x02, [$\x03]\0"
|
|
/* 9492 */ "stsmin $\x02, [$\x03]\0"
|
|
/* 9508 */ "ldtrb $\x01, [$\x02]\0"
|
|
/* 9523 */ "ldtrh $\x01, [$\x02]\0"
|
|
/* 9538 */ "ldtrsb $\x01, [$\x02]\0"
|
|
/* 9554 */ "ldtrsh $\x01, [$\x02]\0"
|
|
/* 9570 */ "ldtrsw $\x01, [$\x02]\0"
|
|
/* 9586 */ "ldtr $\x01, [$\x02]\0"
|
|
/* 9600 */ "stumaxb $\x02, [$\x03]\0"
|
|
/* 9617 */ "stumaxh $\x02, [$\x03]\0"
|
|
/* 9634 */ "stumaxlb $\x02, [$\x03]\0"
|
|
/* 9652 */ "stumaxlh $\x02, [$\x03]\0"
|
|
/* 9670 */ "stumaxl $\x02, [$\x03]\0"
|
|
/* 9687 */ "stumax $\x02, [$\x03]\0"
|
|
/* 9703 */ "stuminb $\x02, [$\x03]\0"
|
|
/* 9720 */ "stuminh $\x02, [$\x03]\0"
|
|
/* 9737 */ "stuminlb $\x02, [$\x03]\0"
|
|
/* 9755 */ "stuminlh $\x02, [$\x03]\0"
|
|
/* 9773 */ "stuminl $\x02, [$\x03]\0"
|
|
/* 9790 */ "stumin $\x02, [$\x03]\0"
|
|
/* 9806 */ "ldurb $\x01, [$\x02]\0"
|
|
/* 9821 */ "ldur $\x01, [$\x02]\0"
|
|
/* 9835 */ "ldurh $\x01, [$\x02]\0"
|
|
/* 9850 */ "ldursb $\x01, [$\x02]\0"
|
|
/* 9866 */ "ldursh $\x01, [$\x02]\0"
|
|
/* 9882 */ "ldursw $\x01, [$\x02]\0"
|
|
/* 9898 */ "mul $\x01, $\x02, $\x03\0"
|
|
/* 9913 */ "smstart\0"
|
|
/* 9921 */ "smstart sm\0"
|
|
/* 9932 */ "smstart za\0"
|
|
/* 9943 */ "smstop\0"
|
|
/* 9950 */ "smstop sm\0"
|
|
/* 9960 */ "smstop za\0"
|
|
/* 9970 */ "mneg $\x01, $\x02, $\x03\0"
|
|
/* 9986 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
|
|
/* 10009 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
|
|
/* 10030 */ "mvn $\x01, $\x03\0"
|
|
/* 10041 */ "mvn $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 10056 */ "orn $\x01, $\x02, $\x03\0"
|
|
/* 10071 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0"
|
|
/* 10087 */ "mov $\x01, $\x03\0"
|
|
/* 10098 */ "orr $\x01, $\x02, $\x03\0"
|
|
/* 10113 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0"
|
|
/* 10128 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
|
|
/* 10149 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
|
|
/* 10170 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
|
|
/* 10191 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0"
|
|
/* 10206 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0"
|
|
/* 10229 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0"
|
|
/* 10250 */ "pacia1716\0"
|
|
/* 10260 */ "paciasp\0"
|
|
/* 10268 */ "paciaz\0"
|
|
/* 10275 */ "pacib1716\0"
|
|
/* 10285 */ "pacibsp\0"
|
|
/* 10293 */ "pacibz\0"
|
|
/* 10300 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 10324 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 10346 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 10370 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 10394 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 10416 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 10440 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 10464 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 10486 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 10510 */ "prfm $\xFF\x01\x38, [$\x02, $\x03]\0"
|
|
/* 10530 */ "prfm $\xFF\x01\x38, [$\x02]\0"
|
|
/* 10546 */ "prfum $\xFF\x01\x38, [$\x02]\0"
|
|
/* 10563 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 10587 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 10609 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 10633 */ "ptrues $\xFF\x01\x06\0"
|
|
/* 10645 */ "ptrues $\xFF\x01\x10\0"
|
|
/* 10657 */ "ptrues $\xFF\x01\x09\0"
|
|
/* 10669 */ "ptrues $\xFF\x01\x0B\0"
|
|
/* 10681 */ "ptrue $\xFF\x01\x06\0"
|
|
/* 10692 */ "ptrue $\xFF\x01\x10\0"
|
|
/* 10703 */ "ptrue $\xFF\x01\x09\0"
|
|
/* 10714 */ "ptrue $\xFF\x01\x0B\0"
|
|
/* 10725 */ "ret\0"
|
|
/* 10729 */ "ngcs $\x01, $\x03\0"
|
|
/* 10741 */ "ngc $\x01, $\x03\0"
|
|
/* 10752 */ "asr $\x01, $\x02, $\x03\0"
|
|
/* 10767 */ "sxtb $\x01, $\x02\0"
|
|
/* 10779 */ "sxth $\x01, $\x02\0"
|
|
/* 10791 */ "sxtw $\x01, $\x02\0"
|
|
/* 10803 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0"
|
|
/* 10826 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0"
|
|
/* 10849 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0"
|
|
/* 10872 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0"
|
|
/* 10895 */ "smull $\x01, $\x02, $\x03\0"
|
|
/* 10912 */ "smnegl $\x01, $\x02, $\x03\0"
|
|
/* 10930 */ "sqdecb $\x01\0"
|
|
/* 10940 */ "sqdecb $\x01, $\xFF\x03\x0E\0"
|
|
/* 10956 */ "sqdecb $\x01, $\xFF\x02\x39\0"
|
|
/* 10972 */ "sqdecb $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 10994 */ "sqdecd $\x01\0"
|
|
/* 11004 */ "sqdecd $\x01, $\xFF\x03\x0E\0"
|
|
/* 11020 */ "sqdecd $\x01, $\xFF\x02\x39\0"
|
|
/* 11036 */ "sqdecd $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11058 */ "sqdecd $\xFF\x01\x10\0"
|
|
/* 11070 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 11088 */ "sqdech $\x01\0"
|
|
/* 11098 */ "sqdech $\x01, $\xFF\x03\x0E\0"
|
|
/* 11114 */ "sqdech $\x01, $\xFF\x02\x39\0"
|
|
/* 11130 */ "sqdech $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11152 */ "sqdech $\xFF\x01\x09\0"
|
|
/* 11164 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 11182 */ "sqdecw $\x01\0"
|
|
/* 11192 */ "sqdecw $\x01, $\xFF\x03\x0E\0"
|
|
/* 11208 */ "sqdecw $\x01, $\xFF\x02\x39\0"
|
|
/* 11224 */ "sqdecw $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11246 */ "sqdecw $\xFF\x01\x0B\0"
|
|
/* 11258 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 11276 */ "sqincb $\x01\0"
|
|
/* 11286 */ "sqincb $\x01, $\xFF\x03\x0E\0"
|
|
/* 11302 */ "sqincb $\x01, $\xFF\x02\x39\0"
|
|
/* 11318 */ "sqincb $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11340 */ "sqincd $\x01\0"
|
|
/* 11350 */ "sqincd $\x01, $\xFF\x03\x0E\0"
|
|
/* 11366 */ "sqincd $\x01, $\xFF\x02\x39\0"
|
|
/* 11382 */ "sqincd $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11404 */ "sqincd $\xFF\x01\x10\0"
|
|
/* 11416 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 11434 */ "sqinch $\x01\0"
|
|
/* 11444 */ "sqinch $\x01, $\xFF\x03\x0E\0"
|
|
/* 11460 */ "sqinch $\x01, $\xFF\x02\x39\0"
|
|
/* 11476 */ "sqinch $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11498 */ "sqinch $\xFF\x01\x09\0"
|
|
/* 11510 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 11528 */ "sqincw $\x01\0"
|
|
/* 11538 */ "sqincw $\x01, $\xFF\x03\x0E\0"
|
|
/* 11554 */ "sqincw $\x01, $\xFF\x02\x39\0"
|
|
/* 11570 */ "sqincw $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0"
|
|
/* 11592 */ "sqincw $\xFF\x01\x0B\0"
|
|
/* 11604 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 11622 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 11646 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 11670 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 11694 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 11718 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 11742 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 11766 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 11790 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 11812 */ "st1b $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 11834 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 11856 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 11878 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 11900 */ "st1 $\xFF\x02\x29, [$\x01], #64\0"
|
|
/* 11920 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0"
|
|
/* 11940 */ "st1 $\xFF\x02\x2B, [$\x01], #64\0"
|
|
/* 11960 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 11980 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 12000 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 12020 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 12040 */ "st1 $\xFF\x02\x30, [$\x01], #64\0"
|
|
/* 12060 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12082 */ "st1h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12104 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12126 */ "st1 $\xFF\x02\x29, [$\x01], #16\0"
|
|
/* 12146 */ "st1 $\xFF\x02\x2A, [$\x01], #8\0"
|
|
/* 12165 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0"
|
|
/* 12185 */ "st1 $\xFF\x02\x2C, [$\x01], #8\0"
|
|
/* 12204 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0"
|
|
/* 12223 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0"
|
|
/* 12243 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0"
|
|
/* 12262 */ "st1 $\xFF\x02\x30, [$\x01], #16\0"
|
|
/* 12282 */ "st1 $\xFF\x02\x29, [$\x01], #48\0"
|
|
/* 12302 */ "st1 $\xFF\x02\x2A, [$\x01], #24\0"
|
|
/* 12322 */ "st1 $\xFF\x02\x2B, [$\x01], #48\0"
|
|
/* 12342 */ "st1 $\xFF\x02\x2C, [$\x01], #24\0"
|
|
/* 12362 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 12382 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 12402 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 12422 */ "st1 $\xFF\x02\x30, [$\x01], #48\0"
|
|
/* 12442 */ "st1 $\xFF\x02\x29, [$\x01], #32\0"
|
|
/* 12462 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0"
|
|
/* 12482 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0"
|
|
/* 12502 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 12522 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 12542 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 12562 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 12582 */ "st1 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 12602 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12624 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 12646 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12680 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12714 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12748 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12782 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12816 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12850 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12884 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12918 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12952 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0"
|
|
/* 12986 */ "st1 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #2\0"
|
|
/* 13009 */ "st1 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 13032 */ "st1 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 13055 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #1\0"
|
|
/* 13078 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13100 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13122 */ "st2g $\x01, [$\x02]\0"
|
|
/* 13136 */ "st2h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13158 */ "st2 $\xFF\x02\x29, [$\x01], #32\0"
|
|
/* 13178 */ "st2 $\xFF\x02\x2B, [$\x01], #32\0"
|
|
/* 13198 */ "st2 $\xFF\x02\x2C, [$\x01], #16\0"
|
|
/* 13218 */ "st2 $\xFF\x02\x2D, [$\x01], #16\0"
|
|
/* 13238 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0"
|
|
/* 13258 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0"
|
|
/* 13278 */ "st2 $\xFF\x02\x30, [$\x01], #32\0"
|
|
/* 13298 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13320 */ "st2 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 13343 */ "st2 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 13366 */ "st2 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #16\0"
|
|
/* 13390 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0"
|
|
/* 13413 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13435 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13457 */ "st3h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13479 */ "st3 $\xFF\x02\x29, [$\x01], #48\0"
|
|
/* 13499 */ "st3 $\xFF\x02\x2B, [$\x01], #48\0"
|
|
/* 13519 */ "st3 $\xFF\x02\x2C, [$\x01], #24\0"
|
|
/* 13539 */ "st3 $\xFF\x02\x2D, [$\x01], #24\0"
|
|
/* 13559 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0"
|
|
/* 13579 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0"
|
|
/* 13599 */ "st3 $\xFF\x02\x30, [$\x01], #48\0"
|
|
/* 13619 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13641 */ "st3 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #6\0"
|
|
/* 13664 */ "st3 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #12\0"
|
|
/* 13688 */ "st3 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #24\0"
|
|
/* 13712 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #3\0"
|
|
/* 13735 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13757 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13779 */ "st4 $\xFF\x02\x29, [$\x01], #64\0"
|
|
/* 13799 */ "st4 $\xFF\x02\x2B, [$\x01], #64\0"
|
|
/* 13819 */ "st4 $\xFF\x02\x2C, [$\x01], #32\0"
|
|
/* 13839 */ "st4 $\xFF\x02\x2D, [$\x01], #32\0"
|
|
/* 13859 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0"
|
|
/* 13879 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0"
|
|
/* 13899 */ "st4 $\xFF\x02\x30, [$\x01], #64\0"
|
|
/* 13919 */ "st4h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13941 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 13963 */ "st4 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #8\0"
|
|
/* 13986 */ "st4 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #16\0"
|
|
/* 14010 */ "st4 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #32\0"
|
|
/* 14034 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0"
|
|
/* 14057 */ "stg $\x01, [$\x02]\0"
|
|
/* 14070 */ "stgp $\x01, $\x02, [$\x03]\0"
|
|
/* 14088 */ "stlurb $\x01, [$\x02]\0"
|
|
/* 14104 */ "stlurh $\x01, [$\x02]\0"
|
|
/* 14120 */ "stlur $\x01, [$\x02]\0"
|
|
/* 14135 */ "stnp $\x01, $\x02, [$\x03]\0"
|
|
/* 14153 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14177 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 14203 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 14229 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14253 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 14279 */ "stnt1h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14303 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 14329 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 14355 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
|
|
/* 14379 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
|
|
/* 14405 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
|
|
/* 14431 */ "stp $\x01, $\x02, [$\x03]\0"
|
|
/* 14448 */ "strb $\x01, [$\x02, $\x03]\0"
|
|
/* 14466 */ "strb $\x01, [$\x02]\0"
|
|
/* 14480 */ "str $\x01, [$\x02, $\x03]\0"
|
|
/* 14497 */ "str $\x01, [$\x02]\0"
|
|
/* 14510 */ "strh $\x01, [$\x02, $\x03]\0"
|
|
/* 14528 */ "strh $\x01, [$\x02]\0"
|
|
/* 14542 */ "str $\xFF\x01\x07, [$\x02]\0"
|
|
/* 14557 */ "str $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0"
|
|
/* 14582 */ "sttrb $\x01, [$\x02]\0"
|
|
/* 14597 */ "sttrh $\x01, [$\x02]\0"
|
|
/* 14612 */ "sttr $\x01, [$\x02]\0"
|
|
/* 14626 */ "sturb $\x01, [$\x02]\0"
|
|
/* 14641 */ "stur $\x01, [$\x02]\0"
|
|
/* 14655 */ "sturh $\x01, [$\x02]\0"
|
|
/* 14670 */ "stz2g $\x01, [$\x02]\0"
|
|
/* 14685 */ "stzg $\x01, [$\x02]\0"
|
|
/* 14699 */ "cmp $\x02, $\xFF\x03\x01\0"
|
|
/* 14712 */ "cmp $\x02, $\x03\0"
|
|
/* 14723 */ "cmp $\x02, $\x03$\xFF\x04\x02\0"
|
|
/* 14738 */ "negs $\x01, $\x03\0"
|
|
/* 14750 */ "negs $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 14766 */ "subs $\x01, $\x02, $\x03\0"
|
|
/* 14782 */ "cmp $\x02, $\x03$\xFF\x04\x03\0"
|
|
/* 14797 */ "neg $\x01, $\x03\0"
|
|
/* 14808 */ "neg $\x01, $\x03$\xFF\x04\x02\0"
|
|
/* 14823 */ "sub $\x01, $\x02, $\x03\0"
|
|
/* 14838 */ "sys $\x01, $\xFF\x02\x3A, $\xFF\x03\x3A, $\x04\0"
|
|
/* 14861 */ "lsr $\x01, $\x02, $\x03\0"
|
|
/* 14876 */ "uxtb $\x01, $\x02\0"
|
|
/* 14888 */ "uxth $\x01, $\x02\0"
|
|
/* 14900 */ "uxtw $\x01, $\x02\0"
|
|
/* 14912 */ "umull $\x01, $\x02, $\x03\0"
|
|
/* 14929 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0"
|
|
/* 14948 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0"
|
|
/* 14967 */ "umnegl $\x01, $\x02, $\x03\0"
|
|
/* 14985 */ "uqdecb $\x01\0"
|
|
/* 14995 */ "uqdecb $\x01, $\xFF\x03\x0E\0"
|
|
/* 15011 */ "uqdecd $\x01\0"
|
|
/* 15021 */ "uqdecd $\x01, $\xFF\x03\x0E\0"
|
|
/* 15037 */ "uqdecd $\xFF\x01\x10\0"
|
|
/* 15049 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 15067 */ "uqdech $\x01\0"
|
|
/* 15077 */ "uqdech $\x01, $\xFF\x03\x0E\0"
|
|
/* 15093 */ "uqdech $\xFF\x01\x09\0"
|
|
/* 15105 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 15123 */ "uqdecw $\x01\0"
|
|
/* 15133 */ "uqdecw $\x01, $\xFF\x03\x0E\0"
|
|
/* 15149 */ "uqdecw $\xFF\x01\x0B\0"
|
|
/* 15161 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 15179 */ "uqincb $\x01\0"
|
|
/* 15189 */ "uqincb $\x01, $\xFF\x03\x0E\0"
|
|
/* 15205 */ "uqincd $\x01\0"
|
|
/* 15215 */ "uqincd $\x01, $\xFF\x03\x0E\0"
|
|
/* 15231 */ "uqincd $\xFF\x01\x10\0"
|
|
/* 15243 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
|
|
/* 15261 */ "uqinch $\x01\0"
|
|
/* 15271 */ "uqinch $\x01, $\xFF\x03\x0E\0"
|
|
/* 15287 */ "uqinch $\xFF\x01\x09\0"
|
|
/* 15299 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
|
|
/* 15317 */ "uqincw $\x01\0"
|
|
/* 15327 */ "uqincw $\x01, $\xFF\x03\x0E\0"
|
|
/* 15343 */ "uqincw $\xFF\x01\x0B\0"
|
|
/* 15355 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
|
|
/* 15373 */ "xpaclri\0"
|
|
/* 15381 */ "zero {za}\0"
|
|
/* 15391 */ "zero {za0.h}\0"
|
|
/* 15404 */ "zero {za1.h}\0"
|
|
/* 15417 */ "zero {za0.s}\0"
|
|
/* 15430 */ "zero {za1.s}\0"
|
|
/* 15443 */ "zero {za2.s}\0"
|
|
/* 15456 */ "zero {za3.s}\0"
|
|
/* 15469 */ "zero {za0.s,za1.s}\0"
|
|
/* 15488 */ "zero {za0.s,za3.s}\0"
|
|
/* 15507 */ "zero {za1.s,za2.s}\0"
|
|
/* 15526 */ "zero {za2.s,za3.s}\0"
|
|
/* 15545 */ "zero {za0.s,za1.s,za2.s}\0"
|
|
/* 15570 */ "zero {za0.s,za1.s,za3.s}\0"
|
|
/* 15595 */ "zero {za0.s,za2.s,za3.s}\0"
|
|
/* 15620 */ "zero {za1.s,za2.s,za3.s}\0"
|
|
;
|
|
|
|
|
|
char *AsmString;
|
|
const size_t OpToSize = sizeof(OpToPatterns) / sizeof(PatternsForOpcode);
|
|
|
|
const unsigned opcode = MCInst_getOpcode(MI);
|
|
|
|
// Check for alias
|
|
int OpToIndex = 0;
|
|
for(int i = 0; i < OpToSize; i++){
|
|
if(OpToPatterns[i].Opcode == opcode){
|
|
OpToIndex = i;
|
|
break;
|
|
}
|
|
}
|
|
// Chech for match
|
|
if(opcode != OpToPatterns[OpToIndex].Opcode)
|
|
return NULL;
|
|
|
|
const PatternsForOpcode opToPat = OpToPatterns[OpToIndex];
|
|
|
|
// Try all patterns for this opcode
|
|
uint32_t AsmStrOffset = ~0U;
|
|
int patIdx = opToPat.PatternStart;
|
|
while(patIdx < (opToPat.PatternStart + opToPat.NumPatterns)){
|
|
// Check operand count first
|
|
if(MCInst_getNumOperands(MI) != Patterns[patIdx].NumOperands)
|
|
return NULL;
|
|
|
|
// Test all conditions for this pattern
|
|
int condIdx = Patterns[patIdx].AliasCondStart;
|
|
int opIdx = 0;
|
|
bool allPass = true;
|
|
while(condIdx < (Patterns[patIdx].AliasCondStart + Patterns[patIdx].NumConds)){
|
|
MCOperand *opnd = MCInst_getOperand(MI, opIdx);
|
|
opIdx++;
|
|
// Not concerned with any Feature related conditions as STI is disregarded
|
|
switch (Conds[condIdx].Kind)
|
|
{
|
|
case AliasPatternCond_K_Ignore :
|
|
// Operand can be anything.
|
|
break;
|
|
case AliasPatternCond_K_Reg :
|
|
// Operand must be a specific register.
|
|
allPass = allPass && (MCOperand_isReg(opnd) && MCOperand_getReg(opnd) == Conds[condIdx].Value);
|
|
break;
|
|
case AliasPatternCond_K_TiedReg :
|
|
// Operand must match the register of another operand.
|
|
allPass = allPass && (MCOperand_isReg(opnd) && MCOperand_getReg(opnd) ==
|
|
MCOperand_getReg(MCInst_getOperand(MI, Conds[condIdx].Value)));
|
|
break;
|
|
case AliasPatternCond_K_Imm :
|
|
// Operand must be a specific immediate.
|
|
allPass = allPass && (MCOperand_isImm(opnd) && MCOperand_getImm(opnd) == Conds[condIdx].Value);
|
|
break;
|
|
case AliasPatternCond_K_RegClass :
|
|
// Operand must be a register in this class. Value is a register class id.
|
|
allPass = allPass && (MCOperand_isReg(opnd) && GETREGCLASS_CONTAIN(Conds[condIdx].Value, (opIdx-1)));
|
|
break;
|
|
case AliasPatternCond_K_Custom :
|
|
// Operand must match some custom criteria.
|
|
allPass = allPass && AArch64InstPrinterValidateMCOperand(opnd, Conds[condIdx].Value);
|
|
break;
|
|
case AliasPatternCond_K_Feature :
|
|
case AliasPatternCond_K_NegFeature :
|
|
case AliasPatternCond_K_OrFeature :
|
|
case AliasPatternCond_K_OrNegFeature :
|
|
case AliasPatternCond_K_EndOrFeatures :
|
|
default :
|
|
break;
|
|
}
|
|
condIdx++;
|
|
}
|
|
if(allPass){
|
|
AsmStrOffset = Patterns[patIdx].AsmStrOffset;
|
|
break;
|
|
}
|
|
patIdx++;
|
|
}
|
|
|
|
// If no alias matched, don't print an alias.
|
|
if (AsmStrOffset == ~0U)
|
|
return NULL;
|
|
|
|
AsmString = cs_strdup(&AsmStrings[AsmStrOffset]);
|
|
|
|
tmpString = cs_strdup(AsmString);
|
|
|
|
while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
|
|
AsmString[I] != '$' && AsmString[I] != '\0')
|
|
++I;
|
|
|
|
tmpString[I] = 0;
|
|
SStream_concat0(OS, tmpString);
|
|
|
|
if (AsmString[I] != '\0') {
|
|
if (AsmString[I] == ' ' || AsmString[I] == '\t') {
|
|
SStream_concat0(OS, " ");
|
|
++I;
|
|
}
|
|
|
|
bool isSME = false;
|
|
do {
|
|
if (AsmString[I] == '$') {
|
|
++I;
|
|
if (AsmString[I] == (char)0xff) {
|
|
++I;
|
|
OpIdx = AsmString[I++] - 1;
|
|
PrintMethodIdx = AsmString[I++] - 1;
|
|
printCustomAliasOperand(MI, 0, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
|
|
} else {
|
|
if (AsmString[I] == '[') {
|
|
if (AsmString[I-1] != ' '){
|
|
set_sme_index(MI, true);
|
|
isSME = true;
|
|
} else {
|
|
set_mem_access(MI, true);
|
|
}
|
|
} else if (AsmString[I] == ']') {
|
|
if (isSME) {
|
|
set_sme_index(MI, false);
|
|
isSME = false;
|
|
} else {
|
|
set_mem_access(MI, false);
|
|
}
|
|
}
|
|
SStream_concat1(OS, AsmString[I++]);
|
|
}
|
|
} while (AsmString[I] != '\0');
|
|
}
|
|
cs_mem_free(AsmString);
|
|
return tmpString;
|
|
}
|
|
|
|
static void printCustomAliasOperand(
|
|
MCInst *MI, uint64_t Address, unsigned OpIdx,
|
|
unsigned PrintMethodIdx,
|
|
SStream *OS)
|
|
{
|
|
switch (PrintMethodIdx) {
|
|
default:
|
|
break;
|
|
case 0:
|
|
printAddSubImm(MI, OpIdx, OS);
|
|
break;
|
|
case 1:
|
|
printShifter(MI, OpIdx, OS);
|
|
break;
|
|
case 2:
|
|
printArithExtend(MI, OpIdx, OS);
|
|
break;
|
|
case 3:
|
|
printLogicalImm32(MI, OpIdx, OS);
|
|
break;
|
|
case 4:
|
|
printLogicalImm64(MI, OpIdx, OS);
|
|
break;
|
|
case 5:
|
|
printSVERegOp(MI, OpIdx, OS, 'b');
|
|
break;
|
|
case 6:
|
|
printSVERegOp(MI, OpIdx, OS, 0);
|
|
break;
|
|
case 7:
|
|
printLogicalImm32(MI, OpIdx, OS);
|
|
break;
|
|
case 8:
|
|
printSVERegOp(MI, OpIdx, OS, 'h');
|
|
break;
|
|
case 9:
|
|
printLogicalImm32(MI, OpIdx, OS);
|
|
break;
|
|
case 10:
|
|
printSVERegOp(MI, OpIdx, OS, 's');
|
|
break;
|
|
case 11:
|
|
printVRegOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 12:
|
|
printImm(MI, OpIdx, OS);
|
|
break;
|
|
case 13:
|
|
printSVEPattern(MI, OpIdx, OS);
|
|
break;
|
|
case 14:
|
|
printImm8OptLsl32(MI, OpIdx, OS);
|
|
break;
|
|
case 15:
|
|
printSVERegOp(MI, OpIdx, OS, 'd');
|
|
break;
|
|
case 16:
|
|
printImm8OptLsl64(MI, OpIdx, OS);
|
|
break;
|
|
case 17:
|
|
printImm8OptLsl32(MI, OpIdx, OS);
|
|
break;
|
|
case 18:
|
|
printImm8OptLsl32(MI, OpIdx, OS);
|
|
break;
|
|
case 19:
|
|
printInverseCondCode(MI, OpIdx, OS);
|
|
break;
|
|
case 20:
|
|
printSVELogicalImm16(MI, OpIdx, OS);
|
|
break;
|
|
case 21:
|
|
printSVELogicalImm32(MI, OpIdx, OS);
|
|
break;
|
|
case 22:
|
|
printSVELogicalImm64(MI, OpIdx, OS);
|
|
break;
|
|
case 23:
|
|
printZPRasFPR(MI, OpIdx, OS, 8);
|
|
break;
|
|
case 24:
|
|
printVectorIndex(MI, OpIdx, OS);
|
|
break;
|
|
case 25:
|
|
printZPRasFPR(MI, OpIdx, OS, 64);
|
|
break;
|
|
case 26:
|
|
printZPRasFPR(MI, OpIdx, OS, 16);
|
|
break;
|
|
case 27:
|
|
printSVERegOp(MI, OpIdx, OS, 'q');
|
|
break;
|
|
case 28:
|
|
printZPRasFPR(MI, OpIdx, OS, 128);
|
|
break;
|
|
case 29:
|
|
printZPRasFPR(MI, OpIdx, OS, 32);
|
|
break;
|
|
case 30:
|
|
printMatrixTileVector(MI, OpIdx, OS, 0);
|
|
break;
|
|
case 31:
|
|
printMatrixIndex(MI, OpIdx, OS);
|
|
break;
|
|
case 32:
|
|
printMatrixTileVector(MI, OpIdx, OS, 1);
|
|
break;
|
|
case 33:
|
|
printFPImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 34:
|
|
printTypedVectorList(MI, OpIdx, OS, 0,'d');
|
|
break;
|
|
case 35:
|
|
printTypedVectorList(MI, OpIdx, OS, 0,'s');
|
|
break;
|
|
case 36:
|
|
printBTIHintOp(MI, OpIdx, OS);
|
|
break;
|
|
case 37:
|
|
printPSBHintOp(MI, OpIdx, OS);
|
|
break;
|
|
case 38:
|
|
printTypedVectorList(MI, OpIdx, OS, 0,'h');
|
|
break;
|
|
case 39:
|
|
printTypedVectorList(MI, OpIdx, OS, 0,'b');
|
|
break;
|
|
case 40:
|
|
printTypedVectorList(MI, OpIdx, OS, 16, 'b');
|
|
break;
|
|
case 41:
|
|
printTypedVectorList(MI, OpIdx, OS, 1, 'd');
|
|
break;
|
|
case 42:
|
|
printTypedVectorList(MI, OpIdx, OS, 2, 'd');
|
|
break;
|
|
case 43:
|
|
printTypedVectorList(MI, OpIdx, OS, 2, 's');
|
|
break;
|
|
case 44:
|
|
printTypedVectorList(MI, OpIdx, OS, 4, 'h');
|
|
break;
|
|
case 45:
|
|
printTypedVectorList(MI, OpIdx, OS, 4, 's');
|
|
break;
|
|
case 46:
|
|
printTypedVectorList(MI, OpIdx, OS, 8, 'b');
|
|
break;
|
|
case 47:
|
|
printTypedVectorList(MI, OpIdx, OS, 8, 'h');
|
|
break;
|
|
case 48:
|
|
printTypedVectorList(MI, OpIdx, OS, 0, 'h');
|
|
break;
|
|
case 49:
|
|
printTypedVectorList(MI, OpIdx, OS, 0, 's');
|
|
break;
|
|
case 50:
|
|
printTypedVectorList(MI, OpIdx, OS, 0, 'd');
|
|
break;
|
|
case 51:
|
|
printTypedVectorList(MI, OpIdx, OS, 0, 'b');
|
|
break;
|
|
case 52:
|
|
printMatrix(MI, OpIdx, OS, 0);
|
|
break;
|
|
case 53:
|
|
printImmHex(MI, OpIdx, OS);
|
|
break;
|
|
case 54:
|
|
printPrefetchOp(MI, OpIdx, OS, true);
|
|
break;
|
|
case 55:
|
|
printPrefetchOp(MI, OpIdx, OS, false);
|
|
break;
|
|
case 56:
|
|
printGPR64as32(MI, OpIdx, OS);
|
|
break;
|
|
case 57:
|
|
printSysCROperand(MI, OpIdx, OS);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp,
|
|
unsigned PredicateIndex) {
|
|
int64_t Val;
|
|
switch (PredicateIndex) {
|
|
default:
|
|
return false; // never reach
|
|
break;
|
|
case 1: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements8(Val);
|
|
|
|
}
|
|
case 2: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements16(Val);
|
|
|
|
}
|
|
case 3: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements32(Val);
|
|
|
|
}
|
|
case 4: {
|
|
|
|
return MCOperand_isImm(MCOp) &&
|
|
MCOperand_getImm(MCOp) != AArch64CC_AL &&
|
|
MCOperand_getImm(MCOp) != AArch64CC_NV;
|
|
|
|
}
|
|
case 5: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements16(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 6: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements32(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 7: {
|
|
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64);
|
|
return AArch64_AM_isSVEMaskOfIdenticalElements64(Val) &&
|
|
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val);
|
|
|
|
}
|
|
case 8: {
|
|
|
|
// "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
return lookupBTIByEncoding(MCOperand_getImm(MCOp) ^ 32) != NULL;
|
|
|
|
}
|
|
case 9: {
|
|
|
|
// Check, if operand is valid, to fix exhaustive aliasing in disassembly.
|
|
// "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
|
|
if (!MCOperand_isImm(MCOp))
|
|
return false;
|
|
return lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|