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312 lines
10 KiB
C
312 lines
10 KiB
C
/*
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* Debugger ARM specific functions
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*
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* Copyright 2010-2013 André Hentschel
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "debugger.h"
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#ifdef __arm__
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#include <capstone/capstone.h>
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extern cs_opt_mem cs_mem;
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/***********************************************************************
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* disasm_one_insn
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*
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* Disassemble instruction at 'addr'. addr is changed to point to the
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* start of the next instruction.
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*/
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void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
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{
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static csh handle;
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cs_insn *insn;
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unsigned char buffer[4];
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SIZE_T count, len;
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DWORD pc = addr->Offset;
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addr->Offset &= ~1;
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if (!dbg_curr_process->process_io->read( dbg_curr_process->handle, memory_to_linear_addr(addr),
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buffer, sizeof(buffer), &len )) return;
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if (!handle)
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{
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cs_option( 0, CS_OPT_MEM, (size_t)&cs_mem );
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cs_open( CS_ARCH_ARM, 0, &handle );
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}
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cs_option( handle, CS_OPT_MODE, pc & 1 ? CS_MODE_THUMB : CS_MODE_ARM );
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cs_option( handle, CS_OPT_DETAIL, CS_OPT_ON );
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count = cs_disasm( handle, buffer, len, pc, 0, &insn );
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if (display) dbg_printf( "%s %s", insn[0].mnemonic, insn[0].op_str );
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if (insn[0].id == ARM_INS_B || insn[0].id == ARM_INS_BL)
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{
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ADDRESS64 a = { .Mode = AddrModeFlat, .Offset = insn[0].detail->arm.operands[0].imm };
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print_address_symbol( &a, TRUE, "" );
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}
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addr->Offset = pc + insn[0].size;
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cs_free( insn, count );
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}
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static BOOL be_arm_get_addr(HANDLE hThread, const dbg_ctx_t *ctx,
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enum be_cpu_addr bca, ADDRESS64* addr)
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{
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switch (bca)
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{
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case be_cpu_addr_pc:
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return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Pc);
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case be_cpu_addr_stack:
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return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Sp);
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case be_cpu_addr_frame:
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return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.R11);
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}
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return FALSE;
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}
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static BOOL be_arm_get_register_info(int regno, enum be_cpu_addr* kind)
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{
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switch (regno)
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{
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case CV_ARM_PC: *kind = be_cpu_addr_pc; return TRUE;
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case CV_ARM_R0 + 11: *kind = be_cpu_addr_frame; return TRUE;
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case CV_ARM_SP: *kind = be_cpu_addr_stack; return TRUE;
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}
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return FALSE;
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}
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static void be_arm_single_step(dbg_ctx_t *ctx, BOOL enable)
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{
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}
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static void be_arm_print_context(HANDLE hThread, const dbg_ctx_t *ctx, int all_regs)
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{
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static const char condflags[] = "NZCV";
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int i;
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char buf[8];
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switch (ctx->ctx.Cpsr & 0x1F)
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{
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case 0: strcpy(buf, "User26"); break;
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case 1: strcpy(buf, "FIQ26"); break;
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case 2: strcpy(buf, "IRQ26"); break;
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case 3: strcpy(buf, "SVC26"); break;
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case 16: strcpy(buf, "User"); break;
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case 17: strcpy(buf, "FIQ"); break;
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case 18: strcpy(buf, "IRQ"); break;
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case 19: strcpy(buf, "SVC"); break;
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case 23: strcpy(buf, "ABT"); break;
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case 27: strcpy(buf, "UND"); break;
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default: strcpy(buf, "UNKNWN"); break;
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}
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dbg_printf("Register dump:\n");
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dbg_printf("%s %s Mode\n", (ctx->ctx.Cpsr & 0x20) ? "Thumb" : "ARM", buf);
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strcpy(buf, condflags);
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for (i = 0; buf[i]; i++)
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if (!((ctx->ctx.Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
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buf[i] = '-';
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dbg_printf(" Pc:%08lx Sp:%08lx Lr:%08lx Cpsr:%08lx(%s)\n",
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ctx->ctx.Pc, ctx->ctx.Sp, ctx->ctx.Lr, ctx->ctx.Cpsr, buf);
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dbg_printf(" r0:%08lx r1:%08lx r2:%08lx r3:%08lx\n",
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ctx->ctx.R0, ctx->ctx.R1, ctx->ctx.R2, ctx->ctx.R3);
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dbg_printf(" r4:%08lx r5:%08lx r6:%08lx r7:%08lx\n",
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ctx->ctx.R4, ctx->ctx.R5, ctx->ctx.R6, ctx->ctx.R7);
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dbg_printf(" r8:%08lx r9:%08lx r10:%08lx r11:%08lx r12:%08lx\n",
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ctx->ctx.R8, ctx->ctx.R9, ctx->ctx.R10, ctx->ctx.R11, ctx->ctx.R12);
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if (all_regs) dbg_printf( "Floating point ARM dump not implemented\n" );
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}
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static void be_arm_print_segment_info(HANDLE hThread, const dbg_ctx_t *ctx)
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{
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}
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static struct dbg_internal_var be_arm_ctx[] =
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{
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{CV_ARM_R0 + 0, "r0", (void*)FIELD_OFFSET(CONTEXT, R0), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 1, "r1", (void*)FIELD_OFFSET(CONTEXT, R1), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 2, "r2", (void*)FIELD_OFFSET(CONTEXT, R2), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 3, "r3", (void*)FIELD_OFFSET(CONTEXT, R3), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 4, "r4", (void*)FIELD_OFFSET(CONTEXT, R4), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 5, "r5", (void*)FIELD_OFFSET(CONTEXT, R5), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 6, "r6", (void*)FIELD_OFFSET(CONTEXT, R6), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 7, "r7", (void*)FIELD_OFFSET(CONTEXT, R7), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 8, "r8", (void*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 9, "r9", (void*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 10, "r10", (void*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 11, "r11", (void*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_int32},
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{CV_ARM_R0 + 12, "r12", (void*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_int32},
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{CV_ARM_SP, "sp", (void*)FIELD_OFFSET(CONTEXT, Sp), dbg_itype_unsigned_int32},
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{CV_ARM_LR, "lr", (void*)FIELD_OFFSET(CONTEXT, Lr), dbg_itype_unsigned_int32},
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{CV_ARM_PC, "pc", (void*)FIELD_OFFSET(CONTEXT, Pc), dbg_itype_unsigned_int32},
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{CV_ARM_CPSR, "cpsr", (void*)FIELD_OFFSET(CONTEXT, Cpsr), dbg_itype_unsigned_int32},
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{0, NULL, 0, dbg_itype_none}
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};
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static BOOL be_arm_is_step_over_insn(const void* insn)
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{
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dbg_printf("be_arm_is_step_over_insn: not done\n");
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return FALSE;
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}
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static BOOL be_arm_is_function_return(const void* insn)
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{
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dbg_printf("be_arm_is_function_return: not done\n");
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return FALSE;
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}
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static BOOL be_arm_is_break_insn(const void* insn)
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{
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dbg_printf("be_arm_is_break_insn: not done\n");
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return FALSE;
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}
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static BOOL be_arm_is_func_call(const void* insn, ADDRESS64* callee)
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{
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return FALSE;
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}
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static BOOL be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
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{
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return FALSE;
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}
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static BOOL be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
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dbg_ctx_t *ctx, enum be_xpoint_type type,
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void* addr, unsigned *val, unsigned size)
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{
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SIZE_T sz;
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switch (type)
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{
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case be_xpoint_break:
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if (!size) return FALSE;
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if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return FALSE;
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default:
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dbg_printf("Unknown/unsupported bp type %c\n", type);
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return FALSE;
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}
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return TRUE;
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}
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static BOOL be_arm_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
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dbg_ctx_t *ctx, enum be_xpoint_type type,
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void* addr, unsigned val, unsigned size)
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{
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SIZE_T sz;
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switch (type)
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{
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case be_xpoint_break:
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if (!size) return FALSE;
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if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return FALSE;
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break;
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default:
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dbg_printf("Unknown/unsupported bp type %c\n", type);
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return FALSE;
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}
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return TRUE;
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}
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static BOOL be_arm_is_watchpoint_set(const dbg_ctx_t *ctx, unsigned idx)
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{
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dbg_printf("be_arm_is_watchpoint_set: not done\n");
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return FALSE;
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}
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static void be_arm_clear_watchpoint(dbg_ctx_t *ctx, unsigned idx)
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{
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dbg_printf("be_arm_clear_watchpoint: not done\n");
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}
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static int be_arm_adjust_pc_for_break(dbg_ctx_t *ctx, BOOL way)
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{
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INT step = (ctx->ctx.Cpsr & 0x20) ? 2 : 4;
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if (way)
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{
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ctx->ctx.Pc -= step;
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return -step;
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}
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ctx->ctx.Pc += step;
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return step;
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}
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static BOOL be_arm_get_context(HANDLE thread, dbg_ctx_t *ctx)
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{
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ctx->ctx.ContextFlags = CONTEXT_ALL;
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return GetThreadContext(thread, &ctx->ctx);
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}
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static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx)
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{
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return SetThreadContext(thread, &ctx->ctx);
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}
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#define REG(f,n,t,r) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)}
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static struct gdb_register be_arm_gdb_register_map[] = {
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REG("core", "r0", NULL, R0),
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REG(NULL, "r1", NULL, R1),
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REG(NULL, "r2", NULL, R2),
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REG(NULL, "r3", NULL, R3),
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REG(NULL, "r4", NULL, R4),
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REG(NULL, "r5", NULL, R5),
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REG(NULL, "r6", NULL, R6),
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REG(NULL, "r7", NULL, R7),
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REG(NULL, "r8", NULL, R8),
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REG(NULL, "r9", NULL, R9),
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REG(NULL, "r10", NULL, R10),
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REG(NULL, "r11", NULL, R11),
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REG(NULL, "r12", NULL, R12),
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REG(NULL, "sp", "data_ptr", Sp),
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REG(NULL, "lr", "code_ptr", Lr),
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REG(NULL, "pc", "code_ptr", Pc),
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REG(NULL, "cpsr", NULL, Cpsr),
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};
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struct backend_cpu be_arm =
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{
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IMAGE_FILE_MACHINE_ARMNT,
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4,
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be_cpu_linearize,
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be_cpu_build_addr,
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be_arm_get_addr,
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be_arm_get_register_info,
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be_arm_single_step,
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be_arm_print_context,
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be_arm_print_segment_info,
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be_arm_ctx,
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be_arm_is_step_over_insn,
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be_arm_is_function_return,
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be_arm_is_break_insn,
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be_arm_is_func_call,
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be_arm_is_jump,
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be_arm_disasm_one_insn,
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be_arm_insert_Xpoint,
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be_arm_remove_Xpoint,
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be_arm_is_watchpoint_set,
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be_arm_clear_watchpoint,
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be_arm_adjust_pc_for_break,
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be_arm_get_context,
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be_arm_set_context,
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be_arm_gdb_register_map,
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ARRAY_SIZE(be_arm_gdb_register_map),
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};
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#endif
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