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da65c809d9
Add patch from upstream PR for Hexagon tests ref: https://github.com/llvm/llvm-project/pull/66785 Revert commit that makes x86_64 test fail ref: https://github.com/llvm/llvm-project/issues/66776 Add workaround for miscompile(?) on armv 32 bit. https://github.com/llvm/llvm-project/issues/62195
31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
Patch-Source: https://github.com/rust-lang/llvm-project/commit/0a157fd7a5f61973ffddf96b3d445a718193eb1a
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From 0a157fd7a5f61973ffddf96b3d445a718193eb1a Mon Sep 17 00:00:00 2001
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From: Cameron Hart <cameron.hart@gmail.com>
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Date: Sun, 10 Jul 2016 23:55:53 +1000
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Subject: [PATCH] [rust] Add accessors for MCSubtargetInfo CPU and Feature
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tables
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This is needed for `-C target-cpu=help` and `-C target-feature=help` in rustc
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---
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llvm/include/llvm/MC/MCSubtargetInfo.h | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h
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index e1f0a86141e36..1e529bf4fb31e 100644
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--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
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+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
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@@ -230,6 +230,14 @@ class MCSubtargetInfo {
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return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
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}
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+ ArrayRef<SubtargetSubTypeKV> getCPUTable() const {
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+ return ProcDesc;
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+ }
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+
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+ ArrayRef<SubtargetFeatureKV> getFeatureTable() const {
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+ return ProcFeatures;
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+ }
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+
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virtual unsigned getHwMode() const { return 0; }
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/// Return the cache size in bytes for the given level of cache.
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