aports/main/llvm18/llvm-riscv-xthreadmempair.patch

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 08678a859ae2..23083672b4e1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1403,8 +1403,10 @@
                          ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS,
                          ISD::EXPERIMENTAL_VP_REVERSE, ISD::MUL,
                          ISD::INSERT_VECTOR_ELT});
-  if (Subtarget.hasVendorXTHeadMemPair())
-    setTargetDAGCombine({ISD::LOAD, ISD::STORE});
+  if (Subtarget.hasVendorXTHeadMemPair()) {
+    setTargetDAGCombine(ISD::LOAD);
+    setTargetDAGCombine(ISD::STORE);
+  }
   if (Subtarget.useRVVForFixedLengthVectors())
     setTargetDAGCombine(ISD::BITCAST);