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https://gitlab.alpinelinux.org/alpine/aports.git
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94d1aa3863
remove esmil-6.10-rc1.jh7110.patch, mostly applied to mainline add few patches from https://github.com/drmpeg/linux which are not yet in mainline kernel
80 lines
3.2 KiB
Diff
80 lines
3.2 KiB
Diff
From 7716903f7e63c2fd918f3cabdb1d1399df1e8d57 Mon Sep 17 00:00:00 2001
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From: Kevin Xie <kevin.xie@starfivetech.com>
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Date: Tue, 27 Feb 2024 18:35:21 +0800
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Subject: [PATCH] PCI: starfive: Offload the NVMe timeout workaround to host
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drivers.
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As the Starfive JH7110 hardware can't keep two inbound post write in
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order all the time, such as MSI messages and NVMe completions. If the
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NVMe completion update later than the MSI, an NVMe IRQ handle will miss.
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As a workaround, we will wait a while before going to the generic
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handle here.
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Verified with NVMe SSD, USB SSD, R8169 NIC.
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The performance are stable and even higher after this patch.
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Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Link: https://lore.kernel.org/r/20240227103522.80915-23-minda.chen@starfivetech.com
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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---
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drivers/pci/controller/plda/pcie-plda-host.c | 12 ++++++++++++
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drivers/pci/controller/plda/pcie-plda.h | 1 +
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drivers/pci/controller/plda/pcie-starfive.c | 1 +
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3 files changed, 14 insertions(+)
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diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c
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index a18923d7cea6e7..9e077ddf45c07e 100644
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--- a/drivers/pci/controller/plda/pcie-plda-host.c
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+++ b/drivers/pci/controller/plda/pcie-plda-host.c
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@@ -13,6 +13,7 @@
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#include <linux/msi.h>
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#include <linux/pci_regs.h>
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#include <linux/pci-ecam.h>
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+#include <linux/delay.h>
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#include "pcie-plda.h"
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@@ -44,6 +45,17 @@ static void plda_handle_msi(struct irq_desc *desc)
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bridge_base_addr + ISTATUS_LOCAL);
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status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
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for_each_set_bit(bit, &status, msi->num_vectors) {
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+ /*
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+ * As the Starfive JH7110 hardware can't keep two
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+ * inbound post write in order all the time, such as
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+ * MSI messages and NVMe completions.
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+ * If the NVMe completion update later than the MSI,
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+ * an NVMe IRQ handle will miss.
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+ * As a workaround, we will wait a while before
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+ * going to the generic handle here.
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+ */
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+ if (port->msi_quirk_delay_us)
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+ udelay(port->msi_quirk_delay_us);
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ret = generic_handle_domain_irq(msi->dev_domain, bit);
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if (ret)
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dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
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diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h
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index 0e7dc0d8e5ba11..074aecce54a2dd 100644
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--- a/drivers/pci/controller/plda/pcie-plda.h
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+++ b/drivers/pci/controller/plda/pcie-plda.h
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@@ -187,6 +187,7 @@ struct plda_pcie_rp {
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int msi_irq;
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int intx_irq;
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int num_events;
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+ u16 msi_quirk_delay_us;
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};
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struct plda_event {
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diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
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index c9933ecf683382..5d8927f27684a2 100644
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--- a/drivers/pci/controller/plda/pcie-starfive.c
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+++ b/drivers/pci/controller/plda/pcie-starfive.c
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@@ -406,6 +406,7 @@ static int starfive_pcie_probe(struct platform_device *pdev)
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plda->host_ops = &sf_host_ops;
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plda->num_events = PLDA_MAX_EVENT_NUM;
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+ plda->msi_quirk_delay_us = 1;
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/* mask doorbell event */
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plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
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& ~BIT(PLDA_AXI_DOORBELL)
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