mirror of
https://gitlab.alpinelinux.org/alpine/aports.git
synced 2025-04-05 04:47:14 +02:00
2824 lines
120 KiB
Diff
2824 lines
120 KiB
Diff
Ran 2to3 to run python code on python3
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/checker.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/checker.py 2024-01-11 13:10:59.751756535 +0100
|
|
@@ -16,5 +16,5 @@ for root, dirs, files in os.walk(os.path
|
|
for line in fread:
|
|
l = line.strip()
|
|
if len(l) > args.len:
|
|
- print "{0}: {1}".format(i, l)
|
|
+ print("{0}: {1}".format(i, l))
|
|
i = i+1
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/trace_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/trace_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/trace_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_me/software/py/trace_gen.py 2024-01-11 13:10:59.638424702 +0100
|
|
@@ -19,7 +19,7 @@ class TraceGen:
|
|
# print header
|
|
def print_header(self):
|
|
print("#### generated by trace_gen.py ####")
|
|
- print("#### packet_len = " + str(self.packet_len) + " ####")
|
|
+ print(("#### packet_len = " + str(self.packet_len) + " ####"))
|
|
|
|
# send load
|
|
# signed: sign extend or not
|
|
@@ -88,20 +88,20 @@ class TraceGen:
|
|
# wait for a number of cycles
|
|
# num_cycles: number of cycles to wait.
|
|
def wait(self, num_cycles):
|
|
- print("0110_" + format(num_cycles, "0" + str(self.packet_len-4) + "b"))
|
|
- print("0101_" + (self.packet_len-4)*"0")
|
|
+ print(("0110_" + format(num_cycles, "0" + str(self.packet_len-4) + "b")))
|
|
+ print(("0101_" + (self.packet_len-4)*"0"))
|
|
|
|
# finish trace
|
|
def test_finish(self):
|
|
print("#### FINISH ####")
|
|
self.wait(8)
|
|
- print("0100_" + (self.packet_len-4)*"0")
|
|
+ print(("0100_" + (self.packet_len-4)*"0"))
|
|
|
|
def test_done(self):
|
|
print("#### DONE ####")
|
|
self.wait(8)
|
|
- print("0011_" + (self.packet_len-4)*"0")
|
|
+ print(("0011_" + (self.packet_len-4)*"0"))
|
|
|
|
# wait for a single cycle
|
|
def nop(self):
|
|
- print("0000_" + "0"*(self.packet_len-4))
|
|
+ print(("0000_" + "0"*(self.packet_len-4)))
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_top/software/py/ptgen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_top/software/py/ptgen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_top/software/py/ptgen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_top/software/py/ptgen.py 2024-01-11 13:11:00.115085056 +0100
|
|
@@ -3,14 +3,14 @@ import sys
|
|
import math
|
|
|
|
def help():
|
|
- print "Usage: ptgen.py <outfile> <root table address> <data sections roots> <data sections size(in pages)>"
|
|
- print "Example: python ptgen.py pt.S 0x80008000 0x80000000,0x8fffc000 4,1"
|
|
+ print("Usage: ptgen.py <outfile> <root table address> <data sections roots> <data sections size(in pages)>")
|
|
+ print("Example: python ptgen.py pt.S 0x80008000 0x80000000,0x8fffc000 4,1")
|
|
|
|
def int2hex(num, width):
|
|
return "{0:#0{1}x}".format(num,width/4 + 2)
|
|
|
|
def checkAddr(vpn, as_start_vpn, as_size, page_pte_num, level, pt_depth):
|
|
- for i in xrange(len(as_start_vpn)):
|
|
+ for i in range(len(as_start_vpn)):
|
|
as_start = as_start_vpn[i]
|
|
as_end = as_start_vpn[i] + as_size[i] - 1
|
|
|
|
@@ -26,7 +26,7 @@ try:
|
|
fileName = str(sys.argv[1])
|
|
root_table_addr = sys.argv[2]
|
|
as_start = sys.argv[3].split(',')
|
|
- as_size = map(int, sys.argv[4].split(','))
|
|
+ as_size = list(map(int, sys.argv[4].split(',')))
|
|
except:
|
|
help()
|
|
quit()
|
|
@@ -45,7 +45,7 @@ page_size = 2**page_offset_width
|
|
root_table_ppn = int(root_table_addr, 16)/page_size
|
|
|
|
as_start_vpn = [0]*len(as_start)
|
|
-for i in xrange(len(as_start)):
|
|
+for i in range(len(as_start)):
|
|
as_start_vpn[i] = int(as_start[i], 16)/page_size
|
|
|
|
vpn_width = vaddr_width - page_offset_width
|
|
@@ -65,10 +65,10 @@ page_table = []
|
|
|
|
pt_table_num[0] = 1
|
|
table_vpns = [[0], [], []]
|
|
-for level in xrange(1, pt_depth):
|
|
+for level in range(1, pt_depth):
|
|
last_vpn = -1
|
|
#print "#######"
|
|
- for j in xrange(len(as_start_vpn)):
|
|
+ for j in range(len(as_start_vpn)):
|
|
masked_vpn = as_start_vpn[j] >> ((pt_depth-level)*lg_page_pte_num)
|
|
masked_vpn = masked_vpn << ((pt_depth-level)*lg_page_pte_num)
|
|
if(last_vpn != masked_vpn):
|
|
@@ -78,9 +78,9 @@ for level in xrange(1, pt_depth):
|
|
pt_table_num[level] += 1
|
|
|
|
last_ppn = root_table_ppn
|
|
-for level in xrange(pt_depth):
|
|
+for level in range(pt_depth):
|
|
pt_roots.append([])
|
|
- for tableNum in xrange(pt_table_num[level]):
|
|
+ for tableNum in range(pt_table_num[level]):
|
|
pt_roots[level].append(last_ppn)
|
|
last_ppn += 1
|
|
|
|
@@ -88,13 +88,13 @@ for level in xrange(pt_depth):
|
|
#print pt_roots
|
|
#print table_vpns
|
|
|
|
-for level in xrange(pt_depth):
|
|
+for level in range(pt_depth):
|
|
page_table.append([])
|
|
#print "---------"
|
|
- for tableNum in xrange(pt_table_num[level]):
|
|
+ for tableNum in range(pt_table_num[level]):
|
|
page_table[level].append([])
|
|
target_tableNum = 0
|
|
- for offset in xrange(page_pte_num):
|
|
+ for offset in range(page_pte_num):
|
|
|
|
vpn = table_vpns[level][tableNum] + (offset << ((pt_depth-level-1)*lg_page_pte_num))
|
|
|
|
@@ -134,8 +134,8 @@ outfile.write("/* address space size in
|
|
outfile.write(".section \".data.pt\"\n")
|
|
outfile.write(".globl _pt\n\n")
|
|
outfile.write("_pt:\n")
|
|
-for i in xrange(len(page_table)):
|
|
- for j in xrange(len(page_table[i])):
|
|
- for k in xrange(len(page_table[i][j])):
|
|
+for i in range(len(page_table)):
|
|
+ for j in range(len(page_table[i])):
|
|
+ for k in range(len(page_table[i][j])):
|
|
outfile.write(" .dword " + int2hex(page_table[i][j][k], 64) + "\n")
|
|
outfile.close()
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_scatter_gather.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_scatter_gather.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_scatter_gather.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_scatter_gather.py 2024-01-11 13:11:00.898408014 +0100
|
|
@@ -39,13 +39,13 @@ def bits_to_rep(x) :
|
|
return len(bin(x-1))-2;
|
|
|
|
def print_case_line(a,result,var_name,result_x):
|
|
- print " ",str(len(a))+"'b",
|
|
+ print(" ",str(len(a))+"'b", end=' ')
|
|
print_bit_list(a)
|
|
- print ": "+var_name+" = ",str(bits_to_rep(len(a))*len(a))+"'b",
|
|
+ print(": "+var_name+" = ",str(bits_to_rep(len(a))*len(a))+"'b", end=' ')
|
|
for x in reversed(result) :
|
|
print_bit_list(int_to_bit_list(x,bits_to_rep(len(a))));
|
|
#sys.stdout.write("_")
|
|
- print "; // ", ' '.join([str(y) for y in reversed(result_x)]);
|
|
+ print("; // ", ' '.join([str(y) for y in reversed(result_x)]));
|
|
|
|
def gen_vec(channels, fn) :
|
|
|
|
@@ -55,7 +55,7 @@ def gen_vec(channels, fn) :
|
|
for j in range(0,2**channels) :
|
|
q = fn(int_to_bit_list(j,channels))
|
|
|
|
- print (" default: "+q+"= 'X;");
|
|
+ print((" default: "+q+"= 'X;"));
|
|
print (" endcase");
|
|
|
|
def gen_fwd_vec_line_helper(a,dpath) :
|
|
@@ -134,23 +134,23 @@ def gen_back_vec_line(a) :
|
|
|
|
def generate_code_for_channel(chan) :
|
|
|
|
- print "\nif (vec_size_lp == "+str(chan)+")"
|
|
- print " begin"
|
|
+ print("\nif (vec_size_lp == "+str(chan)+")")
|
|
+ print(" begin")
|
|
|
|
- print " // backward vec";
|
|
+ print(" // backward vec");
|
|
|
|
gen_vec(chan,gen_back_vec_line)
|
|
|
|
- print "\n // backward vec datapath";
|
|
+ print("\n // backward vec datapath");
|
|
|
|
gen_vec(chan,gen_back_vec_line_dpath)
|
|
|
|
|
|
- print "\n // fwd vec";
|
|
+ print("\n // fwd vec");
|
|
|
|
gen_vec(chan,gen_fwd_vec_line)
|
|
|
|
- print "\n // fwd datapath vec";
|
|
+ print("\n // fwd datapath vec");
|
|
|
|
gen_vec(chan,gen_fwd_vec_line_dpath)
|
|
|
|
@@ -161,7 +161,7 @@ def generate_code_for_channel(chan) :
|
|
|
|
|
|
|
|
-print """
|
|
+print("""
|
|
// MBT 8-18-2014
|
|
// bsg_scatter_gather
|
|
// generated by bsg_scatter_gather.py;
|
|
@@ -196,19 +196,19 @@ module bsg_scatter_gather #(`BSG_INV_PAR
|
|
,output reg [vec_size_lp*`BSG_SAFE_CLOG2(vec_size_lp)-1:0] bk_o
|
|
,output reg [vec_size_lp*`BSG_SAFE_CLOG2(vec_size_lp)-1:0] bk_datapath_o
|
|
);
|
|
-"""
|
|
+""")
|
|
|
|
|
|
for x in channels :
|
|
generate_code_for_channel(x)
|
|
|
|
-print "// synopsys translate_off";
|
|
-print "initial assert (vec_size_lp < ",max_channel,") else $error(\"bsg_scatter_gather: vec_size_lp too large %d\", vec_size_lp);";
|
|
-print "// synopsys translate_on";
|
|
+print("// synopsys translate_off");
|
|
+print("initial assert (vec_size_lp < ",max_channel,") else $error(\"bsg_scatter_gather: vec_size_lp too large %d\", vec_size_lp);");
|
|
+print("// synopsys translate_on");
|
|
|
|
-print "endmodule";
|
|
+print("endmodule");
|
|
|
|
-print "`BSG_ABSTRACT_MODULE(bsg_scatter_gather)"
|
|
+print("`BSG_ABSTRACT_MODULE(bsg_scatter_gather)")
|
|
|
|
#for i in range(1,10) :
|
|
# print i,bits_to_rep(i)
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_ascii_to_rom.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_ascii_to_rom.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_ascii_to_rom.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_ascii_to_rom.py 2024-01-11 13:11:01.358401921 +0100
|
|
@@ -27,37 +27,37 @@ if ((len(sys.argv)==4) and sys.argv[3]==
|
|
zero = 1;
|
|
|
|
if ((len(sys.argv)!=3) and (len(sys.argv)!=4)) :
|
|
- print "Usage ascii_to_rom.py <filename> <modulename>";
|
|
+ print("Usage ascii_to_rom.py <filename> <modulename>");
|
|
exit -1
|
|
|
|
myFile = open(sys.argv[1],"r");
|
|
|
|
i = 0;
|
|
-print "// auto-generated by bsg_ascii_to_rom.py from " + os.path.abspath(sys.argv[1]) + "; do not modify";
|
|
-print "module " + sys.argv[2] + " #(`BSG_INV_PARAM(width_p), `BSG_INV_PARAM(addr_width_p))";
|
|
-print "(input [addr_width_p-1:0] addr_i";
|
|
-print ",output logic [width_p-1:0] data_o";
|
|
-print ");";
|
|
-print "always_comb case(addr_i)"
|
|
+print("// auto-generated by bsg_ascii_to_rom.py from " + os.path.abspath(sys.argv[1]) + "; do not modify");
|
|
+print("module " + sys.argv[2] + " #(`BSG_INV_PARAM(width_p), `BSG_INV_PARAM(addr_width_p))");
|
|
+print("(input [addr_width_p-1:0] addr_i");
|
|
+print(",output logic [width_p-1:0] data_o");
|
|
+print(");");
|
|
+print("always_comb case(addr_i)")
|
|
all_zero = set("0_");
|
|
for line in myFile.readlines() :
|
|
line = line.strip();
|
|
if (len(line)!=0):
|
|
if (line[0] != "#") :
|
|
if (not zero or not (set(line) <= all_zero)) :
|
|
- digits_only = filter(lambda m:m.isdigit(), str(line));
|
|
+ digits_only = [m for m in str(line) if m.isdigit()];
|
|
|
|
# http://stackoverflow.com/questions/2072351/python-conversion-from-binary-string-to-hexadecimal
|
|
hstr = '%0*X' % ((len(digits_only) + 3) // 4, int(digits_only, 2))
|
|
|
|
- print str(i).rjust(10)+": data_o = width_p ' (" + str(len(digits_only))+ "'b"+line+");"+" // 0x"+hstr;
|
|
+ print(str(i).rjust(10)+": data_o = width_p ' (" + str(len(digits_only))+ "'b"+line+");"+" // 0x"+hstr);
|
|
i = i + 1;
|
|
else :
|
|
- print " // " + line;
|
|
+ print(" // " + line);
|
|
if (zero) :
|
|
- print "default".rjust(10) + ": data_o = { width_p { 1'b0 } };"
|
|
+ print("default".rjust(10) + ": data_o = { width_p { 1'b0 } };")
|
|
else :
|
|
- print "default".rjust(10) + ": data_o = 'X;"
|
|
-print "endcase"
|
|
-print "endmodule"
|
|
-print "`BSG_ABSTRACT_MODULE(" + sys.argv[2] + ")"
|
|
+ print("default".rjust(10) + ": data_o = 'X;")
|
|
+print("endcase")
|
|
+print("endmodule")
|
|
+print("`BSG_ABSTRACT_MODULE(" + sys.argv[2] + ")")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.py 2024-01-11 13:10:59.991753356 +0100
|
|
@@ -46,31 +46,31 @@ def print_hold_on_logic(last_w, reqs_w):
|
|
"""
|
|
Print the logic of the hold on logic
|
|
"""
|
|
- print """
|
|
-if ( hold_on_sr_p ) begin """
|
|
- print """
|
|
+ print("""
|
|
+if ( hold_on_sr_p ) begin """)
|
|
+ print("""
|
|
always_comb begin
|
|
- unique casez( last_r )"""
|
|
+ unique casez( last_r )""")
|
|
for last_r in range(reqs_w ):
|
|
last_r_str = bin(last_r)[2:].zfill(last_w);
|
|
req_str = get_single_request_str(last_r, reqs_w)
|
|
#Full cases
|
|
if( (last_r == ( (1<< last_w) -1 ) ) & (last_r == (reqs_w-1) ) ):
|
|
- print """ default: hold_on_sr = ( reqs_i == %d'b%s );"""%( reqs_w, req_str)
|
|
+ print(""" default: hold_on_sr = ( reqs_i == %d'b%s );"""%( reqs_w, req_str))
|
|
#Not Full cases
|
|
else :
|
|
- print """ %d'b%s : hold_on_sr = ( reqs_i == %d'b%s );"""%( last_w, last_r_str, reqs_w, req_str)
|
|
+ print(""" %d'b%s : hold_on_sr = ( reqs_i == %d'b%s );"""%( last_w, last_r_str, reqs_w, req_str))
|
|
|
|
#Not full cases
|
|
if( (1<< last_w ) != reqs_w ):
|
|
- print """ default : hold_on_sr = 1'b0;"""
|
|
+ print(""" default : hold_on_sr = 1'b0;""")
|
|
|
|
- print """ endcase
|
|
+ print(""" endcase
|
|
end //end of always_comb
|
|
|
|
end else begin:not_hold_on_sr_p
|
|
assign hold_on_sr = '0;
|
|
-end //end of hold_on_sr_p """
|
|
+end //end of hold_on_sr_p """)
|
|
|
|
################################################################################
|
|
# Logic for priority reset logic
|
|
@@ -83,28 +83,28 @@ def print_reset_on_logic(reqs_w):
|
|
|
|
req_str= get_single_request_str(0, reqs_w)
|
|
|
|
- print """
|
|
+ print("""
|
|
if ( reset_on_sr_p ) begin:reset_on_%d
|
|
- assign reset_on_sr = ( reqs_i == %d'b%s ) """%( reqs_w,reqs_w, req_str)
|
|
+ assign reset_on_sr = ( reqs_i == %d'b%s ) """%( reqs_w,reqs_w, req_str))
|
|
|
|
for curr_r in range(1, reqs_w):
|
|
req_str= get_single_request_str(curr_r, reqs_w)
|
|
- print """ | ( reqs_i == %d'b%s ) """ %(reqs_w, req_str )
|
|
+ print(""" | ( reqs_i == %d'b%s ) """ %(reqs_w, req_str ))
|
|
|
|
- print " ;"
|
|
- print """
|
|
+ print(" ;")
|
|
+ print("""
|
|
end else begin:not_reset_on_sr_p
|
|
assign reset_on_sr = '0;
|
|
-end //end of reset_on_sr_p """
|
|
+end //end of reset_on_sr_p """)
|
|
max_reqs = 0 # no. of inputs
|
|
try:
|
|
assert len(sys.argv) == 2
|
|
max_reqs = int(sys.argv[1])
|
|
except:
|
|
- print "UsageError: bsg_round_robin_arb.py <max no. of channels>"
|
|
+ print("UsageError: bsg_round_robin_arb.py <max no. of channels>")
|
|
sys.exit()
|
|
|
|
-print """// Round robin arbitration unit
|
|
+print("""// Round robin arbitration unit
|
|
|
|
// Automatically generated using bsg_round_robin_arb.py
|
|
// NOTE: generally prefer https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_arb_round_robin.v to this module
|
|
@@ -122,9 +122,9 @@ print """// Round robin arbitration unit
|
|
|
|
`include "bsg_defines.v"
|
|
|
|
-"""
|
|
+""")
|
|
|
|
-print """module bsg_round_robin_arb #(`BSG_INV_PARAM(inputs_p)
|
|
+print("""module bsg_round_robin_arb #(`BSG_INV_PARAM(inputs_p)
|
|
,lg_inputs_p =`BSG_SAFE_CLOG2(inputs_p)
|
|
,reset_on_sr_p = 1'b0
|
|
,hold_on_sr_p = 1'b0
|
|
@@ -135,9 +135,9 @@ print """module bsg_round_robin_arb #(`B
|
|
// with bsg_parallel_in_serial_out_passthrough. This policy
|
|
// has a slight throughput degradation but effectively
|
|
// arbitrates based on age, so minimizes worst case latency.
|
|
- ,hold_on_valid_p = 1'b0)""" % '''-1'''
|
|
+ ,hold_on_valid_p = 1'b0)""" % '''-1''')
|
|
|
|
-print """ (input clk_i
|
|
+print(""" (input clk_i
|
|
, input reset_i
|
|
, input grants_en_i // whether to suppress grants_o
|
|
|
|
@@ -158,10 +158,10 @@ print """ (input clk_i
|
|
logic [lg_inputs_p-1:0] last, last_n, last_r;
|
|
logic hold_on_sr, reset_on_sr;
|
|
|
|
-"""
|
|
+""")
|
|
|
|
for reqs_w in range(1, max_reqs+1):
|
|
- print """
|
|
+ print("""
|
|
if(inputs_p == %d)
|
|
begin: inputs_%d
|
|
|
|
@@ -169,15 +169,15 @@ logic [%d-1: 0 ] sel_one_hot_n;
|
|
|
|
always_comb
|
|
begin
|
|
- unique casez({last_r, reqs_i})""" % (reqs_w, reqs_w, reqs_w)
|
|
+ unique casez({last_r, reqs_i})""" % (reqs_w, reqs_w, reqs_w))
|
|
|
|
last_w = int(math.ceil(math.log(reqs_w)/math.log(2))) if (reqs_w!=1) else 1
|
|
# print " %d'b"%(1+last_w+reqs_w) + "0" + "_" + "?"*last_w + "_" + "?"*reqs_w + ":"\
|
|
# , "begin sel_one_hot_n="\
|
|
# , "%d'b"%reqs_w + "0"*reqs_w + "; tag_o = (lg_inputs_p) ' (0); end // X"
|
|
- print " %d'b"%(last_w+reqs_w) + "?"*last_w + "_" + "0"*reqs_w + ":"\
|
|
+ print(" %d'b"%(last_w+reqs_w) + "?"*last_w + "_" + "0"*reqs_w + ":"\
|
|
, "begin sel_one_hot_n ="\
|
|
- , "%d'b"%reqs_w + "0"*reqs_w + "; tag_o = (lg_inputs_p) ' (0); end // X"
|
|
+ , "%d'b"%reqs_w + "0"*reqs_w + "; tag_o = (lg_inputs_p) ' (0); end // X")
|
|
|
|
grants = {}
|
|
for i in range(reqs_w):
|
|
@@ -185,29 +185,29 @@ begin
|
|
|
|
for key in grants:
|
|
for req in grants[key]:
|
|
- print " %d'b"%(last_w+reqs_w) + bin(key)[2:].zfill(last_w)\
|
|
+ print(" %d'b"%(last_w+reqs_w) + bin(key)[2:].zfill(last_w)\
|
|
+ "_" + req[0] + ":"\
|
|
, "begin sel_one_hot_n="\
|
|
- , "%d'b"%reqs_w + req[1] + "; tag_o = (lg_inputs_p) ' ("+str(req[1][::-1].index('1'))+"); end"
|
|
+ , "%d'b"%reqs_w + req[1] + "; tag_o = (lg_inputs_p) ' ("+str(req[1][::-1].index('1'))+"); end")
|
|
|
|
- print """ default: begin sel_one_hot_n= {%d{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X
|
|
+ print(""" default: begin sel_one_hot_n= {%d{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X
|
|
endcase
|
|
-end """% (reqs_w)
|
|
+end """% (reqs_w))
|
|
|
|
- print """
|
|
+ print("""
|
|
assign sel_one_hot_o = sel_one_hot_n;
|
|
assign grants_o = sel_one_hot_n & {%d{grants_en_i}} ;
|
|
- """% (reqs_w)
|
|
+ """% (reqs_w))
|
|
|
|
print_hold_on_logic(last_w, reqs_w)
|
|
|
|
print_reset_on_logic(reqs_w)
|
|
|
|
|
|
- print """
|
|
-end: inputs_%d""" % (reqs_w)
|
|
+ print("""
|
|
+end: inputs_%d""" % (reqs_w))
|
|
|
|
-print """
|
|
+print("""
|
|
|
|
assign v_o = | reqs_i ;
|
|
|
|
@@ -238,4 +238,4 @@ endmodule
|
|
|
|
`BSG_ABSTRACT_MODULE(bsg_round_robin_arb)
|
|
|
|
-"""
|
|
+""")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_to_ring_stitch.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_to_ring_stitch.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_to_ring_stitch.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_to_ring_stitch.py 2024-01-11 13:11:01.135071546 +0100
|
|
@@ -16,22 +16,22 @@
|
|
topX = 8
|
|
topY = 8
|
|
|
|
-print "// AUTOGENERATED FILE; DO NOT MODIFY."
|
|
-print "// run with topX=",topX," and topY=",topY
|
|
-print "// ";
|
|
-print '`include "bsg_defines.v"'
|
|
-
|
|
-print "module bsg_mesh_to_ring_stitch #(`BSG_INV_PARAM(y_max_p)"
|
|
-print " ,`BSG_INV_PARAM(x_max_p)"
|
|
-print " ,`BSG_INV_PARAM(width_back_p)"
|
|
-print " ,`BSG_INV_PARAM(width_fwd_p)"
|
|
-print " ,parameter b_lp = $clog2(x_max_p*y_max_p)"
|
|
-print " ) (output [x_max_p-1:0][y_max_p-1:0][b_lp-1:0] id_o"
|
|
-print " ,output [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_in_o"
|
|
-print " ,input [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_out_i"
|
|
-print " ,output [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_in_o"
|
|
-print " ,input [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_out_i"
|
|
-print " );\n\n"
|
|
+print("// AUTOGENERATED FILE; DO NOT MODIFY.")
|
|
+print("// run with topX=",topX," and topY=",topY)
|
|
+print("// ");
|
|
+print('`include "bsg_defines.v"')
|
|
+
|
|
+print("module bsg_mesh_to_ring_stitch #(`BSG_INV_PARAM(y_max_p)")
|
|
+print(" ,`BSG_INV_PARAM(x_max_p)")
|
|
+print(" ,`BSG_INV_PARAM(width_back_p)")
|
|
+print(" ,`BSG_INV_PARAM(width_fwd_p)")
|
|
+print(" ,parameter b_lp = $clog2(x_max_p*y_max_p)")
|
|
+print(" ) (output [x_max_p-1:0][y_max_p-1:0][b_lp-1:0] id_o")
|
|
+print(" ,output [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_in_o")
|
|
+print(" ,input [x_max_p-1:0][y_max_p-1:0][width_back_p-1:0] back_data_out_i")
|
|
+print(" ,output [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_in_o")
|
|
+print(" ,input [x_max_p-1:0][y_max_p-1:0][width_fwd_p-1:0] fwd_data_out_i")
|
|
+print(" );\n\n")
|
|
|
|
|
|
def print_config (maxX,maxY,order) :
|
|
@@ -41,7 +41,7 @@ def print_config (maxX,maxY,order) :
|
|
my_dict[position] = (x,y);
|
|
matrix[x][y] = position;
|
|
|
|
- print "if (x_max_p ==",maxX," && y_max_p ==",maxY,")\nbegin\n"
|
|
+ print("if (x_max_p ==",maxX," && y_max_p ==",maxY,")\nbegin\n")
|
|
for y in range(maxY-1,-1,-1) :
|
|
for x in range(maxX-1,-1,-1) :
|
|
position=matrix[x][y];
|
|
@@ -49,25 +49,25 @@ def print_config (maxX,maxY,order) :
|
|
above = 0 if ((position + 1) == maxX*maxY) else position + 1;
|
|
(below_x,below_y)=my_dict[below];
|
|
(above_x,above_y)=my_dict[above];
|
|
- print "assign back_data_in_o[",below_x,"][",below_y,"] = back_data_out_i[",x,"][",y,"]; // ",below,"<-",position
|
|
- print "assign fwd_data_in_o [",above_x,"][",above_y,"] = fwd_data_out_i [",x,"][",y,"]; // ",position,"->",above
|
|
- print "\n"
|
|
- print " assign id_o = \n {"
|
|
- print "// y = ",
|
|
+ print("assign back_data_in_o[",below_x,"][",below_y,"] = back_data_out_i[",x,"][",y,"]; // ",below,"<-",position)
|
|
+ print("assign fwd_data_in_o [",above_x,"][",above_y,"] = fwd_data_out_i [",x,"][",y,"]; // ",position,"->",above)
|
|
+ print("\n")
|
|
+ print(" assign id_o = \n {")
|
|
+ print("// y = ", end=' ')
|
|
for y in range(0,maxY) :
|
|
- print str(y)+", ",
|
|
- print "";
|
|
+ print(str(y)+", ", end=' ')
|
|
+ print("");
|
|
for x in range(0,maxX) :
|
|
- print " {",
|
|
+ print(" {", end=' ')
|
|
for y in range(0,maxY) :
|
|
if (y != 0) :
|
|
- print ",",
|
|
- print "b_lp ' (" + str(matrix[x][y]) +")",
|
|
+ print(",", end=' ')
|
|
+ print("b_lp ' (" + str(matrix[x][y]) +")", end=' ')
|
|
if (x != maxX-1) :
|
|
- print " }, // x = ",x
|
|
+ print(" }, // x = ",x)
|
|
else:
|
|
- print " } // x = ",x
|
|
- print " };\nend\n"
|
|
+ print(" } // x = ",x)
|
|
+ print(" };\nend\n")
|
|
|
|
# even X, odd/even Y
|
|
for maxX in range(2,topX+1,2) :
|
|
@@ -103,9 +103,9 @@ for maxX in range(3,topX+1,2) :
|
|
print_config(1,2,[(0,0), (0,1)]);
|
|
print_config(2,1,[(0,0), (1,0)]);
|
|
|
|
-print "initial assert ((x_max_p <= " + str(topX) + ") && (y_max_p <= " + str(topY) +")) else begin $error(\"%m x_max_p %d or y_max_p %d too large; rerun generator with larger size than %d/%d\",x_max_p,y_max_p,"+str(topX)+","+str(topY)+"); $finish(); end "
|
|
+print("initial assert ((x_max_p <= " + str(topX) + ") && (y_max_p <= " + str(topY) +")) else begin $error(\"%m x_max_p %d or y_max_p %d too large; rerun generator with larger size than %d/%d\",x_max_p,y_max_p,"+str(topX)+","+str(topY)+"); $finish(); end ")
|
|
|
|
|
|
-print "endmodule"
|
|
+print("endmodule")
|
|
|
|
-print "`BSG_ABSTRACT_MODULE(bsg_mesh_to_ring_stitch)"
|
|
+print("`BSG_ABSTRACT_MODULE(bsg_mesh_to_ring_stitch)")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/legacy/config_net/sim/generate_tb.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/legacy/config_net/sim/generate_tb.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/legacy/config_net/sim/generate_tb.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/legacy/config_net/sim/generate_tb.py 2024-01-11 13:11:02.871715210 +0100
|
|
@@ -53,7 +53,7 @@ sim_time = 500 # time units
|
|
|
|
# ========== Functions ==========
|
|
def readme():
|
|
- print " \n\
|
|
+ print(" \n\
|
|
Name:\n\
|
|
generate_tb.py - python script to generate testbench for chained config_node instances\n\
|
|
\n\
|
|
@@ -77,7 +77,7 @@ def readme():
|
|
\n\
|
|
You can extend the generated testfile to contain your specific test cases;\n\
|
|
then use command ./generate_tb.py -r <testfile> -o <tb file name> to read the\n\
|
|
- modified file, and create testbench accordingly."
|
|
+ modified file, and create testbench accordingly.")
|
|
|
|
def dec2bin(dec, n): # Only works on non-negative number
|
|
bin = ""
|
|
@@ -186,7 +186,7 @@ argparser.add_argument("--create-probe-f
|
|
|
|
try:
|
|
args = argparser.parse_args()
|
|
-except IOError, msg:
|
|
+except IOError as msg:
|
|
argparser.error(str(msg))
|
|
|
|
# ========== ==========
|
|
@@ -201,8 +201,8 @@ for line in spec_file:
|
|
if (l_words[0] == 'r'): # type 'r' indicates a relay node
|
|
relay_id = int(l_words[1]) # l_words[1] must be consecutive integers starting from 0
|
|
if (relay_id != relay_nodes):
|
|
- print "ERROR spec file format: relay_id must be consecutive integers starting from 0!"
|
|
- print ">>> " + line
|
|
+ print("ERROR spec file format: relay_id must be consecutive integers starting from 0!")
|
|
+ print(">>> " + line)
|
|
sys.exit(1)
|
|
else: # relay_nodes != 0
|
|
if (l_words[1] != '0'): # no need to process relay node 0
|
|
@@ -210,7 +210,7 @@ for line in spec_file:
|
|
branch_id = random.randint(0, relay_nodes - 1) # to which the new relay node is connected
|
|
else:
|
|
branch_id = int(l_words[2]) # l_words[2] must be an integer if not an 'x'
|
|
- if d_relay_tree.has_key(branch_id):
|
|
+ if branch_id in d_relay_tree:
|
|
d_relay_tree[branch_id].append(relay_id)
|
|
else:
|
|
d_relay_tree[branch_id] = [relay_id]
|
|
@@ -222,8 +222,8 @@ for line in spec_file:
|
|
d_inst_data_bits[inst_id] = int(l_words[4])
|
|
d_inst_default[inst_id] = l_words[5]
|
|
else:
|
|
- print "ERROR spec file format: type " + l_words[0] + " is not recognized!"
|
|
- print ">>> " + line
|
|
+ print("ERROR spec file format: type " + l_words[0] + " is not recognized!")
|
|
+ print(">>> " + line)
|
|
sys.exit(1)
|
|
|
|
# randomize d_relay_tree if relay_nodes are not provided in spec file
|
|
@@ -232,7 +232,7 @@ if (relay_nodes == 0):
|
|
for relay_id in range(1, relay_nodes): # relay_id 0 is the root
|
|
# because relay node id are consecutive integers, randint(0, relay_id - 1) makes all nodes are connected
|
|
branch_id = random.randint(0, relay_id - 1) # to which the new relay is connected
|
|
- if d_relay_tree.has_key(branch_id):
|
|
+ if branch_id in d_relay_tree:
|
|
d_relay_tree[branch_id].append(relay_id)
|
|
else:
|
|
d_relay_tree[branch_id] = [relay_id]
|
|
@@ -249,8 +249,8 @@ for line in spec_file:
|
|
if (l_words[2] == 'x'): # position 'x' indicates a random branch
|
|
d_inst_pos[inst_id] = random.randint(0, relay_nodes - 1) # inclusive of 0 and (relay_nodes - 1)
|
|
elif (int(l_words[2]) >= relay_nodes): # l_words[2] must be an integer if not an 'x'
|
|
- print "ERROR spec file format: config node branch id doesn't exist, " + l_words[2] + " >= number of relay nodes = " + str(relay_nodes) + "!"
|
|
- print ">>> " + line
|
|
+ print("ERROR spec file format: config node branch id doesn't exist, " + l_words[2] + " >= number of relay nodes = " + str(relay_nodes) + "!")
|
|
+ print(">>> " + line)
|
|
sys.exit(1)
|
|
else:
|
|
d_inst_pos[inst_id] = int(l_words[2])
|
|
@@ -281,8 +281,8 @@ if (args.generate_tests != None):
|
|
test_file.write(str(l_test_id[test]) + "\t\t" + l_test_data[test] + "\n")
|
|
test_file.close()
|
|
os.system("cat " + test_file.name)
|
|
- print " "
|
|
- print str(number_of_tests) + " sets of random test id and data are generated and written into " + test_file.name
|
|
+ print(" ")
|
|
+ print(str(number_of_tests) + " sets of random test id and data are generated and written into " + test_file.name)
|
|
sys.exit(0) # exit after making the test file
|
|
elif (args.read_tests != None):
|
|
# read existing test file and parse
|
|
@@ -327,7 +327,7 @@ for inst_id in l_inst_id: # initialize d
|
|
test_idx = 0
|
|
for test_id in l_test_id:
|
|
test_data = l_test_data[test_idx]
|
|
- if d_reference.has_key(test_id): # extend an existing test sequence for a node having test_id
|
|
+ if test_id in d_reference: # extend an existing test sequence for a node having test_id
|
|
last_index = len(d_reference[test_id]) - 1
|
|
# if a new data item for an id is the same as its previous one, the new data is not appended.
|
|
if(d_reference[test_id][last_index] != test_data):
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_rf_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_rf_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_rf_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_rf_gen.py 2024-01-11 13:11:01.505066645 +0100
|
|
@@ -18,27 +18,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -69,13 +69,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -134,7 +134,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -148,7 +148,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -197,7 +197,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -211,7 +211,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -271,7 +271,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
emit_wire_definition(ident_name_bit("data_i_inv",b));
|
|
emit_rp_fill(str(column) +" 0 UX")
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";");
|
|
for w in range (0,words) :
|
|
emit_gate_instance(dffe
|
|
,[ ident_name_word_bit("reg",w,b)
|
|
@@ -301,7 +301,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
# AOI22 every pair of words
|
|
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";");
|
|
|
|
for w in range (0,words,2) :
|
|
queue_gate_instance(gate_dict, aoi22
|
|
@@ -357,7 +357,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
, w+(15 if (words > 16) else 13)
|
|
);
|
|
|
|
- print "\n";
|
|
+ print("\n");
|
|
# add inverters to data in, and data out.
|
|
# these are on opposite sides of the array
|
|
# we may potentially pay in delay, but we get
|
|
@@ -381,9 +381,9 @@ def generate_Nr1w_array ( words, bits, r
|
|
# since we are using rp_fill commands
|
|
# but it makes things more readable
|
|
|
|
- for x in sorted(gate_dict.items(), key=lambda x: x[1]) :
|
|
+ for x in sorted(list(gate_dict.items()), key=lambda x: x[1]) :
|
|
emit_rp_fill( str(column) +" "+str(x[1])+" UX")
|
|
- print x[0], "// ",x[1];
|
|
+ print(x[0], "// ",x[1]);
|
|
column=column+1
|
|
|
|
|
|
@@ -393,5 +393,5 @@ def generate_Nr1w_array ( words, bits, r
|
|
if len(sys.argv) == 4 :
|
|
generate_Nr1w_array (int(sys.argv[1]), int(sys.argv[2]), int(sys.argv[3]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " words bits readports";
|
|
+ print("Usage: " + sys.argv[0] + " words bits readports");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_dff_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_dff_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_dff_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_dff_gen.py 2024-01-11 13:11:02.081725673 +0100
|
|
@@ -6,27 +6,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -57,16 +57,16 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def rp_fill_string (params) :
|
|
return "// synopsys rp_fill (" + params + ")"
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -166,6 +166,6 @@ else :
|
|
for b in range (1,int(sys.argv[2])+1) :
|
|
generate_dff_nreset_en( sys.argv[1], b, sys.argv[3] );
|
|
else:
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength";
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)";
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength");
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_gate_stack_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_gate_stack_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_gate_stack_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_gate_stack_gen.py 2024-01-11 13:11:01.848395430 +0100
|
|
@@ -16,27 +16,27 @@ import sys;
|
|
fab = "gf_14"
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -87,13 +87,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
def generate_gate_stack ( gatename, rows,signature, vert) :
|
|
if (vert) :
|
|
@@ -135,38 +135,38 @@ def generate_gate_stack ( gatename, rows
|
|
if len(sys.argv) == 4 :
|
|
if sys.argv[2].isdigit() :
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],1);
|
|
elif (sys.argv[2][0]=="-") :
|
|
for x in range(1,-(int(sys.argv[2]))+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],0);
|
|
|
|
elif len(sys.argv) == 5 :
|
|
signature=sys.argv[3]
|
|
num_inputs = signature.count('#') - 2;
|
|
input_params = ["input [width_p-1:0] i"+str(x) for x in range(0,num_inputs)]
|
|
- print '''
|
|
+ print('''
|
|
|
|
module bsg_'''+sys.argv[4],'''#(width_p="inv",harden_p=1)
|
|
('''+"\n ,".join(input_params)+'''
|
|
, output [width_p-1:0] o
|
|
);
|
|
-'''
|
|
+''')
|
|
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print ''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
+ print(''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
begin:macro
|
|
bsg_rp_gf_14_'''+sys.argv[1]+'''_b'''+str(x)+''' gate(.*);
|
|
end
|
|
- else ''';
|
|
- print '''
|
|
+ else ''');
|
|
+ print('''
|
|
begin: notmacro
|
|
initial assert(0!=1) else $error("%m unsupported gatestack size",width_p);
|
|
end
|
|
|
|
endmodule
|
|
-'''
|
|
+''')
|
|
else :
|
|
- print "Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size"
|
|
- print " bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist"
|
|
+ print("Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size")
|
|
+ print(" bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_mux_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_mux_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_mux_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_mux_gen.py 2024-01-11 13:11:02.315055915 +0100
|
|
@@ -23,27 +23,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -74,13 +74,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -131,7 +131,7 @@ def generate_mux_shift ( inputs, bits):
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range (0,bits) :
|
|
|
|
@@ -149,7 +149,7 @@ def generate_mux_shift ( inputs, bits):
|
|
column=column+1;
|
|
|
|
for g in range(left,left+right) :
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(joiner
|
|
@@ -184,5 +184,5 @@ def generate_mux_shift ( inputs, bits):
|
|
if len(sys.argv) == 3 :
|
|
generate_mux_shift (int(sys.argv[1]), int(sys.argv[2]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " inputs bits";
|
|
+ print("Usage: " + sys.argv[0] + " inputs bits");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_reduce_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_reduce_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_reduce_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_misc/bsg_reduce_gen.py 2024-01-11 13:11:01.725063730 +0100
|
|
@@ -2,7 +2,7 @@
|
|
|
|
import sys;
|
|
|
|
-print '''
|
|
+print('''
|
|
|
|
module bsg_rp_gf_14_reduce_and_b4 (input [3:0] i, output o);
|
|
wire [1:0] lo;
|
|
@@ -91,4 +91,4 @@ SC7P5T_ND4X2_SSC14SL bCDEF (.A(i[12]),
|
|
endmodule
|
|
|
|
|
|
-''';
|
|
+''');
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_gen.py 2024-01-11 13:11:02.441720904 +0100
|
|
@@ -24,27 +24,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -75,13 +75,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -113,19 +113,19 @@ def generate_fifo_shift_array ( words, b
|
|
emit_rp_group_begin("fifo_shift")
|
|
|
|
for w in range (0,words+1) :
|
|
- print "wire " + ",".join([ident_name_word_bit("reg",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("reg",w,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
- print "assign " + access_bit("data_o",b)+ " = ", ident_name_word_bit("reg",0,b) + ";";
|
|
+ print("assign " + access_bit("data_o",b)+ " = ", ident_name_word_bit("reg",0,b) + ";");
|
|
|
|
- for w in reversed(range (0,words)) :
|
|
+ for w in reversed(list(range(0,words))) :
|
|
|
|
for g in [1, 2, 0] :
|
|
if (g != 1 or w < words-1) :
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit_port("a2",w,b,g) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit_port("a2",w,b,g) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range (0,bits) :
|
|
# we put the selects first on these gates because
|
|
@@ -160,7 +160,7 @@ def generate_fifo_shift_array ( words, b
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("a3",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a3",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
if (w < words - 1) :
|
|
emit_gate_instance(nand3
|
|
@@ -201,5 +201,5 @@ def generate_fifo_shift_array ( words, b
|
|
if len(sys.argv) == 3 :
|
|
generate_fifo_shift_array (int(sys.argv[1]), int(sys.argv[2]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " words bits";
|
|
+ print("Usage: " + sys.argv[0] + " words bits");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_rf_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_rf_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_rf_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_rf_gen.py 2024-01-11 13:11:03.415041346 +0100
|
|
@@ -17,27 +17,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -68,13 +68,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -125,7 +125,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -139,7 +139,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -188,7 +188,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -202,7 +202,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -262,7 +262,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
emit_wire_definition(ident_name_bit("data_i_inv",b));
|
|
emit_rp_fill(str(column) +" 0 UX")
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";");
|
|
for w in range (0,words) :
|
|
emit_gate_instance(dffe
|
|
,[ ident_name_word_bit("reg",w,b)
|
|
@@ -292,7 +292,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
# AOI22 every pair of words
|
|
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";");
|
|
|
|
for w in range (0,words,2) :
|
|
queue_gate_instance(gate_dict, aoi22
|
|
@@ -348,7 +348,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
, w+(15 if (words > 16) else 13)
|
|
);
|
|
|
|
- print "\n";
|
|
+ print("\n");
|
|
# add inverters to data in, and data out.
|
|
# these are on opposite sides of the array
|
|
# we may potentially pay in delay, but we get
|
|
@@ -372,9 +372,9 @@ def generate_Nr1w_array ( words, bits, r
|
|
# since we are using rp_fill commands
|
|
# but it makes things more readable
|
|
|
|
- for x in sorted(gate_dict.items(), key=lambda x: x[1]) :
|
|
+ for x in sorted(list(gate_dict.items()), key=lambda x: x[1]) :
|
|
emit_rp_fill( str(column) +" "+str(x[1])+" UX")
|
|
- print x[0], "// ",x[1];
|
|
+ print(x[0], "// ",x[1]);
|
|
column=column+1
|
|
|
|
|
|
@@ -384,5 +384,5 @@ def generate_Nr1w_array ( words, bits, r
|
|
if len(sys.argv) == 4 :
|
|
generate_Nr1w_array (int(sys.argv[1]), int(sys.argv[2]), int(sys.argv[3]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " words bits readports";
|
|
+ print("Usage: " + sys.argv[0] + " words bits readports");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_gen.py 2024-01-11 13:11:04.155031544 +0100
|
|
@@ -6,27 +6,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -57,16 +57,16 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def rp_fill_string (params) :
|
|
return "// synopsys rp_fill (" + params + ")"
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -153,6 +153,6 @@ else :
|
|
for b in range (1,int(sys.argv[2])+1) :
|
|
generate_dff_nreset_en( sys.argv[1], b, sys.argv[3] );
|
|
else:
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength";
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)";
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength");
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_gate_stack_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_gate_stack_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_gate_stack_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_gate_stack_gen.py 2024-01-11 13:11:04.521693353 +0100
|
|
@@ -16,27 +16,27 @@ import sys;
|
|
fab = "tsmc_250"
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -87,13 +87,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
def generate_gate_stack ( gatename, rows,signature, vert) :
|
|
if (vert) :
|
|
@@ -135,38 +135,38 @@ def generate_gate_stack ( gatename, rows
|
|
if len(sys.argv) == 4 :
|
|
if sys.argv[2].isdigit() :
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],1);
|
|
elif (sys.argv[2][0]=="-") :
|
|
for x in range(1,-(int(sys.argv[2]))+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],0);
|
|
|
|
elif len(sys.argv) == 5 :
|
|
signature=sys.argv[3]
|
|
num_inputs = signature.count('#') - 2;
|
|
input_params = ["input [width_p-1:0] i"+str(x) for x in range(0,num_inputs)]
|
|
- print '''
|
|
+ print('''
|
|
|
|
module bsg_'''+sys.argv[4],'''#(width_p="inv",harden_p=1)
|
|
('''+"\n ,".join(input_params)+'''
|
|
, output [width_p-1:0] o
|
|
);
|
|
-'''
|
|
+''')
|
|
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print ''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
+ print(''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
begin:macro
|
|
bsg_rp_tsmc_250_'''+sys.argv[1]+'''_b'''+str(x)+''' gate(.*);
|
|
end
|
|
- else ''';
|
|
- print '''
|
|
+ else ''');
|
|
+ print('''
|
|
begin: notmacro
|
|
initial assert(0!=1) else $error("%m unsupported gatestack size",width_p);
|
|
end
|
|
|
|
endmodule
|
|
-'''
|
|
+''')
|
|
else :
|
|
- print "Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size"
|
|
- print " bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist"
|
|
+ print("Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size")
|
|
+ print(" bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_and_csa_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_and_csa_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_and_csa_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_and_csa_gen.py 2024-01-11 13:11:04.645025053 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -129,7 +129,7 @@ def generate_and_csa_block ( rows ) :
|
|
for pos in range (0,rows) :
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " UX");
|
|
- print "wire " + ident_name_bit("and_int",pos) + ";";
|
|
+ print("wire " + ident_name_bit("and_int",pos) + ";");
|
|
|
|
emit_gate_instance(addf
|
|
, [ ident_name_word_bit("csa", pos, 0)
|
|
@@ -155,5 +155,5 @@ def generate_and_csa_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_and_csa_block(int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py 2024-01-11 13:11:05.051686334 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
# NOTE: for symmetric pins, assume that earlier ones are always faster.
|
|
@@ -130,11 +130,11 @@ def generate_booth_4_block ( rows ) :
|
|
emit_rp_group_begin("b4b")
|
|
|
|
for pos in range (0,rows) :
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " RX");
|
|
|
|
@@ -242,5 +242,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py 2024-01-11 13:11:04.778356621 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -138,11 +138,11 @@ def generate_booth_4_block ( rows ) :
|
|
for pos in range (0,rows) :
|
|
adj_pos = start_row + pos;
|
|
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
|
|
# irritatingly, we need to place at least one cell at X position 0 for it to shift everything over.
|
|
@@ -242,13 +242,13 @@ def generate_booth_4_block ( rows ) :
|
|
|
|
|
|
if (adj_pos == 0) :
|
|
- print "assign s_o[0] = SDN_i[0]; /* SDN_i[0][0] */ assign c_o[0] = 1'b0;"
|
|
+ print("assign s_o[0] = SDN_i[0]; /* SDN_i[0][0] */ assign c_o[0] = 1'b0;")
|
|
|
|
if (adj_pos == 1) :
|
|
- print "assign s_o[1] = 1'b0; assign c_o[1] = 1'b0;"
|
|
+ print("assign s_o[1] = 1'b0; assign c_o[1] = 1'b0;")
|
|
|
|
if (adj_pos == 3) :
|
|
- print "assign s_o[" + str(pos) + "] = pp_w" + str(pos) + "_b0; assign c_o[" + str(pos) + "] = 1'b0;"
|
|
+ print("assign s_o[" + str(pos) + "] = pp_w" + str(pos) + "_b0; assign c_o[" + str(pos) + "] = 1'b0;")
|
|
|
|
|
|
emit_rp_group_end("b4b")
|
|
@@ -257,5 +257,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0]
|
|
+ print("Usage: " + sys.argv[0])
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py 2024-01-11 13:11:04.915021478 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -138,24 +138,24 @@ def generate_booth_4_block ( rows ) :
|
|
|
|
for pos in range (0,rows) :
|
|
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " RX");
|
|
|
|
if (pos == 0) :
|
|
- print "assign cl_o = 1'b0;"
|
|
+ print("assign cl_o = 1'b0;")
|
|
|
|
if (pos == 7) :
|
|
- print "assign c_o[" + str(pos) + "] = 1'b0;"
|
|
- print "assign s_o[" + str(pos) + "] = 1'b1;"
|
|
+ print("assign c_o[" + str(pos) + "] = 1'b0;")
|
|
+ print("assign s_o[" + str(pos) + "] = 1'b1;")
|
|
|
|
if (pos == 6) :
|
|
- print "assign c_o[" + str(pos) + "] = 1'b0;"
|
|
+ print("assign c_o[" + str(pos) + "] = 1'b0;")
|
|
|
|
#3
|
|
if (pos < 7) :
|
|
@@ -267,5 +267,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0]
|
|
+ print("Usage: " + sys.argv[0])
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_comp42_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_comp42_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_comp42_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_comp42_gen.py 2024-01-11 13:11:05.175018033 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -126,9 +126,9 @@ def generate_c42_block ( rows ) :
|
|
emit_rp_group_begin("c42")
|
|
|
|
for pos in range (0,rows) :
|
|
- print ""
|
|
- print "wire " + ident_name_bit("s_int",pos) +";";
|
|
- print "wire " + ident_name_bit("cl_int",pos)+";";
|
|
+ print("")
|
|
+ print("wire " + ident_name_bit("s_int",pos) +";");
|
|
+ print("wire " + ident_name_bit("cl_int",pos)+";");
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " UX");
|
|
|
|
@@ -157,5 +157,5 @@ def generate_c42_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_c42_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux_gen.py 2024-01-11 13:11:04.278363243 +0100
|
|
@@ -23,27 +23,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -74,13 +74,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -127,7 +127,7 @@ def generate_mux_shift ( inputs, bits):
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range (0,bits) :
|
|
|
|
@@ -145,7 +145,7 @@ def generate_mux_shift ( inputs, bits):
|
|
column=column+1;
|
|
|
|
for g in range(left,left+right) :
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(joiner
|
|
@@ -180,5 +180,5 @@ def generate_mux_shift ( inputs, bits):
|
|
if len(sys.argv) == 3 :
|
|
generate_mux_shift (int(sys.argv[1]), int(sys.argv[2]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " inputs bits";
|
|
+ print("Usage: " + sys.argv[0] + " inputs bits");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_reduce_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_reduce_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_reduce_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_reduce_gen.py 2024-01-11 13:11:04.391695076 +0100
|
|
@@ -2,7 +2,7 @@
|
|
|
|
import sys;
|
|
|
|
-print '''
|
|
+print('''
|
|
|
|
module bsg_rp_tsmc_250_reduce_and_b4 (input [3:0] i, output o);
|
|
wire [1:0] lo;
|
|
@@ -91,4 +91,4 @@ NAND4X2 bCDEF (.A(i[12]),.B(i[13]),.C(
|
|
endmodule
|
|
|
|
|
|
-''';
|
|
+''');
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_rf_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_rf_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_rf_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_rf_gen.py 2024-01-11 13:11:02.715050617 +0100
|
|
@@ -17,27 +17,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -68,13 +68,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -132,7 +132,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -146,7 +146,7 @@ def generate_2_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_bit_port("qaoi",b,0) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -195,7 +195,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for b in range(0,bits)]) + ";");
|
|
for b in range (0,bits) :
|
|
|
|
emit_gate_instance(dffe
|
|
@@ -209,7 +209,7 @@ def generate_4_word_1r1w_array ( words,
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("qaoi",bank,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(aoi22,
|
|
@@ -269,7 +269,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
emit_wire_definition(ident_name_bit("data_i_inv",b));
|
|
emit_rp_fill(str(column) +" 0 UX")
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("q",w,b) for w in range(words)]) + ";");
|
|
for w in range (0,words) :
|
|
emit_gate_instance(dffe
|
|
,[ ident_name_word_bit("reg",w,b)
|
|
@@ -299,7 +299,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
# AOI22 every pair of words
|
|
|
|
# we generate the state first
|
|
- print "wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit_port("qaoi",w,b,p) for w in range(0,words,2)]) + ";");
|
|
|
|
for w in range (0,words,2) :
|
|
queue_gate_instance(gate_dict, aoi22
|
|
@@ -355,7 +355,7 @@ def generate_Nr1w_array ( words, bits, r
|
|
, w+(15 if (words > 16) else 13)
|
|
);
|
|
|
|
- print "\n";
|
|
+ print("\n");
|
|
# add inverters to data in, and data out.
|
|
# these are on opposite sides of the array
|
|
# we may potentially pay in delay, but we get
|
|
@@ -379,9 +379,9 @@ def generate_Nr1w_array ( words, bits, r
|
|
# since we are using rp_fill commands
|
|
# but it makes things more readable
|
|
|
|
- for x in sorted(gate_dict.items(), key=lambda x: x[1]) :
|
|
+ for x in sorted(list(gate_dict.items()), key=lambda x: x[1]) :
|
|
emit_rp_fill( str(column) +" "+str(x[1])+" UX")
|
|
- print x[0], "// ",x[1];
|
|
+ print(x[0], "// ",x[1]);
|
|
column=column+1
|
|
|
|
|
|
@@ -391,5 +391,5 @@ def generate_Nr1w_array ( words, bits, r
|
|
if len(sys.argv) == 4 :
|
|
generate_Nr1w_array (int(sys.argv[1]), int(sys.argv[2]), int(sys.argv[3]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " words bits readports";
|
|
+ print("Usage: " + sys.argv[0] + " words bits readports");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_gen.py 2024-01-11 13:11:03.925034590 +0100
|
|
@@ -6,27 +6,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -57,16 +57,16 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def rp_fill_string (params) :
|
|
return "// synopsys rp_fill (" + params + ")"
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -161,6 +161,6 @@ else :
|
|
for b in range (1,int(sys.argv[2])+1) :
|
|
generate_dff_nreset_en( sys.argv[1], b, sys.argv[3] );
|
|
else:
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength";
|
|
- print "Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)";
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength");
|
|
+ print("Usage: " + sys.argv[0] + " type " + " bits " + " strength " + "SWEEP (to go from 1..bits)");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_gate_stack_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_gate_stack_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_gate_stack_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_gate_stack_gen.py 2024-01-11 13:11:02.568385894 +0100
|
|
@@ -16,27 +16,27 @@ import sys;
|
|
fab = "tsmc_40"
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -87,13 +87,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
def generate_gate_stack ( gatename, rows,signature, vert) :
|
|
if (vert) :
|
|
@@ -135,38 +135,38 @@ def generate_gate_stack ( gatename, rows
|
|
if len(sys.argv) == 4 :
|
|
if sys.argv[2].isdigit() :
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],1);
|
|
elif (sys.argv[2][0]=="-") :
|
|
for x in range(1,-(int(sys.argv[2]))+1) :
|
|
- print "\n// ****************************************************** \n"
|
|
+ print("\n// ****************************************************** \n")
|
|
generate_gate_stack(sys.argv[1],x,sys.argv[3],0);
|
|
|
|
elif len(sys.argv) == 5 :
|
|
signature=sys.argv[3]
|
|
num_inputs = signature.count('#') - 2;
|
|
input_params = ["input [width_p-1:0] i"+str(x) for x in range(0,num_inputs)]
|
|
- print '''
|
|
+ print('''
|
|
|
|
module bsg_'''+sys.argv[4],'''#(width_p="inv",harden_p=1)
|
|
('''+"\n ,".join(input_params)+'''
|
|
, output [width_p-1:0] o
|
|
);
|
|
-'''
|
|
+''')
|
|
|
|
for x in range(1,int(sys.argv[2])+1) :
|
|
- print ''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
+ print(''' if (harden_p && (width_p=='''+str(x)+'''))
|
|
begin:macro
|
|
bsg_rp_tsmc_40_'''+sys.argv[1]+'''_b'''+str(x)+''' gate(.*);
|
|
end
|
|
- else ''';
|
|
- print '''
|
|
+ else ''');
|
|
+ print('''
|
|
begin: notmacro
|
|
initial assert(0!=1) else $error("%m unsupported gatestack size",width_p);
|
|
end
|
|
|
|
endmodule
|
|
-'''
|
|
+''')
|
|
else :
|
|
- print "Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size"
|
|
- print " bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist"
|
|
+ print("Usage: bsg_gate_stack_gen.py AND2X1 32 > bsg_and_stacks.v # generate each individual netlist of each size")
|
|
+ print(" bsg_gate_stack_gen.py AND2X1 32 and > bsg_and.v # generate the verilog function that thunks to the right netlist")
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_and_csa_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_and_csa_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_and_csa_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_and_csa_gen.py 2024-01-11 13:11:03.801702891 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -129,7 +129,7 @@ def generate_and_csa_block ( rows ) :
|
|
for pos in range (0,rows) :
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " UX");
|
|
- print "wire " + ident_name_bit("and_int",pos) + ";";
|
|
+ print("wire " + ident_name_bit("and_int",pos) + ";");
|
|
|
|
emit_gate_instance(addf
|
|
, [ ident_name_word_bit("csa", pos, 0)
|
|
@@ -155,5 +155,5 @@ def generate_and_csa_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_and_csa_block(int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen.py 2024-01-11 13:11:03.268376621 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
# NOTE: for symmetric pins, assume that earlier ones are always faster.
|
|
@@ -130,11 +130,11 @@ def generate_booth_4_block ( rows ) :
|
|
emit_rp_group_begin("b4b")
|
|
|
|
for pos in range (0,rows) :
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " RX");
|
|
|
|
@@ -242,5 +242,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_cornice.py 2024-01-11 13:11:03.135045055 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -138,11 +138,11 @@ def generate_booth_4_block ( rows ) :
|
|
for pos in range (0,rows) :
|
|
adj_pos = start_row + pos;
|
|
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
|
|
# irritatingly, we need to place at least one cell at X position 0 for it to shift everything over.
|
|
@@ -242,13 +242,13 @@ def generate_booth_4_block ( rows ) :
|
|
|
|
|
|
if (adj_pos == 0) :
|
|
- print "assign s_o[0] = SDN_i[0]; /* SDN_i[0][0] */ assign c_o[0] = 1'b0;"
|
|
+ print("assign s_o[0] = SDN_i[0]; /* SDN_i[0][0] */ assign c_o[0] = 1'b0;")
|
|
|
|
if (adj_pos == 1) :
|
|
- print "assign s_o[1] = 1'b0; assign c_o[1] = 1'b0;"
|
|
+ print("assign s_o[1] = 1'b0; assign c_o[1] = 1'b0;")
|
|
|
|
if (adj_pos == 3) :
|
|
- print "assign s_o[" + str(pos) + "] = pp_w" + str(pos) + "_b0; assign c_o[" + str(pos) + "] = 1'b0;"
|
|
+ print("assign s_o[" + str(pos) + "] = pp_w" + str(pos) + "_b0; assign c_o[" + str(pos) + "] = 1'b0;")
|
|
|
|
|
|
emit_rp_group_end("b4b")
|
|
@@ -257,5 +257,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0]
|
|
+ print("Usage: " + sys.argv[0])
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_booth_4_block_gen_end_cornice.py 2024-01-11 13:11:03.551706202 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -138,24 +138,24 @@ def generate_booth_4_block ( rows ) :
|
|
|
|
for pos in range (0,rows) :
|
|
|
|
- print ""
|
|
- print "wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";"
|
|
- print "wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";"
|
|
+ print("")
|
|
+ print("wire " + ",".join([ident_name_word_bit("pp",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("aoi",pos,b) for b in range(0,4)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("cl",pos,b) for b in range(0,1)])+";")
|
|
+ print("wire " + ",".join([ident_name_word_bit("s0",pos,b) for b in range(0,1)])+";")
|
|
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " RX");
|
|
|
|
if (pos == 0) :
|
|
- print "assign cl_o = 1'b0;"
|
|
+ print("assign cl_o = 1'b0;")
|
|
|
|
if (pos == 7) :
|
|
- print "assign c_o[" + str(pos) + "] = 1'b0;"
|
|
- print "assign s_o[" + str(pos) + "] = 1'b1;"
|
|
+ print("assign c_o[" + str(pos) + "] = 1'b0;")
|
|
+ print("assign s_o[" + str(pos) + "] = 1'b1;")
|
|
|
|
if (pos == 6) :
|
|
- print "assign c_o[" + str(pos) + "] = 1'b0;"
|
|
+ print("assign c_o[" + str(pos) + "] = 1'b0;")
|
|
|
|
#3
|
|
if (pos < 7) :
|
|
@@ -267,5 +267,5 @@ def generate_booth_4_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_booth_4_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0]
|
|
+ print("Usage: " + sys.argv[0])
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_comp42_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_comp42_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_comp42_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_comp42_gen.py 2024-01-11 13:11:03.678371190 +0100
|
|
@@ -14,27 +14,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + " (",
|
|
+ print("module " + name + " (", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -86,13 +86,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -126,9 +126,9 @@ def generate_c42_block ( rows ) :
|
|
emit_rp_group_begin("c42")
|
|
|
|
for pos in range (0,rows) :
|
|
- print ""
|
|
- print "wire " + ident_name_bit("s_int",pos) +";";
|
|
- print "wire " + ident_name_bit("cl_int",pos)+";";
|
|
+ print("")
|
|
+ print("wire " + ident_name_bit("s_int",pos) +";");
|
|
+ print("wire " + ident_name_bit("cl_int",pos)+";");
|
|
|
|
emit_rp_fill("0 " + str(pos*2) + " UX");
|
|
|
|
@@ -157,5 +157,5 @@ def generate_c42_block ( rows ) :
|
|
if len(sys.argv) == 2 :
|
|
generate_c42_block (int(sys.argv[1]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " rows";
|
|
+ print("Usage: " + sys.argv[0] + " rows");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux_gen.py 2024-01-11 13:11:02.998380198 +0100
|
|
@@ -23,27 +23,27 @@
|
|
import sys;
|
|
|
|
def emit_module_header (name, input_args, output_args) :
|
|
- print "module " + name + "(",
|
|
+ print("module " + name + "(", end=' ')
|
|
my_list = []
|
|
for x in input_args :
|
|
my_list.append("input "+x+"\n");
|
|
for x in output_args :
|
|
my_list.append("output "+x+"\n");
|
|
- print (" "*(len(name)+8)+",").join(my_list);
|
|
+ print((" "*(len(name)+8)+",").join(my_list));
|
|
|
|
- print ");";
|
|
+ print(");");
|
|
|
|
def emit_module_footer( ) :
|
|
- print "endmodule";
|
|
+ print("endmodule");
|
|
|
|
def emit_wire_definition (name) :
|
|
- print "wire " + name + "; "
|
|
+ print("wire " + name + "; ")
|
|
|
|
def emit_wire_definition_nocr (name) :
|
|
- print "wire " + name + "; ",
|
|
+ print("wire " + name + "; ", end=' ')
|
|
|
|
def emit_gate_instance (gate_str, arg_list ) :
|
|
- print gate_instance(gate_str,arg_list);
|
|
+ print(gate_instance(gate_str,arg_list));
|
|
|
|
def queue_gate_instance (out_dict, gate_str, arg_list, order) :
|
|
the_string = gate_instance(gate_str,arg_list)
|
|
@@ -74,13 +74,13 @@ def ident_name_bit (name,bit) :
|
|
|
|
|
|
def emit_rp_group_begin (name) :
|
|
- print "// synopsys rp_group (" + name + ")"
|
|
+ print("// synopsys rp_group (" + name + ")")
|
|
|
|
def emit_rp_group_end (name) :
|
|
- print "// synopsys rp_endgroup (" + name +")"
|
|
+ print("// synopsys rp_endgroup (" + name +")")
|
|
|
|
def emit_rp_fill (params):
|
|
- print "// synopsys rp_fill (" + params +")"
|
|
+ print("// synopsys rp_fill (" + params +")")
|
|
|
|
|
|
|
|
@@ -130,7 +130,7 @@ def generate_mux_shift ( inputs, bits):
|
|
emit_rp_fill(str(column) + " 0 UX");
|
|
column=column+1;
|
|
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range (0,bits) :
|
|
|
|
@@ -148,7 +148,7 @@ def generate_mux_shift ( inputs, bits):
|
|
column=column+1;
|
|
|
|
for g in range(left,left+right) :
|
|
- print "wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";";
|
|
+ print("wire " + ",".join([ident_name_word_bit("a2",g,b) for b in range(0,bits)]) + ";");
|
|
|
|
for b in range(0,bits) :
|
|
emit_gate_instance(joiner
|
|
@@ -183,5 +183,5 @@ def generate_mux_shift ( inputs, bits):
|
|
if len(sys.argv) == 3 :
|
|
generate_mux_shift (int(sys.argv[1]), int(sys.argv[2]));
|
|
else :
|
|
- print "Usage: " + sys.argv[0] + " inputs bits";
|
|
+ print("Usage: " + sys.argv[0] + " inputs bits");
|
|
|
|
diff --color -rupN a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_reduce_gen.py b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_reduce_gen.py
|
|
--- a/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_reduce_gen.py 2021-09-26 19:02:04.000000000 +0200
|
|
+++ b/pythondata-cpu-blackparrot-2024.04/pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_reduce_gen.py 2024-01-11 13:11:02.191724216 +0100
|
|
@@ -2,7 +2,7 @@
|
|
|
|
import sys;
|
|
|
|
-print '''
|
|
+print('''
|
|
|
|
module bsg_rp_tsmc_40_reduce_and_b4 (input [3:0] i, output o);
|
|
wire [1:0] lo;
|
|
@@ -91,4 +91,4 @@ ND4D2BWP bCDEF (.A1(i[12]),.A2(i[13]),
|
|
endmodule
|
|
|
|
|
|
-''';
|
|
+''');
|