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6e14169d7f
See https://mail.kde.org/pipermail/distributions/2024-July/001511.html. Signed-off-by: Sam James <sam@gentoo.org>
148 lines
5.7 KiB
Diff
148 lines
5.7 KiB
Diff
https://mail.kde.org/pipermail/distributions/2024-July/001511.html
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https://github.com/xtensor-stack/xsimd/commit/96edf0340492fa9c080f5182b38358ca85baef5e
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From 96edf0340492fa9c080f5182b38358ca85baef5e Mon Sep 17 00:00:00 2001
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From: Dmitry Kazakov <dimula73@gmail.com>
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Date: Tue, 28 May 2024 22:21:08 +0200
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Subject: [PATCH] Fix detection of SSE/AVX/AVX512 when they are explicitly
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disabled by OS
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Some CPU vulnerability mitigations may disable AVX functionality
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on the hardware level via the XCR0 register. We should check that
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manually to verify that OS actually allows us to use this feature.
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See https://bugs.kde.org/show_bug.cgi?id=484622
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Fix #1025
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---
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include/xsimd/config/xsimd_cpuid.hpp | 91 ++++++++++++++++++++++------
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1 file changed, 72 insertions(+), 19 deletions(-)
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diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
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index f22089bac..6dda3be09 100644
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--- a/include/xsimd/config/xsimd_cpuid.hpp
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+++ b/include/xsimd/config/xsimd_cpuid.hpp
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@@ -114,6 +114,35 @@ namespace xsimd
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#endif
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#elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
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+
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+ auto get_xcr0_low = []() noexcept
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+ {
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+ uint32_t xcr0;
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+
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+#if defined(_MSC_VER) && _MSC_VER >= 1400
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+
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+ xcr0 = (uint32_t)_xgetbv(0);
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+
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+#elif defined(__GNUC__)
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+
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+ __asm__(
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+ "xorl %%ecx, %%ecx\n"
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+ "xgetbv\n"
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+ : "=a"(xcr0)
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+ :
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+#if defined(__i386__)
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+ : "ecx", "edx"
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+#else
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+ : "rcx", "rdx"
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+#endif
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+ );
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+
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+#else /* _MSC_VER < 1400 */
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+#error "_MSC_VER < 1400 is not supported"
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+#endif /* _MSC_VER && _MSC_VER >= 1400 */
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+ return xcr0;
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+ };
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+
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auto get_cpuid = [](int reg[4], int level, int count = 0) noexcept
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{
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@@ -148,19 +177,43 @@ namespace xsimd
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get_cpuid(regs1, 0x1);
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- sse2 = regs1[3] >> 26 & 1;
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- sse3 = regs1[2] >> 0 & 1;
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- ssse3 = regs1[2] >> 9 & 1;
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- sse4_1 = regs1[2] >> 19 & 1;
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- sse4_2 = regs1[2] >> 20 & 1;
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- fma3_sse42 = regs1[2] >> 12 & 1;
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+ // OS can explicitly disable the usage of SSE/AVX extensions
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+ // by setting an appropriate flag in CR0 register
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+ //
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+ // https://docs.kernel.org/admin-guide/hw-vuln/gather_data_sampling.html
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+
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+ unsigned sse_state_os_enabled = 1;
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+ unsigned avx_state_os_enabled = 1;
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+ unsigned avx512_state_os_enabled = 1;
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+
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+ // OSXSAVE: A value of 1 indicates that the OS has set CR4.OSXSAVE[bit
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+ // 18] to enable XSETBV/XGETBV instructions to access XCR0 and
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+ // to support processor extended state management using
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+ // XSAVE/XRSTOR.
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+ bool osxsave = regs1[2] >> 27 & 1;
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+ if (osxsave)
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+ {
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+
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+ uint32_t xcr0 = get_xcr0_low();
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+
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+ sse_state_os_enabled = xcr0 >> 1 & 1;
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+ avx_state_os_enabled = xcr0 >> 2 & sse_state_os_enabled;
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+ avx512_state_os_enabled = xcr0 >> 6 & avx_state_os_enabled;
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+ }
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+
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+ sse2 = regs1[3] >> 26 & sse_state_os_enabled;
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+ sse3 = regs1[2] >> 0 & sse_state_os_enabled;
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+ ssse3 = regs1[2] >> 9 & sse_state_os_enabled;
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+ sse4_1 = regs1[2] >> 19 & sse_state_os_enabled;
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+ sse4_2 = regs1[2] >> 20 & sse_state_os_enabled;
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+ fma3_sse42 = regs1[2] >> 12 & sse_state_os_enabled;
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- avx = regs1[2] >> 28 & 1;
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+ avx = regs1[2] >> 28 & avx_state_os_enabled;
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fma3_avx = avx && fma3_sse42;
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int regs8[4];
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get_cpuid(regs8, 0x80000001);
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- fma4 = regs8[2] >> 16 & 1;
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+ fma4 = regs8[2] >> 16 & avx_state_os_enabled;
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// sse4a = regs[2] >> 6 & 1;
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@@ -168,23 +221,23 @@ namespace xsimd
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int regs7[4];
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get_cpuid(regs7, 0x7);
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- avx2 = regs7[1] >> 5 & 1;
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+ avx2 = regs7[1] >> 5 & avx_state_os_enabled;
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int regs7a[4];
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get_cpuid(regs7a, 0x7, 0x1);
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- avxvnni = regs7a[0] >> 4 & 1;
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+ avxvnni = regs7a[0] >> 4 & avx_state_os_enabled;
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fma3_avx2 = avx2 && fma3_sse42;
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- avx512f = regs7[1] >> 16 & 1;
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- avx512cd = regs7[1] >> 28 & 1;
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- avx512dq = regs7[1] >> 17 & 1;
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- avx512bw = regs7[1] >> 30 & 1;
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- avx512er = regs7[1] >> 27 & 1;
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- avx512pf = regs7[1] >> 26 & 1;
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- avx512ifma = regs7[1] >> 21 & 1;
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- avx512vbmi = regs7[2] >> 1 & 1;
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- avx512vnni_bw = regs7[2] >> 11 & 1;
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+ avx512f = regs7[1] >> 16 & avx512_state_os_enabled;
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+ avx512cd = regs7[1] >> 28 & avx512_state_os_enabled;
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+ avx512dq = regs7[1] >> 17 & avx512_state_os_enabled;
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+ avx512bw = regs7[1] >> 30 & avx512_state_os_enabled;
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+ avx512er = regs7[1] >> 27 & avx512_state_os_enabled;
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+ avx512pf = regs7[1] >> 26 & avx512_state_os_enabled;
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+ avx512ifma = regs7[1] >> 21 & avx512_state_os_enabled;
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+ avx512vbmi = regs7[2] >> 1 & avx512_state_os_enabled;
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+ avx512vnni_bw = regs7[2] >> 11 & avx512_state_os_enabled;
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avx512vnni_vbmi = avx512vbmi && avx512vnni_bw;
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#endif
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}
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